From 5b2ba41f56e6202b030a842e6c2f1e74ba25111e Mon Sep 17 00:00:00 2001 From: Reinier van der Walle <walle@astron.nl> Date: Thu, 17 Sep 2020 09:36:14 +0200 Subject: [PATCH] Not using tb_lofar2_unb2b_filterbank_full.vhd --- .../tb_lofar2_unb2b_filterbank_full.vhd | 166 ------------------ 1 file changed, 166 deletions(-) delete mode 100644 applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/tb_lofar2_unb2b_filterbank_full.vhd diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/tb_lofar2_unb2b_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/tb_lofar2_unb2b_filterbank_full.vhd deleted file mode 100644 index 14b5c0e4ca..0000000000 --- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/tb_lofar2_unb2b_filterbank_full.vhd +++ /dev/null @@ -1,166 +0,0 @@ -------------------------------------------------------------------------------- --- --- Copyright 2020 --- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> --- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- -------------------------------------------------------------------------------- - - --- Author: Jonathan Hargreaves --- Purpose: Tb to show that lofar2_unb2b_filterbank_full can simulate --- Description: --- Must use c_sim = TRUE to speed up simulation --- This is a compile-only test bench --- Usage: --- Load sim # check that design can load in vsim --- > as 10 # check that the hierarchy for g_design_name is complete --- > run -a # check that design can simulate some us without error - -LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE common_lib.common_pkg.ALL; -USE unb2b_board_lib.unb2b_board_pkg.ALL; -USE common_lib.tb_common_pkg.ALL; - -ENTITY tb_lofar2_unb2b_filterbank_full IS -END tb_lofar2_unb2b_filterbank_full; - -ARCHITECTURE tb OF tb_lofar2_unb2b_filterbank_full IS - - CONSTANT c_sim : BOOLEAN := TRUE; - CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0 - CONSTANT c_node_nr : NATURAL := 0; -- Back node 3 - CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; - CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; - CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0); - - CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard - CONSTANT c_ext_clk_period : TIME := 5 ns; - CONSTANT c_bck_ref_clk_period : TIME := 5 ns; - CONSTANT c_pps_period : NATURAL := 1000; - - -- Tb - SIGNAL tb_end : STD_LOGIC := '0'; - SIGNAL sim_done : STD_LOGIC := '0'; - - -- DUT - SIGNAL ext_clk : STD_LOGIC := '0'; - SIGNAL pps : STD_LOGIC := '0'; - SIGNAL pps_rst : STD_LOGIC := '0'; - - SIGNAL WDI : STD_LOGIC; - SIGNAL INTA : STD_LOGIC; - SIGNAL INTB : STD_LOGIC; - - SIGNAL eth_clk : STD_LOGIC := '0'; - SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0); - SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0); - - SIGNAL sens_scl : STD_LOGIC; - SIGNAL sens_sda : STD_LOGIC; - SIGNAL pmbus_scl : STD_LOGIC; - SIGNAL pmbus_sda : STD_LOGIC; - - -- back transceivers - SIGNAL bck_rx : STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b); - SIGNAL bck_ref_clk : STD_LOGIC := '1'; - - -- jesd204b syncronization signals - SIGNAL jesd204b_sysref : STD_LOGIC; - SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0); - - -BEGIN - - - ---------------------------------------------------------------------------- - -- System setup - ---------------------------------------------------------------------------- - ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz) - eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz) - bck_ref_clk <= NOT bck_ref_clk AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz) - - INTA <= 'H'; -- pull up - INTB <= 'H'; -- pull up - - sens_scl <= 'H'; -- pull up - sens_sda <= 'H'; -- pull up - pmbus_scl <= 'H'; -- pull up - pmbus_sda <= 'H'; -- pull up - - ------------------------------------------------------------------------------ - -- External PPS - ------------------------------------------------------------------------------ - proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps); - jesd204b_sysref <= pps; - - ------------------------------------------------------------------------------ - -- DUT - ------------------------------------------------------------------------------ - u_lofar_unb2b_filterbank_full : ENTITY work.lofar2_unb2b_filterbank_full - GENERIC MAP ( - g_sim => c_sim, - g_sim_unb_nr => c_unb_nr, - g_sim_node_nr => c_node_nr - ) - PORT MAP ( - -- GENERAL - CLK => ext_clk, - PPS => pps, - WDI => WDI, - INTA => INTA, - INTB => INTB, - - -- Others - VERSION => c_version, - ID => c_id, - TESTIO => open, - - -- I2C Interface to Sensors - SENS_SC => sens_scl, - SENS_SD => sens_sda, - - PMBUS_SC => pmbus_scl, - PMBUS_SD => pmbus_sda, - PMBUS_ALERT => open, - - -- 1GbE Control Interface - ETH_CLK => eth_clk, - ETH_SGIN => eth_rxp, - ETH_SGOUT => eth_txp, - - -- LEDs - QSFP_LED => open, - - -- back transceivers - BCK_RX => bck_rx, - BCK_REF_CLK => bck_ref_clk, - - -- jesd204b syncronization signals - JESD204B_SYSREF => jesd204b_sysref, - JESD204B_SYNC_N => jesd204b_sync_n - ); - - - ------------------------------------------------------------------------------ - -- Simulation end - ------------------------------------------------------------------------------ - sim_done <= '0', '1' AFTER 1 us; - - proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end); - -END tb; -- GitLab