diff --git a/applications/unb1_correlator/src/vhdl/unb1_correlator.vhd b/applications/unb1_correlator/src/vhdl/unb1_correlator.vhd
index 24fea53e47976c93ce5849eb0e17d750ba81e5f5..453c9825c72f3d2d20f5f36d62526658d17c192f 100644
--- a/applications/unb1_correlator/src/vhdl/unb1_correlator.vhd
+++ b/applications/unb1_correlator/src/vhdl/unb1_correlator.vhd
@@ -117,7 +117,9 @@ ARCHITECTURE str OF unb1_correlator IS
 
   -- Correlator
   CONSTANT c_nof_inputs             : NATURAL := 24;
-  CONSTANT c_nof_pre_mult_folds     : NATURAL := 1; 
+  CONSTANT c_nof_input_folds        : NATURAL := 1;
+  CONSTANT c_nof_input_streams      : NATURAL := c_nof_inputs / pow2(c_nof_input_folds);
+  CONSTANT c_nof_pre_mult_folds     : NATURAL := 1;
   CONSTANT c_complex_data_w         : NATURAL := 8;
   CONSTANT c_conjugate              : BOOLEAN := TRUE;
   CONSTANT c_nof_channels           : NATURAL := 64;
@@ -126,10 +128,10 @@ ARCHITECTURE str OF unb1_correlator IS
   CONSTANT c_nof_visibilities       : NATURAL := (c_nof_inputs*(c_nof_inputs+1))/2;
 
   -- Gap size on the correlator input depends on the number of folds
-  CONSTANT c_block_period           : NATURAL := pow2(c_nof_pre_mult_folds);
+  CONSTANT c_block_period           : NATURAL := 1; --pow2(c_nof_pre_mult_folds);  -- To do: figure out the block period as function of both folding factors.
 
   -- Block generator
-  CONSTANT c_bg_block_size          : NATURAL := c_nof_channels;
+  CONSTANT c_bg_block_size          : NATURAL := c_nof_channels*pow2(c_nof_input_folds);
   CONSTANT c_bg_gapsize             : NATURAL := c_bg_block_size*(c_block_period-1);
 
   -- Indicate the integration period with the sync. In the correlator, the
@@ -148,12 +150,12 @@ ARCHITECTURE str OF unb1_correlator IS
                                                           TO_UVEC(   c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
                                                           TO_UVEC(                   0, c_diag_bg_bsn_init_w));
 
-  SIGNAL block_gen_src_out_arr      : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
+  SIGNAL block_gen_src_out_arr      : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
 
-  SIGNAL dp_fifo_sc_src_out_arr     : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
-  SIGNAL dp_fifo_sc_src_in_arr      : t_dp_siso_arr(c_nof_inputs-1 DOWNTO 0);
+  SIGNAL dp_fifo_sc_src_out_arr     : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
+  SIGNAL dp_fifo_sc_src_in_arr      : t_dp_siso_arr(c_nof_input_streams-1 DOWNTO 0);
 
-  SIGNAL correlator_snk_in_arr      : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
+  SIGNAL correlator_snk_in_arr      : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
   SIGNAL correlator_src_out_arr     : t_dp_sosi_arr(1-1 DOWNTO 0);
 
   SIGNAL ram_diag_data_buf_mosi     : t_mem_mosi;
@@ -172,10 +174,10 @@ BEGIN
   -----------------------------------------------------------------------------
   u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
   GENERIC MAP (
-    g_nof_output_streams => c_nof_inputs,
+    g_nof_output_streams => c_nof_input_streams,
     g_buf_dat_w          => 2*c_complex_data_w,
     g_buf_addr_w         => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
-    g_file_name_prefix   => "../../../libraries/dsp/correlator/src/hex/complex_subbands_" & NATURAL'IMAGE(c_complex_data_w),
+    g_file_name_prefix   => "../../../libraries/dsp/correlator/src/hex/complex_subbands_" & NATURAL'IMAGE(c_complex_data_w) & "b_" & "fold_" & NATURAL'IMAGE(c_nof_input_folds),
     g_diag_block_gen_rst => c_bg_ctrl
   )
   PORT MAP (
@@ -194,13 +196,13 @@ BEGIN
   -- . We'll use FIFO buffers and dp_gap to read out the FIFOs to introduce
   --   gaps.
   -----------------------------------------------------------------------------
-  gen_dp_fifo_sc : FOR i IN 0 TO c_nof_inputs-1 GENERATE
+  gen_dp_fifo_sc : FOR i IN 0 TO c_nof_input_streams-1 GENERATE
     u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
     GENERIC MAP (
       g_data_w         => 2*c_complex_data_w,
       g_use_ctrl       => FALSE,
       g_use_complex    => TRUE,
-      g_fifo_size      => c_nof_channels,
+      g_fifo_size      => c_bg_block_size,
       g_fifo_af_margin => 0
     )
     PORT MAP (
@@ -218,7 +220,7 @@ BEGIN
     );
   END GENERATE;
 
-  gen_dp_src_out_timer : FOR i IN 0 TO c_nof_inputs-1 GENERATE
+  gen_dp_src_out_timer : FOR i IN 0 TO c_nof_input_streams-1 GENERATE
     u_dp_src_out_timer : ENTITY dp_lib.dp_src_out_timer
     GENERIC MAP (
       g_block_period => c_block_period
@@ -239,7 +241,8 @@ BEGIN
   -----------------------------------------------------------------------------
   u_correlator : ENTITY correlator_lib.correlator
   GENERIC MAP (
-    g_nof_inputs         => c_nof_inputs,
+    g_nof_input_streams  => c_nof_input_streams,
+    g_nof_input_folds    => c_nof_input_folds,
     g_nof_pre_mult_folds => c_nof_pre_mult_folds,
     g_data_w             => c_complex_data_w,
     g_conjugate          => c_conjugate,