diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
index 61812414dc6f7bf6babbeb9aacec140d3c4960e9..936d476512175590a501899544c8c54330d3e584 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
@@ -55,8 +55,9 @@ ENTITY dp_block_from_mm_dc IS
 END dp_block_from_mm_dc;
 
 ARCHITECTURE rtl OF dp_block_from_mm_dc IS 
-  CONSTANT c_fifo_size : NATURAL := 1024;  -- 512 * 2 = 1024 words.
-  CONSTANT c_start_addr_w : NATURAL := 30;
+  CONSTANT c_packet_size : NATURAL := 1024;  -- 512 * 2 = 1024 words.
+  CONSTANT c_fifo_size : NATURAL := c_packet_size * 2;
+  CONSTANT c_start_addr_w : NATURAL := 29;
   SIGNAL fifo_sosi : t_dp_sosi := c_dp_sosi_rst;
   SIGNAL fifo_siso : t_dp_siso;
   SIGNAL mm_start_pulse : STD_LOGIC := '0';
@@ -95,6 +96,7 @@ BEGIN
   GENERIC MAP (
     g_use_dual_clock => TRUE,
     g_data_w         => c_word_w,
+    g_fifo_fill      => c_packet_size,
     g_fifo_size      => c_fifo_size
   )
   PORT MAP (