diff --git a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board_v1_fpga_device_family.jpg b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board_v1_fpga_device_family.jpg
deleted file mode 100644
index cbe907cf5705a8d93e7725dc5bbc6ba8cf66e27f..0000000000000000000000000000000000000000
Binary files a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board_v1_fpga_device_family.jpg and /dev/null differ
diff --git a/boards/uniboard2/libraries/unb2_board/quartus/unb2a_board.qsf b/boards/uniboard2/libraries/unb2_board/quartus/unb2a_board.qsf
deleted file mode 100644
index bfee21d190540c1387812aaf8cdca87941c1a60c..0000000000000000000000000000000000000000
--- a/boards/uniboard2/libraries/unb2_board/quartus/unb2a_board.qsf
+++ /dev/null
@@ -1,115 +0,0 @@
-###############################################################################
-#
-# Copyright (C) 2014
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-###############################################################################
-
-# This QSF is sourced by other design QSF files.
-# ==============================================
-# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
-
-set_parameter -name g_technology c_tech_arria10_e3sge3
-
-# Device:
-set_global_assignment -name FAMILY "Arria 10"
-set_global_assignment -name DEVICE 10AX115U4F45E3SGE3
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.8 V"
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-#set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
-#set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 4
-set_global_assignment -name ENABLE_OCT_DONE OFF
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
-#set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X1"
-set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQL1024
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 1.8V
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
-#set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_12_5MHZ
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_25MHZ
-#set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
-
-set_global_assignment -name USER_START_UP_CLOCK OFF
-
-set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932
-
-set_global_assignment -name HEX_FILE pm_uc_ES1_ww05p1.hex
-set_global_assignment -name SOURCE_FILE quartus.ini
-
-#set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "IBIS (Signal Integrity)"
-#set_global_assignment -name EDA_OUTPUT_DATA_FORMAT IBIS -section_id eda_board_design_signal_integrity
-#set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 5P0 -section_id eda_board_design_signal_integrity
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-
-
-# Optimize for performance:
-set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
-set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
-
-# To set a location assignment for a PLL, do the following:
-# - after compilation, open the chip planner
-# - hover over the ATX PLL block (left side or right side)
-# - Right click and click "Copy tooltip"
-# - Paste text in here and edit
-#set_location_assignment HSSIPMALCPLL_X0_Y33_N29 -to "unb2_test:u_revision|unb2_board_10gbe:\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:\gen_phy_24:u_ip_arria10_transceiver_pll_10g_0|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst"
-
-
-
-#set_parameter -name dbg_user_identifier 1 -to "\\Generate_XCVR_LANE_INSTANCES:1:xcvr_lane_inst|xcvr_txrx_inst|xcvr_native_a10_0"
-#set_parameter -name dbg_user_identifier 0 -to "\\Generate_XCVR_LANE_INSTANCES:0:xcvr_lane_inst|xcvr_pll_inst|xcvr_atx_pll_a10_0"
-#set_parameter -name dbg_user_identifier 1 -to "\\Generate_XCVR_LANE_INSTANCES:1:xcvr_lane_inst|xcvr_pll_inst|xcvr_atx_pll_a10_0"
-
-set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_0|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_phy_10gbase_r_12:\\gen_phy_12:u_ip_arria10_phy_10gbase_r_12"
-set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_1|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_phy_10gbase_r_12:\\gen_phy_12:u_ip_arria10_phy_10gbase_r_12"
-
-set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_0|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0"
-set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_1|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0"
-
-
-# Pass compile stamps as generics (passed to top-level when $UNB_COMPILE_STAMPS is set)
-if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
-  set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
-  set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
-  post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_SVN_REVISION)"
-  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""] 
-}
-
diff --git a/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl b/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
index 9437c56ae86a4a803878c98e96a95090aab15246..f0e1fcbcc2838bca140bbe67dfdcb1c17ac639ec 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
@@ -19,4 +19,4 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2a_minimal_pins.tcl
+source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
index 2369223fb833489a6934a063855bdc34e8739306..5c2f947727694406247c5cd973408505915cc092 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
@@ -19,19 +19,19 @@
 --
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, unb2_board_lib, mm_lib;
+LIBRARY IEEE, common_lib, unb2a_board_lib, mm_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE unb2_board_lib.unb2_board_pkg.ALL;
-USE unb2_board_lib.unb2_board_peripherals_pkg.ALL;
+USE unb2a_board_lib.unb2_board_pkg.ALL;
+USE unb2a_board_lib.unb2_board_peripherals_pkg.ALL;
 USE mm_lib.mm_file_pkg.ALL;
 USE mm_lib.mm_file_unb_pkg.ALL;
-USE work.qsys_unb2_minimal_pkg.ALL;
+USE work.qsys_unb2a_minimal_pkg.ALL;
 
 
-ENTITY mmm_unb2_minimal IS
+ENTITY mmm_unb2a_minimal IS
   GENERIC (
     g_sim         : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O
     g_sim_unb_nr  : NATURAL := 0;
@@ -99,9 +99,9 @@ ENTITY mmm_unb2_minimal IS
     reg_remu_mosi            : OUT t_mem_mosi;
     reg_remu_miso            : IN  t_mem_miso
   );
-END mmm_unb2_minimal;
+END mmm_unb2a_minimal;
 
-ARCHITECTURE str OF mmm_unb2_minimal IS
+ARCHITECTURE str OF mmm_unb2a_minimal IS
 
   CONSTANT c_sim_node_nr   : NATURAL := g_sim_node_nr;
   CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
@@ -174,7 +174,7 @@ BEGIN
   -- QSYS for synthesis
   ----------------------------------------------------------------------------
   gen_qsys : IF g_sim = FALSE GENERATE
-    u_qsys : qsys_unb2_minimal
+    u_qsys : qsys_unb2a_minimal
     PORT MAP (
 
       clk_clk                                   => mm_clk,
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
index 0c1cd8ba6d162512032ed19af47170c117615983..b9d9769ba92e710d008ff45113183f9efa6811a0 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
@@ -22,13 +22,13 @@
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 
-PACKAGE qsys_unb2_minimal_pkg IS
+PACKAGE qsys_unb2a_minimal_pkg IS
 
     -----------------------------------------------------------------------------
     -- this component declaration is copy-pasted from Quartus v14 QSYS builder
     -----------------------------------------------------------------------------
 
-    component qsys_unb2_minimal is
+    component qsys_unb2a_minimal is
         port (
             avs_eth_0_clk_export               : out std_logic;                                        -- export
             avs_eth_0_irq_export               : in  std_logic                     := 'X';             -- export
@@ -151,6 +151,6 @@ PACKAGE qsys_unb2_minimal_pkg IS
             reg_unb_pmbus_clk_export           : out std_logic;                                        -- export
             reg_unb_pmbus_reset_export         : out std_logic                                         -- export
         );
-    end component qsys_unb2_minimal;
+    end component qsys_unb2a_minimal;
 
-END qsys_unb2_minimal_pkg;
+END qsys_unb2a_minimal_pkg;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
index ea4cf89b162146551fd48e0d1c8c80394acf4c5c..53b99265afed9feeda9b0554d6db51ac9919210d 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
@@ -20,19 +20,19 @@
 --
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, unb2_board_lib, technology_lib;
+LIBRARY IEEE, common_lib, unb2a_board_lib, technology_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE technology_lib.technology_pkg.ALL;
-USE unb2_board_lib.unb2_board_pkg.ALL;
+USE unb2a_board_lib.unb2_board_pkg.ALL;
 
-ENTITY unb2_minimal IS
+ENTITY unb2a_minimal IS
   GENERIC (
-    g_design_name   : STRING  := "unb2_minimal";
+    g_design_name   : STRING  := "unb2a_minimal";
     g_design_note   : STRING  := "UNUSED";
-    g_technology    : NATURAL := c_tech_arria10;
+    g_technology    : NATURAL := c_tech_arria10_e3sge3;
     g_sim           : BOOLEAN := FALSE; --Overridden by TB
     g_sim_unb_nr    : NATURAL := 0;
     g_sim_node_nr   : NATURAL := 0;
@@ -69,10 +69,10 @@ ENTITY unb2_minimal IS
 
     QSFP_LED     : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
   );
-END unb2_minimal;
+END unb2a_minimal;
 
 
-ARCHITECTURE str OF unb2_minimal IS
+ARCHITECTURE str OF unb2a_minimal IS
 
   -- Firmware version x.y
   CONSTANT c_fw_version             : t_unb2_board_fw_version := (1, 1);
@@ -159,7 +159,7 @@ BEGIN
   -----------------------------------------------------------------------------
   -- General control function
   -----------------------------------------------------------------------------
-  u_ctrl : ENTITY unb2_board_lib.ctrl_unb2_board
+  u_ctrl : ENTITY unb2a_board_lib.ctrl_unb2_board
   GENERIC MAP (
     g_sim           => g_sim,
     g_technology    => g_technology,
@@ -280,7 +280,7 @@ BEGIN
   -----------------------------------------------------------------------------
   -- MM master
   -----------------------------------------------------------------------------
-  u_mmm : ENTITY work.mmm_unb2_minimal
+  u_mmm : ENTITY work.mmm_unb2a_minimal
   GENERIC MAP (
     g_sim         => g_sim,
     g_sim_unb_nr  => g_sim_unb_nr,
@@ -351,7 +351,7 @@ BEGIN
     reg_remu_miso            => reg_remu_miso
   );
 
-  u_front_led : ENTITY unb2_board_lib.unb2_board_qsfp_leds
+  u_front_led : ENTITY unb2a_board_lib.unb2_board_qsfp_leds
   GENERIC MAP (
     g_sim           => g_sim,
     g_factory_image => g_factory_image,
@@ -365,7 +365,7 @@ BEGIN
     red_led_arr     => qsfp_red_led_arr
   );
 
-  u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
+  u_front_io : ENTITY unb2a_board_lib.unb2_board_front_io
   GENERIC MAP (
     g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
   )
diff --git a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
index 8bc8b42190fa6b3653504a57ec4533f1df9ea37a..33fc00ac959fff53117681035173446d9793d5d3 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
@@ -20,7 +20,7 @@
 --
 -------------------------------------------------------------------------------
 
--- Purpose: Test bench for unb2_minimal.
+-- Purpose: Test bench for unb2a_minimal.
 -- Description:
 --   The DUT can be targeted at unb 0, node 3 with the same Python scripts 
 --   that are used on hardware. 
@@ -29,10 +29,10 @@
 --     > run_modelsim & (to start Modeslim)
 --
 --   In Modelsim do:
---     > lp unb2_minimal
+--     > lp unb2a_minimal
 --     > mk clean all (only first time to clean all libraries)
---     > mk all (to compile all libraries that are needed for unb2_minimal)
---     . load tb_unb1_minimal simulation by double clicking the tb_unb2_minimal icon
+--     > mk all (to compile all libraries that are needed for unb2a_minimal)
+--     . load tb_unb1_minimal simulation by double clicking the tb_unb2a_minimal icon
 --     > as 10 (to view signals in Wave Window)
 --     > run 100 us (or run -all)
 --
@@ -42,22 +42,22 @@
 --     > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
 --
 
-LIBRARY IEEE, common_lib, unb2_board_lib, i2c_lib;
+LIBRARY IEEE, common_lib, unb2a_board_lib, i2c_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE common_lib.common_pkg.ALL;
-USE unb2_board_lib.unb2_board_pkg.ALL;
+USE unb2a_board_lib.unb2_board_pkg.ALL;
 USE common_lib.tb_common_pkg.ALL;
 
-ENTITY tb_unb2_minimal IS
+ENTITY tb_unb2a_minimal IS
     GENERIC (
-      g_design_name : STRING  := "unb2_minimal";
+      g_design_name : STRING  := "unb2a_minimal";
       g_sim_unb_nr  : NATURAL := 0; -- UniBoard 0
       g_sim_node_nr : NATURAL := 3  -- Node 3
     );
-END tb_unb2_minimal;
+END tb_unb2a_minimal;
 
-ARCHITECTURE tb OF tb_unb2_minimal IS
+ARCHITECTURE tb OF tb_unb2a_minimal IS
 
   CONSTANT c_sim             : BOOLEAN := TRUE;
 
@@ -144,7 +144,7 @@ BEGIN
   ------------------------------------------------------------------------------
   -- DUT
   ------------------------------------------------------------------------------
-  u_unb2_minimal : ENTITY work.unb2_minimal
+  u_unb2a_minimal : ENTITY work.unb2a_minimal
     GENERIC MAP (
       g_sim         => c_sim,
       g_sim_unb_nr  => c_unb_nr,
diff --git a/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg b/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg
index 68389f080ce4cf76f20db809c089e9a61518d4fb..e4e3e89a26d499e78267c41173d6998588ce283d 100644
--- a/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg
+++ b/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg
@@ -1,9 +1,9 @@
-hdl_lib_name = unb2_board
-hdl_library_clause_name = unb2_board_lib
+hdl_lib_name = unb2a_board
+hdl_library_clause_name = unb2a_board_lib
 hdl_lib_uses_synth = common dp ppsh i2c eth remu technology tech_clkbuf tech_pll tech_fractional_pll epcs fpga_sense
 hdl_lib_uses_sim = 
 
-hdl_lib_technology = ip_arria10
+hdl_lib_technology = ip_arria10_e3sge3
 
 synth_files =
     src/vhdl/unb2_board_pkg.vhd
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board.qsf b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board.qsf
deleted file mode 100644
index 577051cd04ca496483104ac833348cdca94c10c4..0000000000000000000000000000000000000000
--- a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board.qsf
+++ /dev/null
@@ -1,113 +0,0 @@
-###############################################################################
-#
-# Copyright (C) 2014
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-###############################################################################
-
-# This QSF is sourced by other design QSF files.
-# ==============================================
-# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
-
-# Device:
-set_global_assignment -name FAMILY "Arria 10"
-set_global_assignment -name DEVICE 10AX115U4F45I3SGES
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.8 V"
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-#set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
-#set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 4
-set_global_assignment -name ENABLE_OCT_DONE OFF
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
-#set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X1"
-set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQL1024
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 1.8V
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
-#set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_12_5MHZ
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_25MHZ
-#set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
-
-set_global_assignment -name USER_START_UP_CLOCK OFF
-
-set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932
-
-set_global_assignment -name HEX_FILE pm_uc_ES1_ww05p1.hex
-set_global_assignment -name SOURCE_FILE quartus.ini
-
-#set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "IBIS (Signal Integrity)"
-#set_global_assignment -name EDA_OUTPUT_DATA_FORMAT IBIS -section_id eda_board_design_signal_integrity
-#set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 5P0 -section_id eda_board_design_signal_integrity
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-
-
-# Optimize for performance:
-set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
-set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
-
-# To set a location assignment for a PLL, do the following:
-# - after compilation, open the chip planner
-# - hover over the ATX PLL block (left side or right side)
-# - Right click and click "Copy tooltip"
-# - Paste text in here and edit
-#set_location_assignment HSSIPMALCPLL_X0_Y33_N29 -to "unb2_test:u_revision|unb2_board_10gbe:\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:\gen_phy_24:u_ip_arria10_transceiver_pll_10g_0|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst"
-
-
-
-#set_parameter -name dbg_user_identifier 1 -to "\\Generate_XCVR_LANE_INSTANCES:1:xcvr_lane_inst|xcvr_txrx_inst|xcvr_native_a10_0"
-#set_parameter -name dbg_user_identifier 0 -to "\\Generate_XCVR_LANE_INSTANCES:0:xcvr_lane_inst|xcvr_pll_inst|xcvr_atx_pll_a10_0"
-#set_parameter -name dbg_user_identifier 1 -to "\\Generate_XCVR_LANE_INSTANCES:1:xcvr_lane_inst|xcvr_pll_inst|xcvr_atx_pll_a10_0"
-
-set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_0|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_phy_10gbase_r_12:\\gen_phy_12:u_ip_arria10_phy_10gbase_r_12"
-set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_1|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_phy_10gbase_r_12:\\gen_phy_12:u_ip_arria10_phy_10gbase_r_12"
-
-set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_0|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0"
-set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_1|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0"
-
-
-# Pass compile stamps as generics (passed to top-level when $UNB_COMPILE_STAMPS is set)
-if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
-  set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
-  set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
-  post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_SVN_REVISION)"
-  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""] 
-}
-
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board_v0_fpga_device_family.JPG b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board_v0_fpga_device_family.JPG
deleted file mode 100644
index f50d11684f4abad160db1a44556541c969d49e6e..0000000000000000000000000000000000000000
Binary files a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board_v0_fpga_device_family.JPG and /dev/null differ
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board.sdc b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
similarity index 100%
rename from boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board.sdc
rename to boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc