diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd index 283f85b15b74f86ce8441551947bbbde776497cd..2ec8cf8a8fa8cfb76cfaf82742ecdb759d8a2833 100644 --- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd +++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd @@ -33,44 +33,44 @@ PACKAGE tech_mac_10g_component_pkg IS -- Copied from entity $RADIOHDL/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd COMPONENT ip_stratixiv_mac_10g IS - PORT ( - csr_clk_clk : in std_logic := '0'; -- csr_clk.clk - csr_reset_reset_n : in std_logic := '0'; -- csr_reset.reset_n - csr_address : in std_logic_vector(12 downto 0) := (others => '0'); -- csr.address - csr_waitrequest : out std_logic; -- .waitrequest - csr_read : in std_logic := '0'; -- .read - csr_readdata : out std_logic_vector(31 downto 0); -- .readdata - csr_write : in std_logic := '0'; -- .write - csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata - tx_clk_clk : in std_logic := '0'; -- tx_clk.clk - tx_reset_reset_n : in std_logic := '0'; -- tx_reset.reset_n - avalon_st_tx_startofpacket : in std_logic := '0'; -- avalon_st_tx.startofpacket - avalon_st_tx_valid : in std_logic := '0'; -- .valid - avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data - avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty - avalon_st_tx_ready : out std_logic; -- .ready - avalon_st_tx_error : in std_logic_vector(0 downto 0) := (others => '0'); -- .error - avalon_st_tx_endofpacket : in std_logic := '0'; -- .endofpacket - avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_st_pause.data - xgmii_tx_data : out std_logic_vector(71 downto 0); -- xgmii_tx.data - avalon_st_txstatus_valid : out std_logic; -- avalon_st_txstatus.valid - avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- .data - avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- .error - rx_clk_clk : in std_logic := '0'; -- rx_clk.clk - rx_reset_reset_n : in std_logic := '0'; -- rx_reset.reset_n - xgmii_rx_data : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_rx.data - avalon_st_rx_startofpacket : out std_logic; -- avalon_st_rx.startofpacket - avalon_st_rx_endofpacket : out std_logic; -- .endofpacket - avalon_st_rx_valid : out std_logic; -- .valid - avalon_st_rx_ready : in std_logic := '0'; -- .ready - avalon_st_rx_data : out std_logic_vector(63 downto 0); -- .data - avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- .empty - avalon_st_rx_error : out std_logic_vector(5 downto 0); -- .error - avalon_st_rxstatus_valid : out std_logic; -- avalon_st_rxstatus.valid - avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- .data - avalon_st_rxstatus_error : out std_logic_vector(6 downto 0); -- .error - link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0) -- link_fault_status_xgmii_rx.data - ); + PORT ( + csr_clk_clk : in std_logic := '0'; -- csr_clk.clk + csr_reset_reset_n : in std_logic := '0'; -- csr_reset.reset_n + csr_address : in std_logic_vector(12 downto 0) := (others => '0'); -- csr.address + csr_waitrequest : out std_logic; -- .waitrequest + csr_read : in std_logic := '0'; -- .read + csr_readdata : out std_logic_vector(31 downto 0); -- .readdata + csr_write : in std_logic := '0'; -- .write + csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata + tx_clk_clk : in std_logic := '0'; -- tx_clk.clk + tx_reset_reset_n : in std_logic := '0'; -- tx_reset.reset_n + avalon_st_tx_startofpacket : in std_logic := '0'; -- avalon_st_tx.startofpacket + avalon_st_tx_valid : in std_logic := '0'; -- .valid + avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data + avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty + avalon_st_tx_ready : out std_logic; -- .ready + avalon_st_tx_error : in std_logic_vector(0 downto 0) := (others => '0'); -- .error + avalon_st_tx_endofpacket : in std_logic := '0'; -- .endofpacket + avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_st_pause.data + xgmii_tx_data : out std_logic_vector(71 downto 0); -- xgmii_tx.data + avalon_st_txstatus_valid : out std_logic; -- avalon_st_txstatus.valid + avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- .data + avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- .error + rx_clk_clk : in std_logic := '0'; -- rx_clk.clk + rx_reset_reset_n : in std_logic := '0'; -- rx_reset.reset_n + xgmii_rx_data : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_rx.data + avalon_st_rx_startofpacket : out std_logic; -- avalon_st_rx.startofpacket + avalon_st_rx_endofpacket : out std_logic; -- .endofpacket + avalon_st_rx_valid : out std_logic; -- .valid + avalon_st_rx_ready : in std_logic := '0'; -- .ready + avalon_st_rx_data : out std_logic_vector(63 downto 0); -- .data + avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- .empty + avalon_st_rx_error : out std_logic_vector(5 downto 0); -- .error + avalon_st_rxstatus_valid : out std_logic; -- avalon_st_rxstatus.valid + avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- .data + avalon_st_rxstatus_error : out std_logic_vector(6 downto 0); -- .error + link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0) -- link_fault_status_xgmii_rx.data + ); END COMPONENT; @@ -80,48 +80,48 @@ PACKAGE tech_mac_10g_component_pkg IS -- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/mac_10g/ip/generated/sim/ip_arria10_mac_10g.vhd COMPONENT ip_arria10_mac_10g_top IS - PORT ( - csr_read : in std_logic := '0'; -- csr.read - csr_write : in std_logic := '0'; -- .write - csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata - csr_readdata : out std_logic_vector(31 downto 0); -- .readdata - csr_waitrequest : out std_logic; -- .waitrequest - csr_address : in std_logic_vector(12 downto 0) := (others => '0'); -- .address - tx_312_5_clk : in std_logic := '0'; -- tx_312_5_clk.clk - tx_156_25_clk : in std_logic := '0'; -- tx_156_25_clk.clk - rx_312_5_clk : in std_logic := '0'; -- rx_312_5_clk.clk - rx_156_25_clk : in std_logic := '0'; -- rx_156_25_clk.clk - csr_clk : in std_logic := '0'; -- csr_clk.clk - csr_rst_n : in std_logic := '0'; -- csr_rst_n.reset_n - tx_rst_n : in std_logic := '0'; -- tx_rst_n.reset_n - rx_rst_n : in std_logic := '0'; -- rx_rst_n.reset_n - avalon_st_tx_startofpacket : in std_logic := '0'; -- avalon_st_tx.startofpacket - avalon_st_tx_endofpacket : in std_logic := '0'; -- .endofpacket - avalon_st_tx_valid : in std_logic := '0'; -- .valid - avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data - avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty - avalon_st_tx_error : in std_logic := '0'; -- .error - avalon_st_tx_ready : out std_logic; -- .ready - avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_st_pause.data - xgmii_tx : out std_logic_vector(71 downto 0); -- xgmii_tx.data - avalon_st_txstatus_valid : out std_logic; -- avalon_st_txstatus.valid - avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- .data - avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- .error - xgmii_rx : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_rx.data - link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0); -- link_fault_status_xgmii_rx.data - avalon_st_rx_data : out std_logic_vector(63 downto 0); -- avalon_st_rx.data - avalon_st_rx_startofpacket : out std_logic; -- .startofpacket - avalon_st_rx_valid : out std_logic; -- .valid - avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- .empty - avalon_st_rx_error : out std_logic_vector(5 downto 0); -- .error - avalon_st_rx_ready : in std_logic := '0'; -- .ready - avalon_st_rx_endofpacket : out std_logic; -- .endofpacket - avalon_st_rxstatus_valid : out std_logic; -- avalon_st_rxstatus.valid - avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- .data - avalon_st_rxstatus_error : out std_logic_vector(6 downto 0); -- .error - unidirectional_en : out std_logic; -- unidirectional.en - unidirectional_remote_fault_dis : out std_logic -- .remote_fault_dis - ); + PORT ( + csr_read : in std_logic := '0'; -- csr.read + csr_write : in std_logic := '0'; -- .write + csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata + csr_readdata : out std_logic_vector(31 downto 0); -- .readdata + csr_waitrequest : out std_logic; -- .waitrequest + csr_address : in std_logic_vector(12 downto 0) := (others => '0'); -- .address + tx_312_5_clk : in std_logic := '0'; -- tx_312_5_clk.clk + tx_156_25_clk : in std_logic := '0'; -- tx_156_25_clk.clk + rx_312_5_clk : in std_logic := '0'; -- rx_312_5_clk.clk + rx_156_25_clk : in std_logic := '0'; -- rx_156_25_clk.clk + csr_clk : in std_logic := '0'; -- csr_clk.clk + csr_rst_n : in std_logic := '0'; -- csr_rst_n.reset_n + tx_rst_n : in std_logic := '0'; -- tx_rst_n.reset_n + rx_rst_n : in std_logic := '0'; -- rx_rst_n.reset_n + avalon_st_tx_startofpacket : in std_logic := '0'; -- avalon_st_tx.startofpacket + avalon_st_tx_endofpacket : in std_logic := '0'; -- .endofpacket + avalon_st_tx_valid : in std_logic := '0'; -- .valid + avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data + avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty + avalon_st_tx_error : in std_logic := '0'; -- .error + avalon_st_tx_ready : out std_logic; -- .ready + avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_st_pause.data + xgmii_tx : out std_logic_vector(71 downto 0); -- xgmii_tx.data + avalon_st_txstatus_valid : out std_logic; -- avalon_st_txstatus.valid + avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- .data + avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- .error + xgmii_rx : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_rx.data + link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0); -- link_fault_status_xgmii_rx.data + avalon_st_rx_data : out std_logic_vector(63 downto 0); -- avalon_st_rx.data + avalon_st_rx_startofpacket : out std_logic; -- .startofpacket + avalon_st_rx_valid : out std_logic; -- .valid + avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- .empty + avalon_st_rx_error : out std_logic_vector(5 downto 0); -- .error + avalon_st_rx_ready : in std_logic := '0'; -- .ready + avalon_st_rx_endofpacket : out std_logic; -- .endofpacket + avalon_st_rxstatus_valid : out std_logic; -- avalon_st_rxstatus.valid + avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- .data + avalon_st_rxstatus_error : out std_logic_vector(6 downto 0); -- .error + unidirectional_en : out std_logic; -- unidirectional.en + unidirectional_remote_fault_dis : out std_logic -- .remote_fault_dis + ); END COMPONENT; END tech_mac_10g_component_pkg;