diff --git a/libraries/dsp/st/src/vhdl/st_histogram.vhd b/libraries/dsp/st/src/vhdl/st_histogram.vhd
index c2c117e3905daaaeec6c1bb376e2ad3deee65ecb..dca3a04862e6cc0fb323297ba4caebb0e30d067b 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram.vhd
@@ -32,10 +32,13 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY st_histogram IS
PORT (
- dp_rst : IN STD_LOGIC;
- dp_clk : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
- snk_in : IN t_dp_sosi
+ snk_in : IN t_dp_sosi;
+
+ ram_mosi : IN t_mem_mosi;
+ ram_miso : OUT t_mem_miso
);
END st_histogram;
@@ -46,6 +49,14 @@ ARCHITECTURE rtl OF st_histogram IS
CONSTANT c_in_data_w : NATURAL := 8;
CONSTANT c_adr_low : NATURAL := c_in_data_w-8; -- 0
+ -------------------------------------------------------------------------------
+ -- ram_pointer
+ -------------------------------------------------------------------------------
+ SIGNAL toggle_ram_pointer : STD_LOGIC;
+ SIGNAL nxt_toggle_ram_pointer : STD_LOGIC;
+ SIGNAL ram_pointer : STD_LOGIC;
+ SIGNAL prv_ram_pointer : STD_LOGIC;
+
-------------------------------------------------------------------------------
-- bin_reader
-------------------------------------------------------------------------------
@@ -83,8 +94,6 @@ ARCHITECTURE rtl OF st_histogram IS
dat_w => c_word_w, -- 32b, def. in common_pkg; >= c_bin_w
nof_dat => c_nof_bins, -- 256 adresses with 32b words
init_sl => '0');
-
- SIGNAL ram_pointer : STD_LOGIC;
SIGNAL common_ram_r_w_wr_mosi_arr : t_mem_mosi_arr(1 DOWNTO 0);
SIGNAL common_ram_r_w_rd_mosi_arr : t_mem_mosi_arr(1 DOWNTO 0);
@@ -96,10 +105,36 @@ ARCHITECTURE rtl OF st_histogram IS
BEGIN
+ -------------------------------------------------------------------------------
+ -- ram_pointer: Keep track of what RAM to target
+ -- . Target either RAM 0 or 1 per sync period
+ -- . RD/WR sides of RAM have shifted sync periods due to rd>wr latency
+ -- . e.g. a new sync period is read while an old sync period is written
+ -- . Solution: treat the RAM pointer as MS address bit
+ -- . ram_pointer is synchronous to snk_in.sync
+ -------------------------------------------------------------------------------
+ p_ram_pointer : PROCESS(dp_rst, dp_clk) IS
+ BEGIN
+ IF dp_rst='1' THEN
+ prv_ram_pointer <= '0';
+ toggle_ram_pointer <= '0';
+ ELSIF RISING_EDGE(dp_clk) THEN
+ toggle_ram_pointer <= nxt_toggle_ram_pointer;
+ prv_ram_pointer <= ram_pointer;
+ END IF;
+ END PROCESS;
+
+ -- Don't toggle the RAM pointer on the first sync as we're already reading the RAM at that point.
+ nxt_toggle_ram_pointer <= '1' WHEN snk_in.sync='1' ELSE toggle_ram_pointer;
+ -- Toggle the RAM pointer starting from 2nd sync onwards
+ ram_pointer <= NOT prv_ram_pointer WHEN snk_in.sync='1' AND toggle_ram_pointer='1' ELSE prv_ram_pointer;
+
+
-------------------------------------------------------------------------------
-- bin_reader : reads bin from RAM, sends bin + count to bin_writer.
-- . Input : snk_in (input data stream)
-- bin_reader_miso (reply to RAM read request: rddata = bin count)
+ -- ram_pointer (to put in MOSI buses as MS address bit)
-- . Output : bin_reader_mosi (RAM read request, address = bin)
-- bin_reader_to_writer_mosi (address = bin, wrdata = bin count)
-------------------------------------------------------------------------------
@@ -107,7 +142,7 @@ BEGIN
bin_reader_mosi.wrdata <= (OTHERS=>'0');
bin_reader_mosi.wr <= '0';
bin_reader_mosi.rd <= snk_in.valid;
- bin_reader_mosi.address <= RESIZE_UVEC(snk_in.data(c_in_data_w-1 DOWNTO c_adr_low), 32);
+ bin_reader_mosi.address <= RESIZE_UVEC(ram_pointer & snk_in.data(c_in_data_w-1 DOWNTO c_adr_low), 32);
-- Store the rd address as bin_writer needs to know where to write the bin count
p_prv_rd_address : PROCESS(dp_clk, dp_rst) IS
@@ -190,17 +225,19 @@ BEGIN
-- histogram_wr_mosi (on user side, auto clears RAM every sync)
-- . Output: histogram_rd_miso (carries the bins the user wants to read)
-- bin_arbiter_miso (carries then bins the bin_reader wants to read)
+ -- . Note: the ram_pointer is carried (with different latencies) as MSbit in:
+ -- . bin_arbiter_wr_mosi.address
+ -- . bin_arbiter_rd_mosi.address
-------------------------------------------------------------------------------
- ram_pointer <= '0'; --FIXME This needs to be somehow tied to snk_in.sync.
-
+
-- Let bin_arbiter write RAM 0 while user reads RAM 1 and vice versa
- common_ram_r_w_wr_mosi_arr(0) <= bin_arbiter_wr_mosi WHEN ram_pointer='0' ELSE histogram_wr_mosi;
- common_ram_r_w_rd_mosi_arr(0) <= bin_arbiter_rd_mosi WHEN ram_pointer='0' ELSE histogram_rd_mosi;
- common_ram_r_w_wr_mosi_arr(1) <= bin_arbiter_wr_mosi WHEN ram_pointer='1' ELSE histogram_wr_mosi;
- common_ram_r_w_rd_mosi_arr(1) <= bin_arbiter_rd_mosi WHEN ram_pointer='1' ELSE histogram_rd_mosi;
+ common_ram_r_w_wr_mosi_arr(0) <= bin_arbiter_wr_mosi WHEN bin_arbiter_wr_mosi.address(8)='0' ELSE histogram_wr_mosi; --FIXME (8) is not generic
+ common_ram_r_w_rd_mosi_arr(0) <= bin_arbiter_rd_mosi WHEN bin_arbiter_rd_mosi.address(8)='0' ELSE histogram_rd_mosi;
+ common_ram_r_w_wr_mosi_arr(1) <= bin_arbiter_wr_mosi WHEN bin_arbiter_wr_mosi.address(8)='1' ELSE histogram_wr_mosi;
+ common_ram_r_w_rd_mosi_arr(1) <= bin_arbiter_rd_mosi WHEN bin_arbiter_rd_mosi.address(8)='0' ELSE histogram_rd_mosi;
-- Let bin_arbiter read RAM 0 while user reads RAM 1 and vice versa
- bin_arbiter_rd_miso <= common_ram_r_w_rd_miso_arr(0) WHEN ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(1);
+ bin_arbiter_rd_miso <= common_ram_r_w_rd_miso_arr(0) WHEN ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(1); --FIXME ISSUE: The MISO has 1 cycle more latency than the MOSI (which carries the ram_pointer)
histogram_rd_miso <= common_ram_r_w_rd_miso_arr(1) WHEN ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(0);
gen_common_ram_r_w : FOR i IN 0 TO c_nof_common_ram_r_w-1 GENERATE
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
index 06f9e1d117789d68315998402bcc690b6ff4c9f7..d7c9262be84b3366f794833099721e76a471cf1f 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
@@ -397,11 +397,11 @@ BEGIN
dp_clk => dp_clk,
-- Streaming
- snk_in => st_histogram_snk_in
+ snk_in => st_histogram_snk_in,
-- Memory Mapped
--- sla_in_ram_mosi => c_mem_mosi_rst,-- sla_in_
--- sla_out_ram_miso => st_histogram_ram_miso, --OPEN -- sla_out_
+ ram_mosi => c_mem_mosi_rst, -- sla_in_
+ ram_miso => st_histogram_ram_miso --OPEN -- sla_out_
-- dbg_ram_miso => st_histogram_dbg_ram_miso
);
diff --git a/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd
index 15c4f2fddae29e9d2f00dd172de76c904ecff142..5463e0c575b2d4b713966a40738ae5c1a5346ea3 100644
--- a/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd
@@ -54,7 +54,7 @@ BEGIN
-- do test for different number of bins
u_tb_st_histogram_counter_nof_2 : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 1, 2, 200, "true" , "counter" );
u_tb_st_histogram_counter_nof_4 : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 2, 4, 200, "true" , "counter" );
-u_tb_st_histogram_counter : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 4, 8, 200, "true" , "counter" );
+u_tb_st_histogram_counter : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 8, 8, 200, "true" , "counter" );
-- do tests for RAM delay issues
u_tb_st_histogram_toggle : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 4, 8, 200, "true" , "toggle" );