diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
index 794f823ec30b620bf176d89dbcfffae62681eab0..56b129b4e69aa6be573df00246a42940f7d6ba4c 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
@@ -73,12 +73,12 @@ BEGIN
mm_mosi.address <= TO_MEM_ADDRESS(start_address + r.word_index + r.step_index);
- out_sosi.data <= RESIZE_DP_DATA(mm_miso.rddata);
+ out_sosi.data <= RESIZE_DP_DATA(mm_miso.rddata(c_word_w-1 DOWNTO 0));
out_sosi.valid <= mm_miso.rdval; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
out_sosi.sop <= r.sop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop
out_sosi.eop <= r.eop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop
- mm_done <= not r.busy;
+ mm_done <= d.eop;
p_reg : PROCESS(rst, clk)
BEGIN
@@ -117,7 +117,7 @@ BEGIN
END IF;
-- check end of block
- IF r.step_index >= c_mem_size THEN -- use d rather than r to have easier end of block condition
+ IF r.step_index >= c_mem_size THEN
d.eop <= '1';
-- prepare for next block
d.busy <= '0';
diff --git a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
index ed847f9d39dfe2b917b1f7684b0974e3fd6e5f1c..29929f9e4339760988579f9026bc03dbf395d0b8 100644
--- a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
@@ -42,10 +42,8 @@ ENTITY dp_block_to_mm IS
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
start_address : IN NATURAL RANGE 0 TO g_step_size * g_nof_data;
- mm_miso : IN t_mem_miso;
mm_mosi : OUT t_mem_mosi;
- in_sosi : IN t_dp_sosi;
- in_siso : OUT t_dp_siso
+ in_sosi : IN t_dp_sosi
);
END dp_block_to_mm;
@@ -55,20 +53,18 @@ ARCHITECTURE rtl OF dp_block_to_mm IS
CONSTANT c_mem_size : NATURAL := g_step_size * g_nof_data;
TYPE t_reg IS RECORD
- busy : STD_LOGIC;
wr : STD_LOGIC;
word_index : NATURAL RANGE 0 TO g_data_size-1;
step_index : NATURAL RANGE 0 TO c_mem_size;
END RECORD;
- CONSTANT c_reg_rst : t_reg := ('0', '0', 0, 0);
+ CONSTANT c_reg_rst : t_reg := ('0', 0, 0);
SIGNAL r : t_reg;
SIGNAL d : t_reg;
BEGIN
- in_siso.ready <= '1';
mm_mosi.address <= TO_MEM_ADDRESS(start_address + r.word_index + r.step_index);
mm_mosi.wrdata <= RESIZE_MEM_DATA(in_sosi.data);
mm_mosi.wr <= r.wr;
@@ -82,38 +78,28 @@ BEGIN
END IF;
END PROCESS;
- p_comb : PROCESS(r, in_sosi, d)
+ p_comb : PROCESS(r, in_sosi)
BEGIN
d <= r;
d.wr <= '0';
- -- if start of block
- IF in_sosi.sop = '1' THEN
- d.busy <= '1';
- d.word_index <= 0;
- d.step_index <= 0;
- END IF;
-
-- if end of block
IF in_sosi.eop = '1' THEN
-- prepare for next block
- d.busy <= '0';
d.word_index <= 0;
d.step_index <= 0;
END IF;
-- while receiving block
- IF r.busy = '1' THEN
- IF in_sosi.valid = '1' THEN
- -- continue with block
- IF r.step_index < c_mem_size THEN
- d.wr <= '1';
- IF r.word_index < g_data_size - 1 THEN
- d.word_index <= r.word_index + 1;
- ELSE
- d.word_index <= 0;
- d.step_index <= r.step_index + g_step_size;
- END IF;
+ IF in_sosi.valid = '1' THEN
+ -- continue with block
+ IF r.step_index < c_mem_size THEN
+ d.wr <= '1';
+ IF r.word_index < g_data_size - 1 THEN
+ d.word_index <= r.word_index + 1;
+ ELSE
+ d.word_index <= 0;
+ d.step_index <= r.step_index + g_step_size;
END IF;
END IF;
END IF;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
index 99d0ffa8bec813b95324d62d4f7ff9169efce106..ce57df42d3e73d76aa49cb9dd5a13981a9fd41cc 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
@@ -20,9 +20,19 @@
-- Author:
-- . Pieter Donker
-- Purpose:
--- . Read a block of data from memory mapped (MM) location and stream it as a block of data.
+-- . Test bench for dp_block_from_mm.vhd and dp_block_to_mm.vhd
+--
-- Description:
--- . " "
+-- . data flow:
+-- p_init_ram --> u_ram_rd --> u_dp_block_from_mm --> dp_block_to_mm --> u_ram_wr --> p_verify_read
+-- . process flow:
+-- p_init_ram --> p_transfer --> p_verify_read / p_verify_check.
+-- . p_init_ram, initializes u_ram_rd with ascending values.
+-- . p_transfer, u_dp_block_from_mm reads data (using data and step size)
+-- from u_ram_rd and stream it to u_dp_block_to_mm which write it to u_ram_wr.
+-- . p_verify_read, set ram address (using data and step size) to check and
+-- read value from ram, also set expected ram value.
+-- . p_verify_check, check if ram_value is equal to expected value.
-- --------------------------------------------------------------------------
-- > as 10
@@ -41,7 +51,7 @@ USE dp_lib.tb_dp_pkg.ALL;
ENTITY tb_dp_block_from_mm IS
GENERIC (
g_data_size : NATURAL := 2;
- g_step_size : NATURAL := 2;
+ g_step_size : NATURAL := 4;
g_nof_data : NATURAL := 512 -- 512
);
END tb_dp_block_from_mm;
@@ -52,7 +62,7 @@ ARCHITECTURE tb OF tb_dp_block_from_mm IS
CONSTANT c_ram_data_size : NATURAL := g_nof_data * g_step_size;
CONSTANT c_ram_adr_w : NATURAL := ceil_log2(c_ram_data_size);
- CONSTANT c_ram : t_c_mem := (c_mem_ram_rd_latency, c_ram_adr_w, c_word_w, 2**c_ram_adr_w, '0');
+ CONSTANT c_ram : t_c_mem := (1, c_ram_adr_w, c_word_w, 2**c_ram_adr_w, '0');
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '1';
@@ -75,11 +85,13 @@ ARCHITECTURE tb OF tb_dp_block_from_mm IS
SIGNAL ram_wr_en : STD_LOGIC := '0';
SIGNAL ram_wr_adr : STD_LOGIC_VECTOR(c_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL ram_wr_dat : STD_LOGIC_VECTOR(c_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL ram_rd_en : STD_LOGIC := '1';
+ SIGNAL ram_rd_en : STD_LOGIC := '0';
SIGNAL ram_rd_adr : STD_LOGIC_VECTOR(c_ram.adr_w-1 DOWNTO 0);
SIGNAL ram_rd_dat : STD_LOGIC_VECTOR(c_ram.dat_w-1 DOWNTO 0);
SIGNAL ram_rd_val : STD_LOGIC;
+ SIGNAL exp_data : NATURAL;
+
SIGNAL init_done : STD_LOGIC := '0';
SIGNAL transfer_done : STD_LOGIC := '0';
@@ -95,13 +107,14 @@ BEGIN
p_init_ram : PROCESS
BEGIN
+ ram_wr_en <= '0';
proc_common_wait_until_low(clk, rst);
proc_common_wait_some_cycles(clk, 10);
FOR i IN 0 TO c_ram.nof_dat-1 LOOP
ram_wr_adr <= TO_UVEC(i, c_ram.adr_w);
ram_wr_dat <= TO_UVEC(i, c_ram.dat_w);
ram_wr_en <= '1';
- proc_common_wait_some_cycles(clk, 2);
+ proc_common_wait_some_cycles(clk, 1);
END LOOP;
ram_wr_en <= '0';
@@ -111,11 +124,11 @@ BEGIN
p_transfer : PROCESS
BEGIN
- proc_common_wait_until_high(clk, init_done);
-
+ start_pulse <= '0';
start_address <= 0;
+ proc_common_wait_until_high(clk, init_done);
start_pulse <= '1';
- proc_common_wait_some_cycles(clk, 20);
+ proc_common_wait_some_cycles(clk, 1);
start_pulse <= '0';
proc_common_wait_until_high(clk, block_done);
@@ -124,18 +137,30 @@ BEGIN
END PROCESS;
- p_verify_ram : PROCESS
+ p_verify_set_ram_addr : PROCESS
+ VARIABLE v_word_index: NATURAL := 0;
+ VARIABLE v_step_index: NATURAL := 0;
+ VARIABLE v_ram_adr : NATURAL := 0;
BEGIN
+ ram_rd_en <= '0';
+ ram_rd_adr <= TO_UVEC(0 , c_ram.adr_w);
+ exp_data <= 0;
proc_common_wait_until_high(clk, transfer_done);
-
- FOR i IN 0 TO c_ram.nof_dat-1 LOOP
- ram_rd_adr <= TO_UVEC(i, c_ram.adr_w);
- ram_rd_en <= '1';
- proc_common_wait_some_cycles(clk, 1);
- ram_rd_en <= '0';
- ASSERT i = TO_UINT(ram_rd_dat) REPORT "RAM values not equal" SEVERITY ERROR;
+ WHILE v_ram_adr < c_ram.nof_dat LOOP
+ ram_rd_adr <= TO_UVEC(v_ram_adr , c_ram.adr_w);
+ ram_rd_en <= '1';
proc_common_wait_some_cycles(clk, 1);
+ exp_data <= v_ram_adr;
+
+ IF v_word_index < g_data_size-1 THEN
+ v_word_index := v_word_index + 1;
+ ELSE
+ v_word_index := 0;
+ v_step_index := v_step_index + g_step_size;
+ END IF;
+ v_ram_adr := start_address + v_step_index + v_word_index;
END LOOP;
+ ram_rd_en <= '0';
proc_common_wait_some_cycles(clk, 10);
tb_end <= '1';
@@ -143,6 +168,19 @@ BEGIN
END PROCESS;
+ p_verify_check_ram_values: PROCESS
+ BEGIN
+ proc_common_wait_until_high(clk, transfer_done);
+ WHILE tb_end = '0' LOOP
+ WAIT UNTIL rising_edge(clk);
+ IF ram_rd_val = '1' THEN
+ ASSERT exp_data = TO_UINT(ram_rd_dat) REPORT "RAM values not equal" SEVERITY ERROR;
+ END IF;
+ END LOOP;
+ WAIT;
+ END PROCESS;
+
+
-- RAM with test data
u_ram_rd: ENTITY common_lib.common_ram_r_w
GENERIC MAP (
@@ -162,7 +200,7 @@ BEGIN
-- DUT : dp_block_from_mm
- u_dut: ENTITY work.dp_block_from_mm
+ u_dp_block_from_mm: ENTITY work.dp_block_from_mm
GENERIC MAP (
g_data_size => g_data_size,
g_step_size => g_step_size,
@@ -184,7 +222,7 @@ BEGIN
);
-- convert mm back to block
- u_tets: ENTITY work.dp_block_to_mm
+ u_dp_block_to_mm: ENTITY work.dp_block_to_mm
GENERIC MAP (
g_data_size => g_data_size,
g_step_size => g_step_size,
@@ -197,10 +235,9 @@ BEGIN
start_address => start_address,
mm_mosi => wr_mosi,
- mm_miso => wr_miso,
+ --mm_miso => wr_miso,
- in_sosi => blk_sosi,
- in_siso => blk_siso
+ in_sosi => blk_sosi
);
-- RAM with converted result