diff --git a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
index fdb97c7b1131c59a73c79dab71526e3afeab94b0..8a5de786b4052024bd0433c6cc6bc5785b35137d 100644
--- a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
@@ -46,7 +46,9 @@ ENTITY tb_io_ddr IS
     g_sim_model             : BOOLEAN := TRUE;  --FALSE;
     g_technology            : NATURAL := c_tech_select_default;
     g_tech_ddr3             : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
-    g_tech_ddr4             : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
+    --g_tech_ddr4             : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
+    g_tech_ddr4             : t_c_tech_ddr := c_tech_ddr4_16g_1600m_64;
+    --g_tech_ddr4             : t_c_tech_ddr := c_tech_ddr4_16g_1600m_72_64;
     g_tb_end                : BOOLEAN := TRUE;   -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
     g_cross_domain_dvr_ctlr : BOOLEAN := TRUE;   -- when TRUE insert clock cross domain logic and also insert clock cross domain logic when g_dvr_clk_period/=c_ctlr_clk_period
     g_dvr_clk_period        : TIME := 5 ns;      -- 200 MHz