diff --git a/applications/lofar2/libraries/sdp/hdllib.cfg b/applications/lofar2/libraries/sdp/hdllib.cfg
index 843a49247a740b06c32a726543192f50f3590cc8..7068a9f4104a54a404540a09e830491c0ded6074 100644
--- a/applications/lofar2/libraries/sdp/hdllib.cfg
+++ b/applications/lofar2/libraries/sdp/hdllib.cfg
@@ -18,6 +18,7 @@ synth_files =
src/vhdl/node_sdp_adc_input_and_timing.vhd
src/vhdl/node_sdp_filterbank.vhd
src/vhdl/node_sdp_beamformer.vhd
+ src/vhdl/node_sdp_correlator.vhd
test_bench_files =
tb/vhdl/tb_sdp_info.vhd
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fa6125942137aa015fcd22f39833fecda5fed067
--- /dev/null
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -0,0 +1,296 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose:
+-- . Implements the functionality of the Subband Correlator in the
+-- LOFAR2 SDPFW design.
+-- Description:
+-- Remark:
+-- .
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.sdp_pkg.ALL;
+
+ENTITY node_sdp_correlator IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE
+ --g_offload_time : NATURAL := c_sdp_offload_time
+ );
+ PORT (
+ dp_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+
+ in_sosi_arr : IN t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ --xst_udp_sosi : OUT t_dp_sosi;
+ --xst_udp_siso : IN t_dp_siso;
+
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ reg_dp_sync_insert_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_sync_insert_v2_miso : OUT t_mem_miso;
+ reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_crosslets_info_miso : OUT t_mem_miso;
+ reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_scheduler_xsub_miso : OUT t_mem_miso;
+ ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_xsq_miso : OUT t_mem_miso;
+
+ --sdp_info : IN t_sdp_info;
+ --gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
+ --stat_eth_src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ --stat_ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ --stat_udp_src_port : IN STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0)
+
+ out_crosslets_info : OUT STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0)
+
+ );
+END node_sdp_correlator;
+
+ARCHITECTURE str OF node_sdp_correlator IS
+
+-- CONSTANT c_nof_masters : POSITIVE := 2;
+
+ -- crosslet statistics offload
+-- SIGNAL ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
+-- SIGNAL ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
+
+-- SIGNAL master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
+-- SIGNAL master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
+-- SIGNAL master_mosi_arr : t_mem_mosi_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
+-- SIGNAL master_miso_arr : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
+
+ SIGNAL quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL xin_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL xsel_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL crosslets_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL crosslets_mosi_arr : t_mem_mosi_arr(0 TO 0) := (OTHERS=>c_mem_mosi_rst); -- (0 TO c_sdp_P_sq-1)
+ SIGNAL crosslets_miso_arr : t_mem_miso_arr(0 TO 0) := (OTHERS=>c_mem_miso_rst); -- (0 TO c_sdp_P_sq-1)
+
+BEGIN
+ ---------------------------------------------------------------
+ -- Requantize 18b to 16b
+ ---------------------------------------------------------------
+ gen_requantize : FOR I IN 0 TO c_sdp_P_pfb-1 GENERATE
+ u_dp_requantize : ENTITY dp_lib.dp_requantize
+ GENERIC MAP (
+ g_complex => TRUE,
+ g_representation => "SIGNED",
+ g_lsb_w => 0,
+ g_lsb_round => TRUE,
+ g_lsb_round_clip => FALSE,
+ g_msb_clip => TRUE,
+ g_msb_clip_symmetric => FALSE,
+ g_in_dat_w => c_sdp_W_subband,
+ g_out_dat_w => c_sdp_W_crosslet
+ )
+ PORT MAP(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => in_sosi_arr(I),
+ src_out => quant_sosi_arr(I)
+ );
+ END GENERATE;
+
+ ---------------------------------------------------------------
+ -- dp_sync_insert_v2
+ ---------------------------------------------------------------
+ u_dp_sync_insert_v2 : ENTITY dp_lib.dp_sync_insert_v2
+ GENERIC MAP (
+ g_nof_streams => c_sdp_P_pfb,
+ g_nof_blk_per_sync => 200000,
+ g_nof_blk_per_sync_min => 19530
+ )
+ PORT MAP (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_sync_insert_v2_mosi,
+ reg_miso => reg_dp_sync_insert_v2_miso,
+
+ in_sosi_arr => quant_sosi_arr,
+ out_sosi_arr => xin_sosi_arr
+ );
+
+ ---------------------------------------------------------------
+ -- Crosslet Subband Select
+ ---------------------------------------------------------------
+ u_crosslets_subband_select : ENTITY work.sdp_crosslets_subband_select
+ GENERIC MAP (
+ g_N_crosslets => c_sdp_N_crosslets
+ )
+ PORT MAP(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => xin_sosi_arr,
+ out_sosi => xsel_sosi,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_crosslets_info_mosi => reg_crosslets_info_mosi,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+
+ reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
+ reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+
+ out_crosslets_info => out_crosslets_info
+ );
+
+ ---------------------------------------------------------------
+ -- Repack 32b to 64b
+ ---------------------------------------------------------------
+ -- Not implemented yet
+
+ ---------------------------------------------------------------
+ -- ring_mux
+ ---------------------------------------------------------------
+ -- Not implemented yet
+
+ ---------------------------------------------------------------
+ -- Repack 64b to 32b
+ ---------------------------------------------------------------
+ -- Not implemented yet
+
+ ---------------------------------------------------------------
+ -- dp_demux
+ ---------------------------------------------------------------
+ -- Not implemented yet
+
+ ---------------------------------------------------------------
+ -- dp_bsn_aligner_v2 Not implemented yet, using st_xsq_dp_to_mm as a replacement
+ ---------------------------------------------------------------
+ u_st_xsq_dp_to_mm : ENTITY st_lib.st_xsq_dp_to_mm
+ GENERIC MAP(
+ g_nof_crosslets => c_sdp_N_crosslets,
+ g_nof_signal_inputs => c_sdp_S_pn,
+ g_dsp_data_w => c_sdp_W_crosslet
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ in_sosi => xsel_sosi,
+ out_sosi_info => crosslets_sosi,
+
+ mm_mosi => crosslets_mosi_arr(0),
+ mm_miso => crosslets_miso_arr(0)
+ );
+
+ ---------------------------------------------------------------
+ -- Crosslets Statistics (XST)
+ ---------------------------------------------------------------
+ u_crosslets_stats : ENTITY st_lib.st_xst
+ GENERIC MAP(
+ g_nof_streams => 1, -- c_sdp_P_sq
+ g_nof_crosslets => c_sdp_N_crosslets,
+ g_nof_signal_inputs => c_sdp_S_pn,
+ g_in_data_w => c_sdp_W_crosslet,
+ g_stat_data_w => c_longword_w,
+ g_stat_data_sz => c_longword_sz/c_word_sz
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_sosi => crosslets_sosi,
+ mm_mosi_arr => crosslets_mosi_arr,
+ mm_miso_arr => crosslets_miso_arr,
+
+ ram_st_xsq_mosi => ram_st_xsq_mosi, --master_mem_mux_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso --master_mem_mux_miso
+ );
+
+-- ---------------------------------------------------------------
+-- -- MM master multiplexer
+-- ---------------------------------------------------------------
+-- -- Connect 2 mm_masters to the common_mem_mux output
+-- master_mosi_arr(0) <= ram_st_bst_mosi; -- MM access via QSYS MM bus
+-- ram_st_bst_miso <= master_miso_arr(0);
+-- master_mosi_arr(1) <= ram_st_offload_mosi; -- MM access by SST offload
+-- ram_st_offload_miso <= master_miso_arr(1);
+--
+-- u_mem_master_mux : ENTITY mm_lib.mm_master_mux
+-- GENERIC MAP (
+-- g_nof_masters => c_nof_masters,
+-- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+-- )
+-- PORT MAP (
+-- mm_clk => mm_clk,
+--
+-- master_mosi_arr => master_mosi_arr,
+-- master_miso_arr => master_miso_arr,
+-- mux_mosi => master_mem_mux_mosi,
+-- mux_miso => master_mem_mux_miso
+-- );
+--
+-- ---------------------------------------------------------------
+-- -- XST UDP offload
+-- ---------------------------------------------------------------
+-- u_sdp_bst_udp_offload: ENTITY work.sdp_statistics_offload
+-- GENERIC MAP (
+-- g_statistics_type => "XST",
+-- g_offload_time => g_offload_time,
+-- g_beamset_id => g_beamset_id
+-- )
+-- PORT MAP (
+-- mm_clk => mm_clk,
+-- mm_rst => mm_rst,
+--
+-- dp_clk => dp_clk,
+-- dp_rst => dp_rst,
+--
+-- master_mosi => ram_st_offload_mosi,
+-- master_miso => ram_st_offload_miso,
+--
+-- reg_enable_mosi => reg_stat_enable_mosi,
+-- reg_enable_miso => reg_stat_enable_miso,
+--
+-- reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+-- reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
+--
+-- sdp_info => sdp_info,
+-- gn_index => TO_UINT(gn_id),
+--
+-- in_sosi => bf_sum_sosi,
+-- out_sosi => bst_udp_sosi,
+-- out_siso => bst_udp_siso,
+--
+-- eth_src_mac => stat_eth_src_mac,
+-- udp_src_port => stat_udp_src_port,
+-- ip_src_addr => stat_ip_src_addr
+-- );
+
+
+END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index d5cb3f69e91f6301bb9431a1ed535bee7cfe08e6..a9f05b3bc51e2db98f91a3c46397d6fbdb2004f6 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -91,6 +91,7 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_W_beamlet_sum : NATURAL := 18;
CONSTANT c_sdp_W_bf_magnitude : NATURAL := 1;
CONSTANT c_sdp_W_bf_weight : NATURAL := 16;
+ CONSTANT c_sdp_W_crosslet : NATURAL := 16;
CONSTANT c_sdp_W_fir_coef : NATURAL := 16;
CONSTANT c_sdp_W_gn_id : NATURAL := 5;
CONSTANT c_sdp_W_statistic : NATURAL := 64;
diff --git a/libraries/dsp/st/hdllib.cfg b/libraries/dsp/st/hdllib.cfg
index 8b4e7ddfb49e185f428e9f73085d935dfbda8f80..02987cf05a878d6d473ef63930b6d49de9696b75 100644
--- a/libraries/dsp/st/hdllib.cfg
+++ b/libraries/dsp/st/hdllib.cfg
@@ -12,6 +12,7 @@ synth_files =
src/vhdl/st_xsq.vhd
src/vhdl/st_xsq_arr.vhd
src/vhdl/st_xsq_mm_to_dp.vhd
+ src/vhdl/st_xsq_dp_to_mm.vhd
src/vhdl/st_xst.vhd
# src/vhdl/st_top.vhd
src/vhdl/st_histogram.vhd
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd b/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d3834eeea9172db07612f79c87fc0dfc10cb9fe0
--- /dev/null
+++ b/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
@@ -0,0 +1,129 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author : R. vd Walle
+-- Purpose:
+-- . Write a block of xsq data with size (g_nof_crosslets * g_nof_signal_inputs)
+-- to RAM.
+-- Description:
+-- After every in_sosi.sop the st_xsq_dp_to_mm.vhd writes the block of data
+-- to RAM and can be read by MM.
+-- --------------------------------------------------------------------------
+
+LIBRARY IEEE,common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY st_xsq_dp_to_mm IS
+ GENERIC (
+ g_nof_crosslets : NATURAL;
+ g_nof_signal_inputs : NATURAL;
+ g_dsp_data_w : NATURAL := 16
+ );
+ PORT (
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ in_sosi : IN t_dp_sosi;
+ mm_mosi : IN t_mem_mosi;
+ mm_miso : OUT t_mem_miso;
+ out_sosi_info : OUT t_dp_sosi
+ );
+END st_xsq_dp_to_mm;
+
+
+ARCHITECTURE rtl OF st_xsq_dp_to_mm IS
+
+ CONSTANT c_nof_data : NATURAL := g_nof_crosslets * g_nof_signal_inputs;
+ CONSTANT c_mm_ram_adr_w : NATURAL := ceil_log2(c_nof_data);
+ CONSTANT c_mm_ram_dat_w : NATURAL := c_nof_complex * g_dsp_data_w;
+
+ SIGNAL ram_wr_mosi : t_mem_mosi := c_mem_mosi_rst;
+
+ SIGNAL reg_sosi_info : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL in_sosi_rewired : t_dp_sosi := c_dp_sosi_rst;
+
+BEGIN
+
+ p_in_sosi : PROCESS(in_sosi)
+ BEGIN
+ in_sosi_rewired <= in_sosi;
+ in_sosi_rewired.data(g_dsp_data_w -1 DOWNTO 0) <= in_sosi.re(g_dsp_data_w-1 DOWNTO 0);
+ in_sosi_rewired.data(c_nof_complex * g_dsp_data_w -1 DOWNTO 0) <= in_sosi.im(g_dsp_data_w-1 DOWNTO 0);
+ END PROCESS;
+
+ u_dp_block_to_mm : ENTITY dp_lib.dp_block_to_mm
+ GENERIC MAP(
+ g_data_size => 1,
+ g_step_size => 1,
+ g_nof_data => c_nof_data
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ start_address => 0,
+ mm_mosi => ram_wr_mosi,
+ in_sosi => in_sosi_rewired
+ );
+
+ u_common_paged_ram_r_w : ENTITY common_lib.common_paged_ram_r_w
+ GENERIC MAP(
+ g_data_w => c_mm_ram_dat_w,
+ g_page_sz => c_nof_data,
+ g_wr_start_page => 0,
+ g_rd_start_page => 1
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ wr_next_page => in_sosi.eop,
+ wr_adr => ram_wr_mosi.address(c_mm_ram_adr_w-1 DOWNTO 0),
+ wr_en => ram_wr_mosi.wr,
+ wr_dat => ram_wr_mosi.wrdata(c_mm_ram_dat_w-1 DOWNTO 0),
+ rd_next_page => in_sosi.eop,
+ rd_adr => mm_mosi.address(c_mm_ram_adr_w-1 DOWNTO 0),
+ rd_en => mm_mosi.rd,
+ rd_dat => mm_miso.rddata(c_mm_ram_dat_w-1 DOWNTO 0),
+ rd_val => mm_miso.rdval
+ );
+
+
+ p_control : PROCESS(rst, clk)
+ BEGIN
+ IF rst='1' THEN
+ out_sosi_info <= c_dp_sosi_rst;
+ reg_sosi_info <= c_dp_sosi_rst;
+ ELSIF rising_edge(clk) THEN
+ IF in_sosi.sop = '1' THEN
+ reg_sosi_info <= in_sosi;
+ END IF;
+ IF in_sosi.eop = '1' THEN
+ out_sosi_info <= reg_sosi_info;
+ out_sosi_info.eop <= '1';
+ out_sosi_info.err <= in_sosi.err;
+ ELSE
+ out_sosi_info <= c_dp_sosi_rst;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+END rtl;