From 586a148114a210a18c8ddc9dd3b9dcb3645f317d Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Mon, 15 Mar 2021 18:45:22 +0100
Subject: [PATCH] L2SDP-206, succelfull compile with Fmax > 200MHz
---
.../tb/vhdl/tb_lofar2_unb2b_filterbank.vhd | 2 +-
.../sdp/src/vhdl/sdp_statistics_offload.vhd | 71 ++++++++++++-------
.../base/dp/src/vhdl/dp_block_from_mm.vhd | 44 +++++++-----
.../jesd204b/ip_arria10_e1sg_jesd204b.vhd | 7 +-
4 files changed, 72 insertions(+), 52 deletions(-)
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
index 0bf899960c..b8aaf32595 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
@@ -195,7 +195,7 @@ BEGIN
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
- proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
jesd204b_sysref <= pps;
ext_pps <= pps;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index 92aaa44f89..db4e7fcded 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -126,14 +126,17 @@ ARCHITECTURE str OF sdp_statistics_offload IS
CONSTANT c_reg_rst : t_reg := (0, 0, '0', (OTHERS => '0'), (OTHERS => '0'), 0, '0', 0, 0);
- SIGNAL r : t_reg;
- SIGNAL d : t_reg;
+ SIGNAL r : t_reg;
+ SIGNAL nxt_r : t_reg;
SIGNAL trigger : STD_LOGIC := '0';
SIGNAL mm_done : STD_LOGIC := '0';
SIGNAL dp_block_from_mm_src_out : t_dp_sosi;
SIGNAL dp_block_from_mm_src_in : t_dp_siso;
+ SIGNAL dp_offload_snk_in : t_dp_sosi;
+ SIGNAL dp_offload_snk_out : t_dp_siso;
+
SIGNAL dp_header_info : STD_LOGIC_VECTOR(1023 DOWNTO 0):= (OTHERS => '0');
SIGNAL bsn_at_sync : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
@@ -175,69 +178,71 @@ BEGIN
IF dp_rst='1' THEN
r <= c_reg_rst;
ELSIF rising_edge(dp_clk) THEN
- r <= d;
+ r <= nxt_r;
END IF;
END PROCESS;
p_control_packet_offload : PROCESS(r, gn_index, in_sosi, trigger, mm_done, dp_header_info)
+ VARIABLE v: t_reg;
BEGIN
- d <= r;
- d.start_pulse <= '0';
- d.nof_cycles_dly <= gn_index * g_offload_time;
+ v := r;
+ v.start_pulse := '0';
+ v.nof_cycles_dly := gn_index * g_offload_time;
-- Count number of sop's in a sync interval and get payload errors and keep them till next sync.
IF in_sosi.sync = '1' THEN
- d.integration_interval <= r.interval_cnt;
- d.interval_cnt <= 0;
- d.payload_err <= '0';
+ v.integration_interval := r.interval_cnt;
+ v.interval_cnt := 0;
+ v.payload_err := '0';
ELSE
IF in_sosi.eop = '1' THEN
- d.payload_err <= r.payload_err OR in_sosi.err(0);
+ v.payload_err := r.payload_err OR in_sosi.err(0);
END IF;
IF in_sosi.sop = '1' THEN
- d.interval_cnt <= r.interval_cnt + 1;
+ v.interval_cnt := r.interval_cnt + 1;
END IF;
END IF;
-- assign sdp_data_id for different statistic types
IF g_statistics_type = "SST" THEN
- d.data_id <= x"000000" & TO_UVEC(r.block_count + c_sdp_S_pn * gn_index, 8);
+ v.data_id := x"000000" & TO_UVEC(r.block_count + c_sdp_S_pn * gn_index, 8);
ELSIF g_statistics_type = "BST" THEN
- d.data_id <= x"0000" & TO_UVEC(c_beamlet_id, 16);
+ v.data_id := x"0000" & TO_UVEC(c_beamlet_id, 16);
ELSIF g_statistics_type = "XST" THEN
- d.data_id <= x"00" & TO_UVEC(0, 8) & TO_UVEC(0, 8) & TO_UVEC(0, 8); -- TODO: fill in right values for XST.
+ v.data_id := x"00" & TO_UVEC(0, 8) & TO_UVEC(0, 8) & TO_UVEC(0, 8); -- TODO: fill in right values for XST.
ELSE
- d.data_id <= x"00000000";
+ v.data_id := x"00000000";
END IF;
-- Issue start_pulse per packet offload
IF trigger = '1' THEN
-- Use trigger to start first packet
- d.start_pulse <= '1';
- d.start_address <= 0;
- d.block_count <= 1;
+ v.start_pulse := '1';
+ v.start_address := 0;
+ v.block_count := 1;
ELSIF mm_done = '1' THEN
-- Use mm_done to start next packets
IF r.block_count < c_nof_packets THEN
IF r.block_count MOD c_nof_data_per_step = 0 THEN
- d.start_address <= r.start_address + c_data_size; -- step to next packet within block
+ v.start_address := r.start_address + c_data_size; -- step to next packet within block
ELSE
- d.start_address <= r.block_count / c_nof_data_per_step * c_block_size; -- jump to first packet in next block
+ v.start_address := r.block_count / c_nof_data_per_step * c_block_size; -- jump to first packet in next block
END IF;
- d.start_pulse <= '1';
- d.block_count <= r.block_count + 1;
+ v.start_pulse := '1';
+ v.block_count := r.block_count + 1;
ELSE
-- Prepare for next trigger interval.
- d.start_address <= 0;
- d.block_count <= 0;
+ v.start_address := 0;
+ v.block_count := 0;
END IF;
END IF;
-- Release header info per packet offload
IF trigger = '1' OR mm_done = '1' THEN
- d.dp_header_info <= dp_header_info;
+ v.dp_header_info := dp_header_info;
END IF;
+ nxt_r <= v;
END PROCESS;
u_mms_common_variable_delay : ENTITY common_lib.mms_common_variable_delay
@@ -274,6 +279,18 @@ BEGIN
out_siso => dp_block_from_mm_src_in
);
+ u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready
+ PORT MAP(
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => dp_block_from_mm_src_in,
+ snk_in => dp_block_from_mm_src_out,
+ -- ST source
+ src_in => dp_offload_snk_out,
+ src_out => dp_offload_snk_in
+ );
+
u_dp_offload_tx_v3: ENTITY dp_lib.dp_offload_tx_v3
GENERIC MAP (
g_nof_streams => c_nof_streams,
@@ -290,8 +307,8 @@ BEGIN
dp_clk => dp_clk,
reg_hdr_dat_mosi => reg_hdr_dat_mosi,
reg_hdr_dat_miso => reg_hdr_dat_miso,
- snk_in_arr(0) => dp_block_from_mm_src_out,
- snk_out_arr(0) => dp_block_from_mm_src_in,
+ snk_in_arr(0) => dp_offload_snk_in,
+ snk_out_arr(0) => dp_offload_snk_out,
src_out_arr(0) => out_sosi,
src_in_arr(0) => out_siso,
hdr_fields_in_arr(0) => r.dp_header_info
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
index d3b8c961bb..ca050afb70 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
@@ -66,8 +66,8 @@ ARCHITECTURE rtl OF dp_block_from_mm IS
CONSTANT c_reg_rst : t_reg := ('0', '0', '0', 0, 0);
- SIGNAL r : t_reg;
- SIGNAL d : t_reg;
+ SIGNAL r : t_reg;
+ SIGNAL nxt_r : t_reg;
SIGNAL mm_address : NATURAL := 0;
SIGNAL last_mm_address : NATURAL := 0;
BEGIN
@@ -77,10 +77,14 @@ BEGIN
mm_mosi.address <= TO_MEM_ADDRESS(mm_address);
- out_sosi.data <= RESIZE_DP_DATA(mm_miso.rddata(c_word_w-1 DOWNTO 0));
- out_sosi.valid <= mm_miso.rdval; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
- out_sosi.sop <= r.sop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop
- out_sosi.eop <= r.eop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop
+ u_sosi : PROCESS(r, mm_miso)
+ BEGIN
+ out_sosi <= c_dp_sosi_rst; -- To avoid Modelsim warnings on conversion to integer from unused fields.
+ out_sosi.data <= RESIZE_DP_DATA(mm_miso.rddata(c_word_w-1 DOWNTO 0));
+ out_sosi.valid <= mm_miso.rdval; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
+ out_sosi.sop <= r.sop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop
+ out_sosi.eop <= r.eop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop
+ END PROCESS;
mm_done <= r.eop;
@@ -89,45 +93,47 @@ BEGIN
IF rst='1' THEN
r <= c_reg_rst;
ELSIF rising_edge(clk) THEN
- r <= d;
+ r <= nxt_r;
END IF;
END PROCESS;
p_comb : PROCESS(r, start_pulse, out_siso, mm_address, last_mm_address)
+ VARIABLE v : t_reg;
BEGIN
- d <= r;
- d.sop <= '0';
- d.eop <= '0';
+ v := r;
+ v.sop := '0';
+ v.eop := '0';
mm_mosi.rd <= '0';
IF r.busy = '0' AND start_pulse = '1' THEN
-- initiate next block
- d.busy <= '1';
+ v.busy := '1';
ELSIF r.busy = '1' THEN
IF out_siso.ready = '1' THEN
-- continue with block
mm_mosi.rd <= '1';
IF r.word_index < g_data_size - 1 THEN
- d.word_index <= r.word_index + 1;
+ v.word_index := r.word_index + 1;
ELSE
- d.word_index <= 0;
- d.step_index <= r.step_index + g_step_size;
+ v.word_index := 0;
+ v.step_index := r.step_index + g_step_size;
END IF;
-- check start of block
IF r.word_index = 0 AND r.step_index = 0 THEN
- d.sop <= '1';
+ v.sop := '1';
END IF;
-- check end of block
IF mm_address >= last_mm_address THEN
- d.eop <= '1';
+ v.eop := '1';
-- prepare for next block
- d.busy <= '0';
- d.word_index <= 0;
- d.step_index <= 0;
+ v.busy := '0';
+ v.word_index := 0;
+ v.step_index := 0;
END IF;
END IF;
END IF;
+ nxt_r <= v;
END PROCESS;
END rtl;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index d57dddde37..105a6387e9 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -117,8 +117,6 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL jesd204b_sysref_2 : STD_LOGIC;
SIGNAL jesd204b_sysref_frameclk_1 : STD_LOGIC;
SIGNAL jesd204b_sysref_frameclk_2 : STD_LOGIC;
- SIGNAL jesd204b_sysref_linkclk_1 : STD_LOGIC;
- SIGNAL jesd204b_sysref_linkclk_2 : STD_LOGIC;
-- Data path
SIGNAL jesd204b_rx_link_data_arr : STD_LOGIC_VECTOR(c_jesd204b_rx_data_w*g_nof_streams-1 DOWNTO 0);
@@ -176,7 +174,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
rxphy_clk : out std_logic_vector(0 downto 0); -- export
sof : out std_logic_vector(3 downto 0); -- export
somf : out std_logic_vector(c_jesd204b_rx_somf_w-1 downto 0); -- export
@@ -399,7 +397,6 @@ BEGIN
END IF;
END PROCESS;
-
-----------------------------------------------------------------------------
-- Move sysref from rxlink_clk to rxframe_clk
-----------------------------------------------------------------------------
@@ -412,7 +409,7 @@ BEGIN
ELSE
IF rising_edge(rxframe_clk) THEN
jesd204b_sysref_frameclk_1 <= jesd204b_sysref_2; -- sysref from rxlink_clk domain
- jesd204b_sysref_frameclk_2 <= jesd204b_sysref_linkclk_1;
+ jesd204b_sysref_frameclk_2 <= jesd204b_sysref_frameclk_1;
IF jesd204b_sysref_frameclk_1 = '1' and jesd204b_sysref_frameclk_2 = '0' THEN
rx_sysref <= '1';
ELSE
--
GitLab