From 585fe58839489ef2a03f4b3b4049dad24d71437a Mon Sep 17 00:00:00 2001 From: Leon Hiemstra <hiemstra@astron.nl> Date: Wed, 8 Apr 2015 12:12:12 +0000 Subject: [PATCH] using radioHDL pinning file --- .../quartus/unb1_ddr3_transpose_pins.tcl | 2 +- .../unb_ddr3_transpose_pins_constraints.tcl | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl index 23df2d360c..644fc9a105 100644 --- a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl +++ b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl @@ -3,5 +3,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tc source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl -source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl +source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb_ddr3_transpose_pins_constraints.tcl b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb_ddr3_transpose_pins_constraints.tcl index 2aacace6ef..b9ce367313 100644 --- a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb_ddr3_transpose_pins_constraints.tcl +++ b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb_ddr3_transpose_pins_constraints.tcl @@ -238,14 +238,6 @@ set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].clk[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_IO[0].clk[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].clk[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_IO[0].clk[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].clk_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_IO[0].clk_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].clk_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_IO[0].clk_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 @@ -390,6 +382,14 @@ set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_OU[0]. set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_OU[0].dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_OU[0].dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_OU[0].dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU[0].ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU[0].ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU[0].ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU[0].ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU[0].ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU[0].ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU[0].ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU[0].ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0 -- GitLab