diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/sopc_unb_ddr3_transpose.sopc b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/sopc_unb_ddr3_transpose.sopc
index 156b2a0e0c79f8035a45fc07e220a384f95a2c28..1e97c7a04e5632f2e8a82157b7d99a2ac0def9f9 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/sopc_unb_ddr3_transpose.sopc
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/sopc_unb_ddr3_transpose.sopc
@@ -84,19 +84,19 @@
type = "String";
}
}
- element ram_ss_ss_wide.mem
+ element ram_diag_data_buffer_re.mem
{
datum baseAddress
{
- value = "69632";
+ value = "32768";
type = "long";
}
}
- element ram_diag_data_buffer_re.mem
+ element reg_bsn_monitor.mem
{
datum baseAddress
{
- value = "32768";
+ value = "384";
type = "long";
}
}
@@ -108,56 +108,56 @@
type = "long";
}
}
- element ram_diag_bg.mem
+ element pio_pps.mem
{
datum baseAddress
{
- value = "49152";
+ value = "728";
type = "long";
}
}
- element ram_diag_data_buffer_im.mem
+ element ram_ss_ss_wide.mem
{
datum baseAddress
{
- value = "16384";
+ value = "8192";
type = "long";
}
}
- element reg_diag_data_buffer_im.mem
+ element reg_diag_data_buffer_re.mem
{
datum baseAddress
{
- value = "128";
+ value = "256";
type = "long";
}
}
- element pio_pps.mem
+ element rom_system_info.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "728";
+ value = "4096";
type = "long";
}
}
- element reg_wdi.mem
+ element ram_diag_bg.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "12288";
+ value = "49152";
type = "long";
}
}
- element reg_bsn_monitor.mem
+ element reg_diag_data_buffer_im.mem
{
datum baseAddress
{
- value = "384";
+ value = "128";
type = "long";
}
}
@@ -169,15 +169,15 @@
type = "long";
}
}
- element reg_diag_data_buffer_re.mem
+ element ram_diag_data_buffer_im.mem
{
datum baseAddress
{
- value = "256";
+ value = "16384";
type = "long";
}
}
- element rom_system_info.mem
+ element pio_system_info.mem
{
datum _lockedAddress
{
@@ -186,11 +186,11 @@
}
datum baseAddress
{
- value = "4096";
+ value = "0";
type = "long";
}
}
- element pio_system_info.mem
+ element reg_wdi.mem
{
datum _lockedAddress
{
@@ -199,7 +199,7 @@
}
datum baseAddress
{
- value = "0";
+ value = "12288";
type = "long";
}
}
@@ -207,7 +207,7 @@
{
datum baseAddress
{
- value = "65536";
+ value = "69632";
type = "long";
}
}
@@ -223,7 +223,7 @@
{
datum baseAddress
{
- value = "8192";
+ value = "65536";
type = "long";
}
}
@@ -399,19 +399,19 @@
type = "long";
}
}
- element timer_0.s1
+ element pio_wdi.s1
{
datum baseAddress
{
- value = "576";
+ value = "704";
type = "long";
}
}
- element pio_wdi.s1
+ element timer_0.s1
{
datum baseAddress
{
- value = "704";
+ value = "576";
type = "long";
}
}
@@ -438,10 +438,10 @@
<parameter name="globalResetBus" value="true" />
<parameter name="hdlLanguage" value="VHDL" />
<parameter name="maxAdditionalLatency" value="0" />
- <parameter name="projectName">unb_ddr3_transpose.qpf</parameter>
+ <parameter name="projectName">unb1_ddr3_transpose.qpf</parameter>
<parameter name="sopcBorderPoints" value="true" />
- <parameter name="systemHash" value="-54082890877" />
- <parameter name="timeStamp" value="1418900184248" />
+ <parameter name="systemHash" value="-52238569193" />
+ <parameter name="timeStamp" value="1427970877526" />
<parameter name="useTestBenchNamingPattern" value="false" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="25000000" />
@@ -542,7 +542,7 @@
<parameter name="dcache_numTCDM" value="_0" />
<parameter name="dcache_lineSize" value="_32" />
<parameter name="dcache_bursts" value="false" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_im.mem' start='0x80' end='0x100' /><slave name='reg_diag_data_buffer_re.mem' start='0x100' end='0x180' /><slave name='reg_bsn_monitor.mem' start='0x180' end='0x200' /><slave name='avs_eth_0.mms_reg' start='0x200' end='0x240' /><slave name='timer_0.s1' start='0x240' end='0x260' /><slave name='reg_unb_sens.mem' start='0x260' end='0x280' /><slave name='reg_diag_bg.mem' start='0x280' end='0x2A0' /><slave name='altpll_0.pll_slave' start='0x2A0' end='0x2B0' /><slave name='pio_debug_wave.s1' start='0x2B0' end='0x2C0' /><slave name='pio_wdi.s1' start='0x2C0' end='0x2D0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2D0' end='0x2D8' /><slave name='pio_pps.mem' start='0x2D8' end='0x2E0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_diag_data_buffer_im.mem' start='0x4000' end='0x8000' /><slave name='ram_diag_data_buffer_re.mem' start='0x8000' end='0xC000' /><slave name='ram_diag_bg.mem' start='0xC000' end='0x10000' /><slave name='avs_eth_0.mms_ram' start='0x10000' end='0x11000' /><slave name='ram_ss_ss_wide.mem' start='0x11000' end='0x12000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_im.mem' start='0x80' end='0x100' /><slave name='reg_diag_data_buffer_re.mem' start='0x100' end='0x180' /><slave name='reg_bsn_monitor.mem' start='0x180' end='0x200' /><slave name='avs_eth_0.mms_reg' start='0x200' end='0x240' /><slave name='timer_0.s1' start='0x240' end='0x260' /><slave name='reg_unb_sens.mem' start='0x260' end='0x280' /><slave name='reg_diag_bg.mem' start='0x280' end='0x2A0' /><slave name='altpll_0.pll_slave' start='0x2A0' end='0x2B0' /><slave name='pio_debug_wave.s1' start='0x2B0' end='0x2C0' /><slave name='pio_wdi.s1' start='0x2C0' end='0x2D0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2D0' end='0x2D8' /><slave name='pio_pps.mem' start='0x2D8' end='0x2E0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='ram_ss_ss_wide.mem' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_diag_data_buffer_im.mem' start='0x4000' end='0x8000' /><slave name='ram_diag_data_buffer_re.mem' start='0x8000' end='0xC000' /><slave name='ram_diag_bg.mem' start='0xC000' end='0x10000' /><slave name='avs_eth_0.mms_tse' start='0x10000' end='0x11000' /><slave name='avs_eth_0.mms_ram' start='0x11000' end='0x12000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="dataAddrWidth" value="18" />
<parameter name="customInstSlavesSystemInfo" value="<info/>" />
<parameter name="cpuReset" value="false" />
@@ -805,9 +805,6 @@ q]]></parameter>
<parameter name="timeoutPulseOutput" value="false" />
<parameter name="timerPreset">SIMPLE_PERIODIC_INTERRUPT</parameter>
</module>
- <module kind="avs_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
- <parameter name="AUTO_MM_CLOCK_RATE" value="50000000" />
- </module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
@@ -889,6 +886,9 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module>
+ <module kind="avs2_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
+ <parameter name="AUTO_MM_CLOCK_RATE" value="50000000" />
+ </module>
<connection
kind="avalon"
version="11.1"
@@ -990,38 +990,6 @@ q]]></parameter>
<connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
<parameter name="irqNumber" value="1" />
</connection>
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="avs_eth_0.mms_tse">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x2000" />
- </connection>
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="avs_eth_0.mms_reg">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0200" />
- </connection>
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="avs_eth_0.mms_ram">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00010000" />
- </connection>
- <connection
- kind="interrupt"
- version="11.1"
- start="cpu_0.d_irq"
- end="avs_eth_0.interrupt">
- <parameter name="irqNumber" value="2" />
- </connection>
<connection
kind="clock"
version="11.1"
@@ -1168,7 +1136,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="ram_ss_ss_wide.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00011000" />
+ <parameter name="baseAddress" value="0x2000" />
</connection>
<connection
kind="clock"
@@ -1183,4 +1151,36 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0180" />
</connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_tse">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00010000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_reg">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0200" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_ram">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00011000" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="avs_eth_0.interrupt">
+ <parameter name="irqNumber" value="2" />
+ </connection>
</system>
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
index 7d5e3528654c227bbd5f53bc3a5203e0e8c37a9e..42cfb412966022e9784fae95ab7c195fde0ed720 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
@@ -207,6 +207,8 @@ ARCHITECTURE str OF unb1_ddr3_transpose IS
SIGNAL out_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL out_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL ddr_ref_rst : STD_LOGIC;
+
BEGIN
-----------------------------------------------------------------------------
@@ -222,6 +224,7 @@ BEGIN
g_fw_version => c_fw_version,
g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
g_use_phy => c_use_phy,
+ g_dp_clk_use_pll => FALSE,
g_aux => c_unb1_board_aux
)
PORT MAP (
@@ -235,8 +238,8 @@ BEGIN
mm_locked => mm_locked,
mm_rst => mm_rst,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => OPEN,--dp_rst,
+ dp_clk => OPEN,--dp_clk,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
@@ -423,6 +426,19 @@ BEGIN
bsn_sosi_arr(0) <= bg_sosi_arr(0);
bsn_sosi_arr(1) <= out_sosi_arr(0);
+
+ u_areset_ddr_ref_rst : ENTITY common_lib.common_areset
+ GENERIC MAP(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ PORT MAP(
+ clk => CLK,
+ in_rst => mm_rst,
+ out_rst => ddr_ref_rst
+ );
+
+
u_ddr3_T: ENTITY ddr3_lib.ddr3_transpose
GENERIC MAP(
g_sim => g_sim,
@@ -441,8 +457,14 @@ BEGIN
mm_rst => mm_rst,
mm_clk => mm_clk,
+ dp_ref_clk => CLK,
+ dp_ref_rst => ddr_ref_rst,
+
dp_rst => dp_rst,
dp_clk => dp_clk,
+
+ dp_out_clk => dp_clk,
+ dp_out_rst => dp_rst,
snk_out_arr => bg_siso_arr,
snk_in_arr => bg_sosi_arr,