diff --git a/boards/uniboard1/designs/unb1_test/hdllib.cfg b/boards/uniboard1/designs/unb1_test/hdllib.cfg
index 61cf80f99b80fcd44ea5537a092ea139efae33f8..ac5e99e2e7a5f2ee50da96ed0c16bb94831a1fe4 100644
--- a/boards/uniboard1/designs/unb1_test/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/hdllib.cfg
@@ -7,7 +7,9 @@ hdl_lib_technology = ip_stratixiv
synth_files =
src/vhdl/qsys_unb1_test_pkg.vhd
+ src/vhdl/unb1_test_pkg.vhd
src/vhdl/mmm_unb1_test.vhd
+ src/vhdl/bgdb_stream_test.vhd
src/vhdl/unb1_test.vhd
test_bench_files =
diff --git a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
index 7fed96c210203d094a569bf33673020a1b5998e6..c4d316d4769302aa1cd6ae9055d1702fd9064470 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
+++ b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
@@ -65,218 +65,266 @@
type = "String";
}
}
- element reg_dpmm_ctrl.mem
+ element reg_bsn_monitor_10GbE.mem
{
datum baseAddress
{
- value = "12432";
+ value = "12800";
type = "long";
}
}
- element reg_dpmm_data.mem
+ element reg_dp_offload_tx_10GbE.mem
{
datum baseAddress
{
- value = "12440";
+ value = "12480";
type = "long";
}
}
- element reg_mmdp_data.mem
+ element reg_io_ddr.mem
{
datum baseAddress
{
- value = "12456";
+ value = "12672";
type = "long";
}
}
- element reg_dp_offload_rx_hdr_dat.mem
+ element reg_mmdp_ctrl.mem
{
datum baseAddress
{
- value = "1024";
+ value = "12704";
type = "long";
}
}
- element reg_remu.mem
+ element ram_diag_data_buffer_1GbE.mem
{
datum baseAddress
{
- value = "12320";
+ value = "65536";
type = "long";
}
}
- element reg_unb_sens.mem
+ element reg_epcs.mem
{
datum baseAddress
{
- value = "480";
+ value = "12608";
type = "long";
}
}
- element reg_diag_bg.mem
+ element reg_diag_bg_1GbE.mem
{
datum baseAddress
{
- value = "12384";
+ value = "12640";
type = "long";
}
}
- element reg_tr_xaui.mem
+ element reg_diag_data_buffer_1GbE.mem
{
datum baseAddress
{
- value = "16384";
+ value = "128";
type = "long";
}
}
- element pio_pps.mem
+ element pio_system_info.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "12464";
+ value = "0";
type = "long";
}
}
- element reg_dp_offload_tx.mem
+ element ram_ss_ss_wide.mem
{
datum baseAddress
{
- value = "320";
+ value = "393216";
type = "long";
}
}
- element reg_diag_data_buffer.mem
+ element reg_unb_sens.mem
{
datum baseAddress
{
- value = "128";
+ value = "12544";
type = "long";
}
}
- element reg_dp_offload_tx_1gbe_hdr_dat.mem
+ element reg_tr_10GbE.mem
{
datum baseAddress
{
- value = "28672";
+ value = "262144";
type = "long";
}
}
- element reg_tr_10GbE.mem
+ element reg_bsn_monitor_1GbE.mem
{
datum baseAddress
{
- value = "262144";
+ value = "512";
type = "long";
}
}
- element ram_diag_bg.mem
+ element reg_dpmm_ctrl.mem
{
datum baseAddress
{
- value = "32768";
+ value = "12688";
type = "long";
}
}
- element ram_ss_ss_wide.mem
+ element reg_tr_xaui.mem
{
datum baseAddress
{
- value = "393216";
+ value = "16384";
type = "long";
}
}
- element pio_system_info.mem
+ element reg_dp_offload_tx_1GbE.mem
{
- datum _lockedAddress
+ datum baseAddress
{
- value = "1";
- type = "boolean";
+ value = "12416";
+ type = "long";
}
+ }
+ element reg_diag_bg_10GbE.mem
+ {
datum baseAddress
{
- value = "0";
+ value = "256";
type = "long";
}
}
- element rom_system_info.mem
+ element reg_dp_offload_rx_1GbE_hdr_dat.mem
{
- datum _lockedAddress
+ datum baseAddress
{
- value = "1";
- type = "boolean";
+ value = "1024";
+ type = "long";
}
+ }
+ element reg_dp_offload_tx_1GbE_hdr_dat.mem
+ {
datum baseAddress
{
- value = "4096";
+ value = "13312";
type = "long";
}
}
- element reg_io_ddr.mem
+ element reg_mmdp_data.mem
{
datum baseAddress
{
- value = "12416";
+ value = "12712";
type = "long";
}
}
- element reg_dp_offload_tx_hdr_dat.mem
+ element ram_diag_data_buffer_10GbE.mem
{
datum baseAddress
{
- value = "13312";
+ value = "458752";
type = "long";
}
}
- element reg_epcs.mem
+ element pio_pps.mem
{
datum baseAddress
{
- value = "12352";
+ value = "12720";
type = "long";
}
}
- element reg_wdi.mem
+ element reg_dpmm_data.mem
{
- datum _lockedAddress
+ datum baseAddress
{
- value = "1";
- type = "boolean";
+ value = "12696";
+ type = "long";
}
+ }
+ element reg_remu.mem
+ {
datum baseAddress
{
- value = "12288";
+ value = "12576";
type = "long";
}
}
- element reg_bsn_monitor.mem
+ element reg_diag_data_buffer_10GbE.mem
{
datum baseAddress
{
- value = "512";
+ value = "384";
type = "long";
}
}
- element reg_mmdp_ctrl.mem
+ element reg_dp_offload_rx_10GbE_hdr_dat.mem
{
datum baseAddress
{
- value = "12448";
+ value = "29696";
type = "long";
}
}
- element ram_diag_data_buffer.mem
+ element reg_dp_offload_tx_10GbE_hdr_dat.mem
{
datum baseAddress
{
- value = "65536";
+ value = "28672";
type = "long";
}
}
- element reg_dp_offload_tx_1gbe.mem
+ element ram_diag_bg_1GbE.mem
{
datum baseAddress
{
- value = "384";
+ value = "32768";
+ type = "long";
+ }
+ }
+ element reg_wdi.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "12288";
+ type = "long";
+ }
+ }
+ element ram_diag_bg_10GbE.mem
+ {
+ datum baseAddress
+ {
+ value = "524288";
+ type = "long";
+ }
+ }
+ element rom_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "4096";
type = "long";
}
}
@@ -292,7 +340,7 @@
{
datum baseAddress
{
- value = "256";
+ value = "12352";
type = "long";
}
}
@@ -346,19 +394,35 @@
type = "String";
}
}
- element ram_diag_bg
+ element ram_diag_bg_10GbE
{
datum _sortIndex
{
- value = "27";
+ value = "31";
type = "int";
}
}
- element ram_diag_data_buffer
+ element ram_diag_bg_1GbE
{
datum _sortIndex
{
- value = "25";
+ value = "30";
+ type = "int";
+ }
+ }
+ element ram_diag_data_buffer_10GbE
+ {
+ datum _sortIndex
+ {
+ value = "35";
+ type = "int";
+ }
+ }
+ element ram_diag_data_buffer_1GbE
+ {
+ datum _sortIndex
+ {
+ value = "34";
type = "int";
}
}
@@ -366,11 +430,19 @@
{
datum _sortIndex
{
- value = "28";
+ value = "36";
type = "int";
}
}
- element reg_bsn_monitor
+ element reg_bsn_monitor_10GbE
+ {
+ datum _sortIndex
+ {
+ value = "21";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_1GbE
{
datum _sortIndex
{
@@ -378,55 +450,71 @@
type = "int";
}
}
- element reg_diag_bg
+ element reg_diag_bg_10GbE
{
datum _sortIndex
{
- value = "26";
+ value = "29";
type = "int";
}
}
- element reg_diag_data_buffer
+ element reg_diag_bg_1GbE
{
datum _sortIndex
{
- value = "24";
+ value = "28";
type = "int";
}
}
- element reg_dp_offload_rx_hdr_dat
+ element reg_diag_data_buffer_10GbE
{
datum _sortIndex
{
- value = "23";
+ value = "33";
type = "int";
}
}
- element reg_dp_offload_tx
+ element reg_diag_data_buffer_1GbE
{
datum _sortIndex
{
- value = "21";
+ value = "32";
type = "int";
}
}
- element reg_dp_offload_tx_1gbe
+ element reg_dp_offload_rx_10GbE_hdr_dat
{
datum _sortIndex
{
- value = "30";
+ value = "27";
type = "int";
}
}
- element reg_dp_offload_tx_1gbe_hdr_dat
+ element reg_dp_offload_rx_1GbE_hdr_dat
{
datum _sortIndex
{
- value = "31";
+ value = "26";
+ type = "int";
+ }
+ }
+ element reg_dp_offload_tx_10GbE
+ {
+ datum _sortIndex
+ {
+ value = "23";
type = "int";
}
}
- element reg_dp_offload_tx_hdr_dat
+ element reg_dp_offload_tx_10GbE_hdr_dat
+ {
+ datum _sortIndex
+ {
+ value = "25";
+ type = "int";
+ }
+ }
+ element reg_dp_offload_tx_1GbE
{
datum _sortIndex
{
@@ -434,6 +522,14 @@
type = "int";
}
}
+ element reg_dp_offload_tx_1GbE_hdr_dat
+ {
+ datum _sortIndex
+ {
+ value = "24";
+ type = "int";
+ }
+ }
element reg_dpmm_ctrl
{
datum _sortIndex
@@ -462,7 +558,7 @@
{
datum _sortIndex
{
- value = "29";
+ value = "37";
type = "int";
}
}
@@ -530,14 +626,6 @@
type = "int";
}
}
- element pio_wdi.s1
- {
- datum baseAddress
- {
- value = "12304";
- type = "long";
- }
- }
element onchip_memory2_0.s1
{
datum _lockedAddress
@@ -555,7 +643,15 @@
{
datum baseAddress
{
- value = "448";
+ value = "12320";
+ type = "long";
+ }
+ }
+ element pio_wdi.s1
+ {
+ datum baseAddress
+ {
+ value = "12304";
type = "long";
}
}
@@ -582,7 +678,7 @@
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
- <parameter name="timeStamp" value="1429017518755" />
+ <parameter name="timeStamp" value="1429698630991" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
@@ -1541,423 +1637,633 @@
<port name="coe_read_export_from_the_reg_remu" internal="coe_read_export" />
</interface>
<interface
- name="reg_bsn_monitor_readdata"
- internal="reg_bsn_monitor.readdata"
+ name="reg_bsn_monitor_1gbe_readdata"
+ internal="reg_bsn_monitor_1GbE.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_read"
- internal="reg_bsn_monitor.read"
+ name="reg_bsn_monitor_1gbe_read"
+ internal="reg_bsn_monitor_1GbE.read"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_writedata"
- internal="reg_bsn_monitor.writedata"
+ name="reg_bsn_monitor_1gbe_writedata"
+ internal="reg_bsn_monitor_1GbE.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_write"
- internal="reg_bsn_monitor.write"
+ name="reg_bsn_monitor_1gbe_write"
+ internal="reg_bsn_monitor_1GbE.write"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_address"
- internal="reg_bsn_monitor.address"
+ name="reg_bsn_monitor_1gbe_address"
+ internal="reg_bsn_monitor_1GbE.address"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_clk"
- internal="reg_bsn_monitor.clk"
+ name="reg_bsn_monitor_1gbe_clk"
+ internal="reg_bsn_monitor_1GbE.clk"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_reset"
- internal="reg_bsn_monitor.reset"
+ name="reg_bsn_monitor_1gbe_reset"
+ internal="reg_bsn_monitor_1GbE.reset"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_readdata"
- internal="reg_dp_offload_tx.readdata"
+ name="ram_ss_ss_wide_readdata"
+ internal="ram_ss_ss_wide.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_read"
- internal="reg_dp_offload_tx.read"
+ name="ram_ss_ss_wide_read"
+ internal="ram_ss_ss_wide.read"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_writedata"
- internal="reg_dp_offload_tx.writedata"
+ name="ram_ss_ss_wide_writedata"
+ internal="ram_ss_ss_wide.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_write"
- internal="reg_dp_offload_tx.write"
+ name="ram_ss_ss_wide_write"
+ internal="ram_ss_ss_wide.write"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_address"
- internal="reg_dp_offload_tx.address"
+ name="ram_ss_ss_wide_address"
+ internal="ram_ss_ss_wide.address"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_clk"
- internal="reg_dp_offload_tx.clk"
+ name="ram_ss_ss_wide_clk"
+ internal="ram_ss_ss_wide.clk"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_reset"
- internal="reg_dp_offload_tx.reset"
+ name="ram_ss_ss_wide_reset"
+ internal="ram_ss_ss_wide.reset"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_hdr_dat_readdata"
- internal="reg_dp_offload_tx_hdr_dat.readdata"
+ name="reg_io_ddr_readdata"
+ internal="reg_io_ddr.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_hdr_dat_read"
- internal="reg_dp_offload_tx_hdr_dat.read"
+ name="reg_io_ddr_read"
+ internal="reg_io_ddr.read"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_hdr_dat_writedata"
- internal="reg_dp_offload_tx_hdr_dat.writedata"
+ name="reg_io_ddr_writedata"
+ internal="reg_io_ddr.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_hdr_dat_write"
- internal="reg_dp_offload_tx_hdr_dat.write"
+ name="reg_io_ddr_write"
+ internal="reg_io_ddr.write"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_hdr_dat_address"
- internal="reg_dp_offload_tx_hdr_dat.address"
+ name="reg_io_ddr_address"
+ internal="reg_io_ddr.address"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_hdr_dat_clk"
- internal="reg_dp_offload_tx_hdr_dat.clk"
+ name="reg_io_ddr_clk"
+ internal="reg_io_ddr.clk"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_hdr_dat_reset"
- internal="reg_dp_offload_tx_hdr_dat.reset"
+ name="reg_io_ddr_reset"
+ internal="reg_io_ddr.reset"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_rx_hdr_dat_readdata"
- internal="reg_dp_offload_rx_hdr_dat.readdata"
+ name="reg_diag_data_buffer_10gbe_readdata"
+ internal="reg_diag_data_buffer_10GbE.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_rx_hdr_dat_read"
- internal="reg_dp_offload_rx_hdr_dat.read"
+ name="reg_diag_data_buffer_10gbe_read"
+ internal="reg_diag_data_buffer_10GbE.read"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_rx_hdr_dat_writedata"
- internal="reg_dp_offload_rx_hdr_dat.writedata"
+ name="reg_diag_data_buffer_10gbe_writedata"
+ internal="reg_diag_data_buffer_10GbE.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_rx_hdr_dat_write"
- internal="reg_dp_offload_rx_hdr_dat.write"
+ name="reg_diag_data_buffer_10gbe_write"
+ internal="reg_diag_data_buffer_10GbE.write"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_rx_hdr_dat_address"
- internal="reg_dp_offload_rx_hdr_dat.address"
+ name="reg_diag_data_buffer_10gbe_address"
+ internal="reg_diag_data_buffer_10GbE.address"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_rx_hdr_dat_clk"
- internal="reg_dp_offload_rx_hdr_dat.clk"
+ name="reg_diag_data_buffer_10gbe_clk"
+ internal="reg_diag_data_buffer_10GbE.clk"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_rx_hdr_dat_reset"
- internal="reg_dp_offload_rx_hdr_dat.reset"
+ name="reg_diag_data_buffer_10gbe_reset"
+ internal="reg_diag_data_buffer_10GbE.reset"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buffer_readdata"
- internal="reg_diag_data_buffer.readdata"
+ name="ram_diag_bg_10gbe_readdata"
+ internal="ram_diag_bg_10GbE.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buffer_read"
- internal="reg_diag_data_buffer.read"
+ name="ram_diag_bg_10gbe_read"
+ internal="ram_diag_bg_10GbE.read"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buffer_writedata"
- internal="reg_diag_data_buffer.writedata"
+ name="ram_diag_bg_10gbe_writedata"
+ internal="ram_diag_bg_10GbE.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buffer_write"
- internal="reg_diag_data_buffer.write"
+ name="ram_diag_bg_10gbe_write"
+ internal="ram_diag_bg_10GbE.write"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buffer_address"
- internal="reg_diag_data_buffer.address"
+ name="ram_diag_bg_10gbe_address"
+ internal="ram_diag_bg_10GbE.address"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buffer_clk"
- internal="reg_diag_data_buffer.clk"
+ name="ram_diag_bg_10gbe_clk"
+ internal="ram_diag_bg_10GbE.clk"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buffer_reset"
- internal="reg_diag_data_buffer.reset"
+ name="ram_diag_bg_10gbe_reset"
+ internal="ram_diag_bg_10GbE.reset"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buffer_readdata"
- internal="ram_diag_data_buffer.readdata"
+ name="reg_diag_bg_10gbe_readdata"
+ internal="reg_diag_bg_10GbE.readdata"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buffer_read"
- internal="ram_diag_data_buffer.read"
+ name="reg_diag_bg_10gbe_read"
+ internal="reg_diag_bg_10GbE.read"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buffer_writedata"
- internal="ram_diag_data_buffer.writedata"
+ name="reg_diag_bg_10gbe_writedata"
+ internal="reg_diag_bg_10GbE.writedata"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buffer_write"
- internal="ram_diag_data_buffer.write"
+ name="reg_diag_bg_10gbe_write"
+ internal="reg_diag_bg_10GbE.write"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buffer_address"
- internal="ram_diag_data_buffer.address"
+ name="reg_diag_bg_10gbe_address"
+ internal="reg_diag_bg_10GbE.address"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buffer_clk"
- internal="ram_diag_data_buffer.clk"
+ name="reg_diag_bg_10gbe_clk"
+ internal="reg_diag_bg_10GbE.clk"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buffer_reset"
- internal="ram_diag_data_buffer.reset"
+ name="reg_diag_bg_10gbe_reset"
+ internal="reg_diag_bg_10GbE.reset"
type="conduit"
dir="end" />
<interface
- name="reg_diag_bg_readdata"
- internal="reg_diag_bg.readdata"
+ name="reg_dp_offload_rx_10gbe_hdr_dat_readdata"
+ internal="reg_dp_offload_rx_10GbE_hdr_dat.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_diag_bg_read"
- internal="reg_diag_bg.read"
+ name="reg_dp_offload_rx_10gbe_hdr_dat_read"
+ internal="reg_dp_offload_rx_10GbE_hdr_dat.read"
type="conduit"
dir="end" />
<interface
- name="reg_diag_bg_writedata"
- internal="reg_diag_bg.writedata"
+ name="reg_dp_offload_rx_10gbe_hdr_dat_writedata"
+ internal="reg_dp_offload_rx_10GbE_hdr_dat.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_diag_bg_write"
- internal="reg_diag_bg.write"
+ name="reg_dp_offload_rx_10gbe_hdr_dat_write"
+ internal="reg_dp_offload_rx_10GbE_hdr_dat.write"
type="conduit"
dir="end" />
<interface
- name="reg_diag_bg_address"
- internal="reg_diag_bg.address"
+ name="reg_dp_offload_rx_10gbe_hdr_dat_address"
+ internal="reg_dp_offload_rx_10GbE_hdr_dat.address"
type="conduit"
dir="end" />
<interface
- name="reg_diag_bg_clk"
- internal="reg_diag_bg.clk"
+ name="reg_dp_offload_rx_10gbe_hdr_dat_clk"
+ internal="reg_dp_offload_rx_10GbE_hdr_dat.clk"
type="conduit"
dir="end" />
<interface
- name="reg_diag_bg_reset"
- internal="reg_diag_bg.reset"
+ name="reg_dp_offload_rx_10gbe_hdr_dat_reset"
+ internal="reg_dp_offload_rx_10GbE_hdr_dat.reset"
type="conduit"
dir="end" />
<interface
- name="ram_diag_bg_readdata"
- internal="ram_diag_bg.readdata"
+ name="reg_dp_offload_tx_10gbe_hdr_dat_readdata"
+ internal="reg_dp_offload_tx_10GbE_hdr_dat.readdata"
type="conduit"
dir="end" />
<interface
- name="ram_diag_bg_read"
- internal="ram_diag_bg.read"
+ name="reg_dp_offload_tx_10gbe_hdr_dat_read"
+ internal="reg_dp_offload_tx_10GbE_hdr_dat.read"
type="conduit"
dir="end" />
<interface
- name="ram_diag_bg_writedata"
- internal="ram_diag_bg.writedata"
+ name="reg_dp_offload_tx_10gbe_hdr_dat_writedata"
+ internal="reg_dp_offload_tx_10GbE_hdr_dat.writedata"
type="conduit"
dir="end" />
<interface
- name="ram_diag_bg_write"
- internal="ram_diag_bg.write"
+ name="reg_dp_offload_tx_10gbe_hdr_dat_write"
+ internal="reg_dp_offload_tx_10GbE_hdr_dat.write"
type="conduit"
dir="end" />
<interface
- name="ram_diag_bg_address"
- internal="ram_diag_bg.address"
+ name="reg_dp_offload_tx_10gbe_hdr_dat_address"
+ internal="reg_dp_offload_tx_10GbE_hdr_dat.address"
type="conduit"
dir="end" />
<interface
- name="ram_diag_bg_clk"
- internal="ram_diag_bg.clk"
+ name="reg_dp_offload_tx_10gbe_hdr_dat_clk"
+ internal="reg_dp_offload_tx_10GbE_hdr_dat.clk"
type="conduit"
dir="end" />
<interface
- name="ram_diag_bg_reset"
- internal="ram_diag_bg.reset"
+ name="reg_dp_offload_tx_10gbe_hdr_dat_reset"
+ internal="reg_dp_offload_tx_10GbE_hdr_dat.reset"
type="conduit"
dir="end" />
<interface
- name="ram_ss_ss_wide_readdata"
- internal="ram_ss_ss_wide.readdata"
+ name="reg_dp_offload_tx_10gbe_readdata"
+ internal="reg_dp_offload_tx_10GbE.readdata"
type="conduit"
dir="end" />
<interface
- name="ram_ss_ss_wide_read"
- internal="ram_ss_ss_wide.read"
+ name="reg_dp_offload_tx_10gbe_read"
+ internal="reg_dp_offload_tx_10GbE.read"
type="conduit"
dir="end" />
<interface
- name="ram_ss_ss_wide_writedata"
- internal="ram_ss_ss_wide.writedata"
+ name="reg_dp_offload_tx_10gbe_writedata"
+ internal="reg_dp_offload_tx_10GbE.writedata"
type="conduit"
dir="end" />
<interface
- name="ram_ss_ss_wide_write"
- internal="ram_ss_ss_wide.write"
+ name="reg_dp_offload_tx_10gbe_write"
+ internal="reg_dp_offload_tx_10GbE.write"
type="conduit"
dir="end" />
<interface
- name="ram_ss_ss_wide_address"
- internal="ram_ss_ss_wide.address"
+ name="reg_dp_offload_tx_10gbe_address"
+ internal="reg_dp_offload_tx_10GbE.address"
type="conduit"
dir="end" />
<interface
- name="ram_ss_ss_wide_clk"
- internal="ram_ss_ss_wide.clk"
+ name="reg_dp_offload_tx_10gbe_clk"
+ internal="reg_dp_offload_tx_10GbE.clk"
type="conduit"
dir="end" />
<interface
- name="ram_ss_ss_wide_reset"
- internal="ram_ss_ss_wide.reset"
+ name="reg_dp_offload_tx_10gbe_reset"
+ internal="reg_dp_offload_tx_10GbE.reset"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_readdata"
- internal="reg_io_ddr.readdata"
+ name="reg_bsn_monitor_10gbe_readdata"
+ internal="reg_bsn_monitor_10GbE.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_read"
- internal="reg_io_ddr.read"
+ name="reg_bsn_monitor_10gbe_read"
+ internal="reg_bsn_monitor_10GbE.read"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_writedata"
- internal="reg_io_ddr.writedata"
+ name="reg_bsn_monitor_10gbe_writedata"
+ internal="reg_bsn_monitor_10GbE.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_write"
- internal="reg_io_ddr.write"
+ name="reg_bsn_monitor_10gbe_write"
+ internal="reg_bsn_monitor_10GbE.write"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_address"
- internal="reg_io_ddr.address"
+ name="reg_bsn_monitor_10gbe_address"
+ internal="reg_bsn_monitor_10GbE.address"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_clk"
- internal="reg_io_ddr.clk"
+ name="reg_bsn_monitor_10gbe_clk"
+ internal="reg_bsn_monitor_10GbE.clk"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_reset"
- internal="reg_io_ddr.reset"
+ name="reg_bsn_monitor_10gbe_reset"
+ internal="reg_bsn_monitor_10GbE.reset"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_1gbe_readdata"
- internal="reg_dp_offload_tx_1gbe.readdata"
+ name="reg_dp_offload_tx_1gbe_reset"
+ internal="reg_dp_offload_tx_1GbE.reset"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_1gbe_read"
- internal="reg_dp_offload_tx_1gbe.read"
+ name="reg_dp_offload_tx_1gbe_clk"
+ internal="reg_dp_offload_tx_1GbE.clk"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_1gbe_writedata"
- internal="reg_dp_offload_tx_1gbe.writedata"
+ name="reg_dp_offload_tx_1gbe_address"
+ internal="reg_dp_offload_tx_1GbE.address"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_write"
- internal="reg_dp_offload_tx_1gbe.write"
+ internal="reg_dp_offload_tx_1GbE.write"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_1gbe_address"
- internal="reg_dp_offload_tx_1gbe.address"
+ name="reg_dp_offload_tx_1gbe_writedata"
+ internal="reg_dp_offload_tx_1GbE.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_1gbe_clk"
- internal="reg_dp_offload_tx_1gbe.clk"
+ name="reg_dp_offload_tx_1gbe_read"
+ internal="reg_dp_offload_tx_1GbE.read"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_1gbe_reset"
- internal="reg_dp_offload_tx_1gbe.reset"
+ name="reg_dp_offload_tx_1gbe_readdata"
+ internal="reg_dp_offload_tx_1GbE.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_1gbe_hdr_dat_readdata"
- internal="reg_dp_offload_tx_1gbe_hdr_dat.readdata"
+ name="reg_dp_offload_tx_1gbe_hdr_dat_reset"
+ internal="reg_dp_offload_tx_1GbE_hdr_dat.reset"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_1gbe_hdr_dat_read"
- internal="reg_dp_offload_tx_1gbe_hdr_dat.read"
+ name="reg_dp_offload_tx_1gbe_hdr_dat_clk"
+ internal="reg_dp_offload_tx_1GbE_hdr_dat.clk"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_1gbe_hdr_dat_writedata"
- internal="reg_dp_offload_tx_1gbe_hdr_dat.writedata"
+ name="reg_dp_offload_tx_1gbe_hdr_dat_address"
+ internal="reg_dp_offload_tx_1GbE_hdr_dat.address"
type="conduit"
dir="end" />
<interface
name="reg_dp_offload_tx_1gbe_hdr_dat_write"
- internal="reg_dp_offload_tx_1gbe_hdr_dat.write"
+ internal="reg_dp_offload_tx_1GbE_hdr_dat.write"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_1gbe_hdr_dat_address"
- internal="reg_dp_offload_tx_1gbe_hdr_dat.address"
+ name="reg_dp_offload_tx_1gbe_hdr_dat_writedata"
+ internal="reg_dp_offload_tx_1GbE_hdr_dat.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_1gbe_hdr_dat_clk"
- internal="reg_dp_offload_tx_1gbe_hdr_dat.clk"
+ name="reg_dp_offload_tx_1gbe_hdr_dat_read"
+ internal="reg_dp_offload_tx_1GbE_hdr_dat.read"
type="conduit"
dir="end" />
<interface
- name="reg_dp_offload_tx_1gbe_hdr_dat_reset"
- internal="reg_dp_offload_tx_1gbe_hdr_dat.reset"
+ name="reg_dp_offload_tx_1gbe_hdr_dat_readdata"
+ internal="reg_dp_offload_tx_1GbE_hdr_dat.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_1gbe_hdr_dat_reset"
+ internal="reg_dp_offload_rx_1GbE_hdr_dat.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_1gbe_hdr_dat_clk"
+ internal="reg_dp_offload_rx_1GbE_hdr_dat.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_1gbe_hdr_dat_address"
+ internal="reg_dp_offload_rx_1GbE_hdr_dat.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_1gbe_hdr_dat_write"
+ internal="reg_dp_offload_rx_1GbE_hdr_dat.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_1gbe_hdr_dat_writedata"
+ internal="reg_dp_offload_rx_1GbE_hdr_dat.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_1gbe_hdr_dat_read"
+ internal="reg_dp_offload_rx_1GbE_hdr_dat.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_1gbe_hdr_dat_readdata"
+ internal="reg_dp_offload_rx_1GbE_hdr_dat.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_1gbe_reset"
+ internal="reg_diag_bg_1GbE.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_1gbe_clk"
+ internal="reg_diag_bg_1GbE.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_1gbe_address"
+ internal="reg_diag_bg_1GbE.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_1gbe_write"
+ internal="reg_diag_bg_1GbE.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_1gbe_writedata"
+ internal="reg_diag_bg_1GbE.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_1gbe_read"
+ internal="reg_diag_bg_1GbE.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_1gbe_readdata"
+ internal="reg_diag_bg_1GbE.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_1gbe_reset"
+ internal="ram_diag_bg_1GbE.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_1gbe_clk"
+ internal="ram_diag_bg_1GbE.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_1gbe_address"
+ internal="ram_diag_bg_1GbE.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_1gbe_write"
+ internal="ram_diag_bg_1GbE.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_1gbe_writedata"
+ internal="ram_diag_bg_1GbE.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_1gbe_read"
+ internal="ram_diag_bg_1GbE.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_1gbe_readdata"
+ internal="ram_diag_bg_1GbE.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_1gbe_reset"
+ internal="reg_diag_data_buffer_1GbE.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_1gbe_clk"
+ internal="reg_diag_data_buffer_1GbE.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_1gbe_address"
+ internal="reg_diag_data_buffer_1GbE.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_1gbe_write"
+ internal="reg_diag_data_buffer_1GbE.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_1gbe_writedata"
+ internal="reg_diag_data_buffer_1GbE.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_1gbe_read"
+ internal="reg_diag_data_buffer_1GbE.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_1gbe_readdata"
+ internal="reg_diag_data_buffer_1GbE.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_1gbe_reset"
+ internal="ram_diag_data_buffer_1GbE.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_1gbe_clk"
+ internal="ram_diag_data_buffer_1GbE.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_1gbe_address"
+ internal="ram_diag_data_buffer_1GbE.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_1gbe_write"
+ internal="ram_diag_data_buffer_1GbE.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_1gbe_writedata"
+ internal="ram_diag_data_buffer_1GbE.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_1gbe_read"
+ internal="ram_diag_data_buffer_1GbE.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_1gbe_readdata"
+ internal="ram_diag_data_buffer_1GbE.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_10gbe_reset"
+ internal="ram_diag_data_buffer_10GbE.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_10gbe_clk"
+ internal="ram_diag_data_buffer_10GbE.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_10gbe_address"
+ internal="ram_diag_data_buffer_10GbE.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_10gbe_write"
+ internal="ram_diag_data_buffer_10GbE.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_10gbe_writedata"
+ internal="ram_diag_data_buffer_10GbE.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_10gbe_read"
+ internal="ram_diag_data_buffer_10GbE.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_10gbe_readdata"
+ internal="ram_diag_data_buffer_10GbE.readdata"
type="conduit"
dir="end" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
@@ -2190,7 +2496,7 @@ q]]></parameter>
<parameter name="dcache_numTCDM" value="0" />
<parameter name="dcache_lineSize" value="32" />
<parameter name="instAddrWidth" value="18" />
- <parameter name="dataAddrWidth" value="19" />
+ <parameter name="dataAddrWidth" value="20" />
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
@@ -2200,7 +2506,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='avs_eth_0.mms_reg' start='0x100' end='0x140' /><slave name='reg_dp_offload_tx.mem' start='0x140' end='0x180' /><slave name='reg_dp_offload_tx_1gbe.mem' start='0x180' end='0x1C0' /><slave name='timer_0.s1' start='0x1C0' end='0x1E0' /><slave name='reg_unb_sens.mem' start='0x1E0' end='0x200' /><slave name='reg_bsn_monitor.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='reg_remu.mem' start='0x3020' end='0x3040' /><slave name='reg_epcs.mem' start='0x3040' end='0x3060' /><slave name='reg_diag_bg.mem' start='0x3060' end='0x3080' /><slave name='reg_io_ddr.mem' start='0x3080' end='0x3090' /><slave name='reg_dpmm_ctrl.mem' start='0x3090' end='0x3098' /><slave name='reg_dpmm_data.mem' start='0x3098' end='0x30A0' /><slave name='reg_mmdp_ctrl.mem' start='0x30A0' end='0x30A8' /><slave name='reg_mmdp_data.mem' start='0x30A8' end='0x30B0' /><slave name='pio_pps.mem' start='0x30B0' end='0x30B8' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='reg_dp_offload_tx_1gbe_hdr_dat.mem' start='0x7000' end='0x7400' /><slave name='ram_diag_bg.mem' start='0x8000' end='0x10000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_1GbE.mem' start='0x80' end='0x100' /><slave name='reg_diag_bg_10GbE.mem' start='0x100' end='0x180' /><slave name='reg_diag_data_buffer_10GbE.mem' start='0x180' end='0x200' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_1GbE_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_dp_offload_tx_1GbE.mem' start='0x3080' end='0x30C0' /><slave name='reg_dp_offload_tx_10GbE.mem' start='0x30C0' end='0x3100' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3120' /><slave name='reg_remu.mem' start='0x3120' end='0x3140' /><slave name='reg_epcs.mem' start='0x3140' end='0x3160' /><slave name='reg_diag_bg_1GbE.mem' start='0x3160' end='0x3180' /><slave name='reg_io_ddr.mem' start='0x3180' end='0x3190' /><slave name='reg_dpmm_ctrl.mem' start='0x3190' end='0x3198' /><slave name='reg_dpmm_data.mem' start='0x3198' end='0x31A0' /><slave name='reg_mmdp_ctrl.mem' start='0x31A0' end='0x31A8' /><slave name='reg_mmdp_data.mem' start='0x31A8' end='0x31B0' /><slave name='pio_pps.mem' start='0x31B0' end='0x31B8' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x3200' end='0x3400' /><slave name='reg_dp_offload_tx_1GbE_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='reg_dp_offload_tx_10GbE_hdr_dat.mem' start='0x7000' end='0x7400' /><slave name='reg_dp_offload_rx_10GbE_hdr_dat.mem' start='0x7400' end='0x7800' /><slave name='ram_diag_bg_1GbE.mem' start='0x8000' end='0x10000' /><slave name='ram_diag_data_buffer_1GbE.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' /><slave name='ram_diag_data_buffer_10GbE.mem' start='0x70000' end='0x80000' /><slave name='ram_diag_bg_10GbE.mem' start='0x80000' end='0x88000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="125000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" />
@@ -2215,7 +2521,11 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_bsn_monitor">
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_bsn_monitor_1GbE">
<parameter name="g_adr_w" value="7" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
@@ -2224,7 +2534,7 @@ q]]></parameter>
kind="avs_common_mm"
version="1.0"
enabled="1"
- name="reg_dp_offload_tx">
+ name="reg_dp_offload_tx_1GbE">
<parameter name="g_adr_w" value="4" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
@@ -2233,7 +2543,7 @@ q]]></parameter>
kind="avs_common_mm"
version="1.0"
enabled="1"
- name="reg_dp_offload_tx_hdr_dat">
+ name="reg_dp_offload_tx_1GbE_hdr_dat">
<parameter name="g_adr_w" value="8" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
@@ -2242,7 +2552,7 @@ q]]></parameter>
kind="avs_common_mm"
version="1.0"
enabled="1"
- name="reg_dp_offload_rx_hdr_dat">
+ name="reg_dp_offload_rx_1GbE_hdr_dat">
<parameter name="g_adr_w" value="8" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
@@ -2251,7 +2561,7 @@ q]]></parameter>
kind="avs_common_mm"
version="1.0"
enabled="1"
- name="reg_diag_data_buffer">
+ name="reg_diag_data_buffer_1GbE">
<parameter name="g_adr_w" value="5" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
@@ -2260,17 +2570,25 @@ q]]></parameter>
kind="avs_common_mm"
version="1.0"
enabled="1"
- name="ram_diag_data_buffer">
+ name="ram_diag_data_buffer_1GbE">
<parameter name="g_adr_w" value="14" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_diag_bg">
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_bg_1GbE">
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_diag_bg">
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="ram_diag_bg_1GbE">
<parameter name="g_adr_w" value="13" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
@@ -2289,7 +2607,34 @@ q]]></parameter>
kind="avs_common_mm"
version="1.0"
enabled="1"
- name="reg_dp_offload_tx_1gbe">
+ name="reg_bsn_monitor_10GbE">
+ <parameter name="g_adr_w" value="7" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_bg_10GbE">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="ram_diag_bg_10GbE">
+ <parameter name="g_adr_w" value="13" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dp_offload_tx_10GbE">
<parameter name="g_adr_w" value="4" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
@@ -2298,11 +2643,38 @@ q]]></parameter>
kind="avs_common_mm"
version="1.0"
enabled="1"
- name="reg_dp_offload_tx_1gbe_hdr_dat">
+ name="reg_dp_offload_tx_10GbE_hdr_dat">
+ <parameter name="g_adr_w" value="8" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dp_offload_rx_10GbE_hdr_dat">
<parameter name="g_adr_w" value="8" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_data_buffer_10GbE">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="ram_diag_data_buffer_10GbE">
+ <parameter name="g_adr_w" value="14" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
<connection
kind="avalon"
version="11.1"
@@ -2364,7 +2736,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x01c0" />
+ <parameter name="baseAddress" value="0x3020" />
</connection>
<connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
<parameter name="irqNumber" value="1" />
@@ -2375,7 +2747,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_unb_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x01e0" />
+ <parameter name="baseAddress" value="0x3100" />
</connection>
<connection
kind="avalon"
@@ -2407,7 +2779,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3020" />
+ <parameter name="baseAddress" value="0x3120" />
</connection>
<connection
kind="avalon"
@@ -2415,7 +2787,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3090" />
+ <parameter name="baseAddress" value="0x3190" />
</connection>
<connection
kind="avalon"
@@ -2423,7 +2795,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3098" />
+ <parameter name="baseAddress" value="0x3198" />
</connection>
<connection
kind="avalon"
@@ -2431,7 +2803,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x30a0" />
+ <parameter name="baseAddress" value="0x31a0" />
</connection>
<connection
kind="avalon"
@@ -2439,7 +2811,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x30a8" />
+ <parameter name="baseAddress" value="0x31a8" />
</connection>
<connection
kind="avalon"
@@ -2447,7 +2819,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3040" />
+ <parameter name="baseAddress" value="0x3140" />
</connection>
<connection
kind="avalon"
@@ -2455,7 +2827,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x30b0" />
+ <parameter name="baseAddress" value="0x31b0" />
</connection>
<connection
kind="avalon"
@@ -2479,7 +2851,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0100" />
+ <parameter name="baseAddress" value="0x3040" />
</connection>
<connection
kind="avalon"
@@ -2698,12 +3070,12 @@ q]]></parameter>
kind="reset"
version="11.1"
start="clk_0.clk_reset"
- end="reg_bsn_monitor.system_reset" />
+ end="reg_bsn_monitor_1GbE.system_reset" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="reg_bsn_monitor.mem">
+ end="reg_bsn_monitor_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0200" />
</connection>
@@ -2711,22 +3083,22 @@ q]]></parameter>
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="reg_bsn_monitor.system_reset" />
+ end="reg_bsn_monitor_1GbE.system_reset" />
<connection
kind="reset"
version="11.1"
start="clk_0.clk_reset"
- end="reg_dp_offload_rx_hdr_dat.system_reset" />
+ end="reg_dp_offload_rx_1GbE_hdr_dat.system_reset" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="reg_dp_offload_rx_hdr_dat.system_reset" />
+ end="reg_dp_offload_rx_1GbE_hdr_dat.system_reset" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="reg_dp_offload_rx_hdr_dat.mem">
+ end="reg_dp_offload_rx_1GbE_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0400" />
</connection>
@@ -2734,35 +3106,35 @@ q]]></parameter>
kind="reset"
version="11.1"
start="clk_0.clk_reset"
- end="reg_dp_offload_tx.system_reset" />
+ end="reg_dp_offload_tx_1GbE.system_reset" />
<connection
kind="reset"
version="11.1"
start="clk_0.clk_reset"
- end="reg_dp_offload_tx_hdr_dat.system_reset" />
+ end="reg_dp_offload_tx_1GbE_hdr_dat.system_reset" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="reg_dp_offload_tx_hdr_dat.system_reset" />
+ end="reg_dp_offload_tx_1GbE_hdr_dat.system_reset" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="reg_dp_offload_tx.system_reset" />
+ end="reg_dp_offload_tx_1GbE.system_reset" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="reg_dp_offload_tx.mem">
+ end="reg_dp_offload_tx_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0140" />
+ <parameter name="baseAddress" value="0x3080" />
</connection>
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="reg_dp_offload_tx_hdr_dat.mem">
+ end="reg_dp_offload_tx_1GbE_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3400" />
</connection>
@@ -2770,7 +3142,7 @@ q]]></parameter>
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="reg_diag_data_buffer.mem">
+ end="reg_diag_data_buffer_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0080" />
</connection>
@@ -2778,7 +3150,7 @@ q]]></parameter>
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="ram_diag_data_buffer.mem">
+ end="ram_diag_data_buffer_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010000" />
</connection>
@@ -2786,35 +3158,35 @@ q]]></parameter>
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="reg_diag_data_buffer.system_reset" />
+ end="reg_diag_data_buffer_1GbE.system_reset" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="ram_diag_data_buffer.system_reset" />
+ end="ram_diag_data_buffer_1GbE.system_reset" />
<connection
kind="reset"
version="11.1"
start="clk_0.clk_reset"
- end="reg_diag_data_buffer.system_reset" />
+ end="reg_diag_data_buffer_1GbE.system_reset" />
<connection
kind="reset"
version="11.1"
start="clk_0.clk_reset"
- end="ram_diag_data_buffer.system_reset" />
+ end="ram_diag_data_buffer_1GbE.system_reset" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="reg_diag_bg.mem">
+ end="reg_diag_bg_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3060" />
+ <parameter name="baseAddress" value="0x3160" />
</connection>
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="ram_diag_bg.mem">
+ end="ram_diag_bg_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x8000" />
</connection>
@@ -2822,22 +3194,22 @@ q]]></parameter>
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="ram_diag_bg.system_reset" />
+ end="ram_diag_bg_1GbE.system_reset" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="reg_diag_bg.system_reset" />
+ end="reg_diag_bg_1GbE.system_reset" />
<connection
kind="reset"
version="11.1"
start="clk_0.clk_reset"
- end="reg_diag_bg.system_reset" />
+ end="reg_diag_bg_1GbE.system_reset" />
<connection
kind="reset"
version="11.1"
start="clk_0.clk_reset"
- end="ram_diag_bg.system_reset" />
+ end="ram_diag_bg_1GbE.system_reset" />
<connection
kind="reset"
version="11.1"
@@ -2919,42 +3291,42 @@ q]]></parameter>
kind="clock"
version="11.1"
start="clk_0.clk"
- end="reg_bsn_monitor.system" />
+ end="reg_bsn_monitor_1GbE.system" />
<connection
kind="clock"
version="11.1"
start="clk_0.clk"
- end="reg_dp_offload_tx.system" />
+ end="reg_dp_offload_tx_1GbE.system" />
<connection
kind="clock"
version="11.1"
start="clk_0.clk"
- end="reg_dp_offload_tx_hdr_dat.system" />
+ end="reg_dp_offload_tx_1GbE_hdr_dat.system" />
<connection
kind="clock"
version="11.1"
start="clk_0.clk"
- end="reg_dp_offload_rx_hdr_dat.system" />
+ end="reg_dp_offload_rx_1GbE_hdr_dat.system" />
<connection
kind="clock"
version="11.1"
start="clk_0.clk"
- end="reg_diag_data_buffer.system" />
+ end="reg_diag_data_buffer_1GbE.system" />
<connection
kind="clock"
version="11.1"
start="clk_0.clk"
- end="ram_diag_data_buffer.system" />
+ end="ram_diag_data_buffer_1GbE.system" />
<connection
kind="clock"
version="11.1"
start="clk_0.clk"
- end="reg_diag_bg.system" />
+ end="reg_diag_bg_1GbE.system" />
<connection
kind="clock"
version="11.1"
start="clk_0.clk"
- end="ram_diag_bg.system" />
+ end="ram_diag_bg_1GbE.system" />
<connection
kind="clock"
version="11.1"
@@ -2977,52 +3349,190 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_io_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3080" />
+ <parameter name="baseAddress" value="0x3180" />
</connection>
<connection
kind="reset"
version="11.1"
start="clk_0.clk_reset"
- end="reg_dp_offload_tx_1gbe.system_reset" />
+ end="reg_bsn_monitor_10GbE.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_bsn_monitor_10GbE.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_diag_bg_10GbE.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_diag_bg_10GbE.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="ram_diag_bg_10GbE.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="ram_diag_bg_10GbE.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_dp_offload_tx_10GbE.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_dp_offload_tx_10GbE.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_dp_offload_tx_10GbE_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_dp_offload_tx_10GbE_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_dp_offload_rx_10GbE_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_dp_offload_rx_10GbE_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_diag_data_buffer_10GbE.system_reset" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="reg_dp_offload_tx_1gbe.system_reset" />
+ end="reg_diag_data_buffer_10GbE.system_reset" />
<connection
kind="reset"
version="11.1"
start="clk_0.clk_reset"
- end="reg_dp_offload_tx_1gbe_hdr_dat.system_reset" />
+ end="ram_diag_data_buffer_10GbE.system_reset" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="reg_dp_offload_tx_1gbe_hdr_dat.system_reset" />
+ end="ram_diag_data_buffer_10GbE.system_reset" />
<connection
kind="clock"
version="11.1"
start="clk_0.clk"
- end="reg_dp_offload_tx_1gbe.system" />
+ end="reg_bsn_monitor_10GbE.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_10GbE.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3200" />
+ </connection>
<connection
kind="clock"
version="11.1"
start="clk_0.clk"
- end="reg_dp_offload_tx_1gbe_hdr_dat.system" />
+ end="reg_dp_offload_tx_10GbE.system" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="reg_dp_offload_tx_1gbe.mem">
+ end="reg_dp_offload_tx_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0180" />
+ <parameter name="baseAddress" value="0x30c0" />
</connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_dp_offload_tx_10GbE_hdr_dat.system" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="reg_dp_offload_tx_1gbe_hdr_dat.mem">
+ end="reg_dp_offload_tx_10GbE_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x7000" />
</connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_dp_offload_rx_10GbE_hdr_dat.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_rx_10GbE_hdr_dat.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x7400" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_diag_bg_10GbE.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_bg_10GbE.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0100" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="ram_diag_bg_10GbE.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_diag_bg_10GbE.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00080000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_diag_data_buffer_10GbE.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_data_buffer_10GbE.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0180" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="ram_diag_data_buffer_10GbE.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_diag_data_buffer_10GbE.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00070000" />
+ </connection>
</system>
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
index 8b130ff5684c1088c3d32b22edbd6c4637f8d664..b63296d9cd6f30a8831544b9d423240a408fb670 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
@@ -38,7 +38,7 @@ ENTITY unb1_test_10GbE IS
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
g_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
- g_use_MB_I : NATURAL := 1; -- 1: use MB_I 0: do not use
+ g_use_MB_I : NATURAL := 0; -- 1: use MB_I 0: do not use
g_use_MB_II : NATURAL := 0
);
PORT (
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/bgdb_stream_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/bgdb_stream_test.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e50ac621d8b7e94d3fba457d38f38aa74219716b
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/bgdb_stream_test.vhd
@@ -0,0 +1,345 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, diag_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE work.unb1_test_pkg.ALL;
+
+ENTITY bgdb_stream_test IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_nof_streams : NATURAL;
+ g_data_w : NATURAL;
+
+ g_bg_block_size : NATURAL := 900;
+ g_bg_gapsize : NATURAL := 100;
+ g_bg_blocks_per_sync : NATURAL := 200000;
+
+ g_def_block_size : NATURAL := 0;
+ g_max_nof_blocks_per_packet : NATURAL := 0;
+ g_remove_crc : BOOLEAN
+ );
+ PORT (
+ -- System
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+
+ ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+
+ -- blockgen mm
+ reg_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG control register (one for all streams)
+ reg_diag_bg_miso : OUT t_mem_miso;
+ ram_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream)
+ ram_diag_bg_miso : OUT t_mem_miso;
+
+ -- dp_offload_tx
+ reg_dp_offload_tx_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_offload_tx_miso : OUT t_mem_miso;
+ reg_dp_offload_tx_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_offload_tx_hdr_dat_miso : OUT t_mem_miso;
+
+ -- to MAC
+ dp_offload_tx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ dp_offload_tx_src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
+
+ -- dp_offload_rx
+ reg_dp_offload_rx_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_offload_rx_hdr_dat_miso : OUT t_mem_miso;
+
+ -- from MAC
+ dp_offload_rx_snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ dp_offload_rx_snk_out_arr : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+
+ -- bsn
+ reg_bsn_monitor_mosi : IN t_mem_mosi;
+ reg_bsn_monitor_miso : OUT t_mem_miso;
+
+ -- databuffer
+ reg_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_diag_data_buf_miso : OUT t_mem_miso;
+ ram_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_diag_data_buf_miso : OUT t_mem_miso
+ );
+END bgdb_stream_test;
+
+
+
+ARCHITECTURE str OF bgdb_stream_test IS
+
+ -- Block generator
+ CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
+ '0', -- enable_sync
+ TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
+
+
+ CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111011111100"&"0001"&"101111111";
+ CONSTANT c_nof_crc_words : NATURAL := 1;
+ CONSTANT c_max_nof_words_per_block : NATURAL := g_bg_block_size;
+ CONSTANT c_min_nof_words_per_block : NATURAL := 1;
+ CONSTANT c_def_nof_blocks_per_packet : NATURAL := 1;
+
+ SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL block_gen_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+ SIGNAL fifo_block_gen_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL fifo_block_gen_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+
+ SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+
+ SIGNAL hdr_fields_in_arr : t_slv_1024_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL hdr_fields_out_arr : t_slv_1024_arr(g_nof_streams-1 DOWNTO 0);
+
+ SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+
+BEGIN
+
+ gen_hdr_in_fields : FOR i IN 0 TO g_nof_streams-1 GENERATE
+ -- dst = src
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_dst_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_dst_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
+
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr")) <= x"0A0A" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_dst_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_dst_addr")) <= x"0A0A" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
+
+ -- dst port goes through 4000,4001,4002
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_src_port") DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= TO_UVEC(4000+i, 16);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port") DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= TO_UVEC(4000+i, 16);
+
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_sync" ) DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )) <= slv(fifo_block_gen_src_out_arr(i).sync);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )) <= fifo_block_gen_src_out_arr(i).bsn(59 DOWNTO 0);
+ END GENERATE;
+
+
+ -----------------------------------------------------------------------------
+ -- TX: Block generator and DP fifo
+ -----------------------------------------------------------------------------
+ u_mms_diag_block_gen: ENTITY diag_lib.mms_diag_block_gen
+ GENERIC MAP (
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_name_prefix => "../../counter_data_" & NATURAL'IMAGE(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,--block_gen_src_1GbE_out_arr,
+ out_siso_arr => block_gen_src_in_arr,--block_gen_src_1GbE_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,--reg_diag_bg_1GbE_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,--reg_diag_bg_1GbE_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,--ram_diag_bg_1GbE_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso --ram_diag_bg_1GbE_miso
+ );
+
+ gen_dp_fifo_sc : FOR i IN 0 TO g_nof_streams-1 GENERATE
+ u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
+ GENERIC MAP (
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => TRUE,
+ g_use_sync => TRUE,
+ g_fifo_size => 50
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
+ END GENERATE;
+
+ --gen_bg_src_out_arr : FOR i IN 0 TO g_nof_streams-1 GENERATE
+ -- bg_src_out_arr(i) <= fifo_block_gen_src_out_arr(i);
+ --END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- TX: dp_offload_tx
+ -----------------------------------------------------------------------------
+ u_dp_offload_tx : ENTITY dp_lib.dp_offload_tx
+ GENERIC MAP (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => FALSE,
+ g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_def_nof_words_per_block => g_def_block_size,
+ g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_def_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ reg_mosi => reg_dp_offload_tx_mosi,
+ reg_miso => reg_dp_offload_tx_miso,
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams-1 DOWNTO 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams-1 DOWNTO 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams-1 DOWNTO 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams-1 DOWNTO 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams-1 DOWNTO 0)
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- RX: dp_offload_rx
+ -----------------------------------------------------------------------------
+ u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
+ GENERIC MAP (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
+
+
+ gen_hdr_out_fields : FOR i IN 0 TO g_nof_streams-1 GENERATE
+ diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )));
+ diag_data_buf_snk_in_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )), c_dp_stream_bsn_w);
+ END GENERATE;
+
+
+ -----------------------------------------------------------------------------
+ -- RX: Data buffers and BSN monitors
+ -----------------------------------------------------------------------------
+ dp_offload_rx_src_in_arr <= diag_data_buf_snk_out_arr(g_nof_streams-1 downto 0);
+
+ gen_bsn_mon_in : FOR i IN 0 TO g_nof_streams-1 GENERATE
+ diag_data_buf_snk_in_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
+ diag_data_buf_snk_in_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
+ diag_data_buf_snk_in_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
+ diag_data_buf_snk_in_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
+ diag_data_buf_snk_in_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
+ END GENERATE;
+
+
+
+ u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
+ GENERIC MAP (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => TRUE,
+ g_sync_timeout => g_bg_blocks_per_sync*(g_bg_block_size+g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync+1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync*g_bg_block_size+1),
+ g_log_first_bsn => TRUE
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams-1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams-1 downto 0)
+ );
+
+
+ diag_data_buf_snk_out_arr <= (OTHERS=>c_dp_siso_rdy);
+
+ u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
+ GENERIC MAP (
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, --g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => FALSE -- sync by reading last address of data buffer
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+
+ --in_sync => diag_data_buf_snk_in_arr(0).sop,
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
+
+END str;
+
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 72b41764928565691643720850902642d6bbf974..06a5ede9de8fe19e6e44742270a500c7a37b1ef6 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -39,6 +39,7 @@ USE tech_tse_lib.tech_tse_pkg.ALL;
USE tech_tse_lib.tb_tech_tse_pkg.ALL;
USE work.qsys_unb1_test_pkg.ALL;
USE reorder_lib.reorder_pkg.ALL;
+USE work.unb1_test_pkg.ALL;
ENTITY mmm_unb1_test IS
@@ -46,12 +47,10 @@ ENTITY mmm_unb1_test IS
g_sim : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
- g_nof_streams_1GbE : NATURAL;
+ g_nof_streams_1GbE : NATURAL;
g_nof_streams_10GbE : NATURAL;
g_nof_streams_ddr : NATURAL;
- g_bg_block_size : NATURAL;
- g_hdr_field_arr : t_common_field_arr;
- g_nof_dp_offload_tx : NATURAL
+ g_bg_block_size : NATURAL
);
PORT (
mm_rst : IN STD_LOGIC;
@@ -107,28 +106,52 @@ ENTITY mmm_unb1_test IS
reg_remu_mosi : OUT t_mem_mosi;
reg_remu_miso : IN t_mem_miso;
- ram_diag_bg_mosi : OUT t_mem_mosi;
- ram_diag_bg_miso : IN t_mem_miso;
- reg_diag_bg_mosi : OUT t_mem_mosi;
- reg_diag_bg_miso : IN t_mem_miso;
-
- reg_dp_offload_tx_mosi_arr : OUT t_mem_mosi_arr(g_nof_dp_offload_tx-1 DOWNTO 0);
- reg_dp_offload_tx_miso_arr : IN t_mem_miso_arr(g_nof_dp_offload_tx-1 DOWNTO 0);
-
- reg_dp_offload_tx_hdr_dat_mosi_arr : OUT t_mem_mosi_arr(g_nof_dp_offload_tx-1 DOWNTO 0);
- reg_dp_offload_tx_hdr_dat_miso_arr : IN t_mem_miso_arr(g_nof_dp_offload_tx-1 DOWNTO 0);
-
- reg_dp_offload_rx_hdr_dat_mosi : OUT t_mem_mosi;
- reg_dp_offload_rx_hdr_dat_miso : IN t_mem_miso;
-
- reg_bsn_monitor_mosi : OUT t_mem_mosi;
- reg_bsn_monitor_miso : IN t_mem_miso;
-
- ram_diag_data_buf_mosi : OUT t_mem_mosi;
- ram_diag_data_buf_miso : IN t_mem_miso;
- reg_diag_data_buf_mosi : OUT t_mem_mosi;
- reg_diag_data_buf_miso : IN t_mem_miso;
-
+ -- block gen
+ ram_diag_bg_1GbE_mosi : OUT t_mem_mosi;
+ ram_diag_bg_1GbE_miso : IN t_mem_miso;
+ reg_diag_bg_1GbE_mosi : OUT t_mem_mosi;
+ reg_diag_bg_1GbE_miso : IN t_mem_miso;
+
+ ram_diag_bg_10GbE_mosi : OUT t_mem_mosi;
+ ram_diag_bg_10GbE_miso : IN t_mem_miso;
+ reg_diag_bg_10GbE_mosi : OUT t_mem_mosi;
+ reg_diag_bg_10GbE_miso : IN t_mem_miso;
+
+ -- dp_offload_tx
+ reg_dp_offload_tx_1GbE_mosi : OUT t_mem_mosi;
+ reg_dp_offload_tx_1GbE_miso : IN t_mem_miso;
+ reg_dp_offload_tx_1GbE_hdr_dat_mosi : OUT t_mem_mosi;
+ reg_dp_offload_tx_1GbE_hdr_dat_miso : IN t_mem_miso;
+
+ reg_dp_offload_tx_10GbE_mosi : OUT t_mem_mosi;
+ reg_dp_offload_tx_10GbE_miso : IN t_mem_miso;
+ reg_dp_offload_tx_10GbE_hdr_dat_mosi : OUT t_mem_mosi;
+ reg_dp_offload_tx_10GbE_hdr_dat_miso : IN t_mem_miso;
+
+ -- dp_offload_rx
+ reg_dp_offload_rx_1GbE_hdr_dat_mosi : OUT t_mem_mosi;
+ reg_dp_offload_rx_1GbE_hdr_dat_miso : IN t_mem_miso;
+ reg_dp_offload_rx_10GbE_hdr_dat_mosi : OUT t_mem_mosi;
+ reg_dp_offload_rx_10GbE_hdr_dat_miso : IN t_mem_miso;
+
+ -- bsn
+ reg_bsn_monitor_1GbE_mosi : OUT t_mem_mosi;
+ reg_bsn_monitor_1GbE_miso : IN t_mem_miso;
+ reg_bsn_monitor_10GbE_mosi : OUT t_mem_mosi;
+ reg_bsn_monitor_10GbE_miso : IN t_mem_miso;
+
+ -- databuffer
+ ram_diag_data_buf_1GbE_mosi : OUT t_mem_mosi;
+ ram_diag_data_buf_1GbE_miso : IN t_mem_miso;
+ reg_diag_data_buf_1GbE_mosi : OUT t_mem_mosi;
+ reg_diag_data_buf_1GbE_miso : IN t_mem_miso;
+
+ ram_diag_data_buf_10GbE_mosi : OUT t_mem_mosi;
+ ram_diag_data_buf_10GbE_miso : IN t_mem_miso;
+ reg_diag_data_buf_10GbE_mosi : OUT t_mem_mosi;
+ reg_diag_data_buf_10GbE_miso : IN t_mem_miso;
+
+ -- tr_10GbE
reg_tr_10GbE_mosi : OUT t_mem_mosi;
reg_tr_10GbE_miso : IN t_mem_miso;
reg_tr_xaui_mosi : OUT t_mem_mosi;
@@ -144,23 +167,30 @@ END mmm_unb1_test;
ARCHITECTURE str OF mmm_unb1_test IS
- CONSTANT g_nof_streams : NATURAL := g_nof_streams_1GbE + g_nof_streams_10GbE + g_nof_streams_ddr;
- CONSTANT g_nof_streams_eth : NATURAL := g_nof_streams_1GbE + g_nof_streams_10GbE;
-
-- Block generator
- CONSTANT c_ram_diag_bg_addr_w : NATURAL := ceil_log2(g_nof_streams* pow2(ceil_log2(g_bg_block_size))); -- 5*10 --> 13
+ CONSTANT c_ram_diag_bg_1GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(ceil_log2(g_bg_block_size)));
+ CONSTANT c_ram_diag_bg_10GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb1_board_peripherals_mm_reg_default
- CONSTANT c_reg_dp_offload_tx_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_eth * pow2(c_reg_dp_offload_tx_adr_w)); -- 4*1
+ CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb1_board_peripherals_mm_reg_default
+ CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
+ CONSTANT c_reg_dp_offload_tx_10GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_dp_offload_tx_adr_w));
- CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
- CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words);
- CONSTANT c_reg_dp_offload_tx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_eth * pow2(c_reg_dp_offload_tx_hdr_dat_adr_w));
+ CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
+ CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
- CONSTANT c_reg_dp_offload_rx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
- CONSTANT c_reg_dp_offload_rx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_hdr_dat_nof_words);
- CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_eth * pow2(c_reg_dp_offload_rx_hdr_dat_adr_w));
+ CONSTANT c_reg_dp_offload_tx_10GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ CONSTANT c_reg_dp_offload_tx_10GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_10GbE_hdr_dat_nof_words);
+ CONSTANT c_reg_dp_offload_tx_10GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_dp_offload_tx_10GbE_hdr_dat_adr_w));
+
+ CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
+ CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
+
+ CONSTANT c_reg_dp_offload_rx_10GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ CONSTANT c_reg_dp_offload_rx_10GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_10GbE_hdr_dat_nof_words);
+ CONSTANT c_reg_dp_offload_rx_10GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_dp_offload_rx_10GbE_hdr_dat_adr_w));
-- reorder
-- v--- FIXME: g_frame_size_in
@@ -175,15 +205,14 @@ ARCHITECTURE str OF mmm_unb1_test IS
CONSTANT c_reg_tr_xaui_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_tr_xaui_adr_w));
-- BSN monitors
- CONSTANT c_reg_rsp_bsn_monitor_adr_w : NATURAL := ceil_log2(g_nof_streams * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
+ CONSTANT c_reg_rsp_bsn_monitor_1GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
+ CONSTANT c_reg_rsp_bsn_monitor_10GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
CONSTANT c_dp_reg_mm_nof_words : NATURAL := 1;
CONSTANT c_dp_reg_mm_adr_w : NATURAL := ceil_log2(c_eth_nof_udp_ports * pow2(ceil_log2(c_dp_reg_mm_nof_words)));
-- Simulation
- CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
-
CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
@@ -244,44 +273,60 @@ BEGIN
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GbE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+
+ u_mm_file_ram_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GbE")
+ PORT MAP(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
+
+ u_mm_file_reg_diag_bg_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+
+ u_mm_file_ram_diag_bg_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
+ PORT MAP(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+
- u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+ u_mm_file_reg_dp_offload_tx_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_mosi, reg_dp_offload_tx_10GbE_miso);
- u_mm_file_reg_dp_offload_tx_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi_arr(1), reg_dp_offload_tx_miso_arr(1) );
- u_mm_file_reg_dp_offload_tx_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi_arr(0), reg_dp_offload_tx_miso_arr(0) );
+ u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
+ u_mm_file_reg_dp_offload_tx_10GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE_HDR_DAT")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_hdr_dat_mosi, reg_dp_offload_tx_10GbE_hdr_dat_miso);
- u_mm_file_reg_dp_offload_tx_1_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi_arr(1), reg_dp_offload_tx_hdr_dat_miso_arr(1) );
- u_mm_file_reg_dp_offload_tx_0_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi_arr(0), reg_dp_offload_tx_hdr_dat_miso_arr(0) );
+ u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso );
+ u_mm_file_reg_dp_offload_rx_10GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_10GBE_HDR_DAT")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_10GbE_hdr_dat_mosi, reg_dp_offload_rx_10GbE_hdr_dat_miso );
- u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
+ u_mm_file_reg_bsn_monitor_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso );
- u_mm_file_reg_bsn_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+ u_mm_file_reg_bsn_monitor_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso );
- u_mm_file_ram_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
- PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+ u_mm_file_ram_diag_data_buffer_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
+ u_mm_file_ram_diag_data_buffer_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
- u_mm_file_reg_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
- PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+ u_mm_file_reg_diag_data_buffer_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
+ u_mm_file_reg_diag_data_buffer_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
- u_mm_file_ram_ss_ss_transp : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- PORT MAP(mm_rst, mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
+ u_mm_file_ram_ss_ss_transp : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ PORT MAP(mm_rst, mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
- u_mm_file_reg_io_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
- PORT MAP(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+ u_mm_file_reg_io_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
+ PORT MAP(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
@@ -378,7 +423,7 @@ BEGIN
-- the_reg_dpmm_data
coe_clk_export_from_the_reg_dpmm_data => OPEN,
coe_reset_export_from_the_reg_dpmm_data => OPEN,
- coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
+ coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0 DOWNTO 0),
coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
@@ -387,7 +432,7 @@ BEGIN
-- the_reg_dpmm_ctrl
coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
+ coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0 DOWNTO 0),
coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
@@ -396,7 +441,7 @@ BEGIN
-- the_reg_mmdp_data
coe_clk_export_from_the_reg_mmdp_data => OPEN,
coe_reset_export_from_the_reg_mmdp_data => OPEN,
- coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
+ coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0 DOWNTO 0),
coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
@@ -405,7 +450,7 @@ BEGIN
-- the_reg_mmdp_ctrl
coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
+ coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0 DOWNTO 0),
coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
@@ -432,7 +477,7 @@ BEGIN
-- the_pio_pps
coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
@@ -462,7 +507,7 @@ BEGIN
-- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
coe_clk_export_from_the_reg_wdi => OPEN,
coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0 DOWNTO 0),
coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
@@ -488,116 +533,166 @@ BEGIN
coe_write_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wr,
coe_writedata_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0),
- -- the_reg_diag_bg
- reg_diag_bg_address_export => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
- reg_diag_bg_clk_export => OPEN,
- reg_diag_bg_read_export => reg_diag_bg_mosi.rd,
- reg_diag_bg_readdata_export => reg_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_diag_bg_reset_export => OPEN,
- reg_diag_bg_write_export => reg_diag_bg_mosi.wr,
- reg_diag_bg_writedata_export => reg_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_ram_diag_bg
- ram_diag_bg_address_export => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w-1 DOWNTO 0),
- ram_diag_bg_clk_export => OPEN,
- ram_diag_bg_read_export => ram_diag_bg_mosi.rd,
- ram_diag_bg_readdata_export => ram_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
- ram_diag_bg_reset_export => OPEN,
- ram_diag_bg_write_export => ram_diag_bg_mosi.wr,
- ram_diag_bg_writedata_export => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-
- -- the_reg_dp_offload_tx
- reg_dp_offload_tx_address_export => reg_dp_offload_tx_mosi_arr(1).address(c_reg_dp_offload_tx_multi_adr_w-1 DOWNTO 0),
- reg_dp_offload_tx_clk_export => OPEN,
- reg_dp_offload_tx_read_export => reg_dp_offload_tx_mosi_arr(1).rd,
- reg_dp_offload_tx_readdata_export => reg_dp_offload_tx_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
- reg_dp_offload_tx_reset_export => OPEN,
- reg_dp_offload_tx_write_export => reg_dp_offload_tx_mosi_arr(1).wr,
- reg_dp_offload_tx_writedata_export => reg_dp_offload_tx_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_offload_tx_hdr_dat
- reg_dp_offload_tx_hdr_dat_address_export => reg_dp_offload_tx_hdr_dat_mosi_arr(1).address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w-1 DOWNTO 0),
- reg_dp_offload_tx_hdr_dat_clk_export => OPEN,
- reg_dp_offload_tx_hdr_dat_read_export => reg_dp_offload_tx_hdr_dat_mosi_arr(1).rd,
- reg_dp_offload_tx_hdr_dat_readdata_export => reg_dp_offload_tx_hdr_dat_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
- reg_dp_offload_tx_hdr_dat_reset_export => OPEN,
- reg_dp_offload_tx_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi_arr(1).wr,
- reg_dp_offload_tx_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-
-
- -- the_reg_dp_offload_tx_1gbe
- reg_dp_offload_tx_1gbe_address_export => reg_dp_offload_tx_mosi_arr(0).address(c_reg_dp_offload_tx_multi_adr_w-1 DOWNTO 0),
- reg_dp_offload_tx_1gbe_clk_export => OPEN,
- reg_dp_offload_tx_1gbe_read_export => reg_dp_offload_tx_mosi_arr(0).rd,
- reg_dp_offload_tx_1gbe_readdata_export => reg_dp_offload_tx_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
- reg_dp_offload_tx_1gbe_reset_export => OPEN,
- reg_dp_offload_tx_1gbe_write_export => reg_dp_offload_tx_mosi_arr(0).wr,
- reg_dp_offload_tx_1gbe_writedata_export => reg_dp_offload_tx_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_offload_tx_1gbe_hdr_dat
- reg_dp_offload_tx_1gbe_hdr_dat_address_export => reg_dp_offload_tx_hdr_dat_mosi_arr(0).address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w-1 DOWNTO 0),
- reg_dp_offload_tx_1gbe_hdr_dat_clk_export => OPEN,
- reg_dp_offload_tx_1gbe_hdr_dat_read_export => reg_dp_offload_tx_hdr_dat_mosi_arr(0).rd,
- reg_dp_offload_tx_1gbe_hdr_dat_readdata_export => reg_dp_offload_tx_hdr_dat_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
- reg_dp_offload_tx_1gbe_hdr_dat_reset_export => OPEN,
- reg_dp_offload_tx_1gbe_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi_arr(0).wr,
- reg_dp_offload_tx_1gbe_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-
-
- -- the_reg_dp_offload_rx_hdr_dat
- reg_dp_offload_rx_hdr_dat_address_export => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0),
- reg_dp_offload_rx_hdr_dat_clk_export => OPEN,
- reg_dp_offload_rx_hdr_dat_read_export => reg_dp_offload_rx_hdr_dat_mosi.rd,
- reg_dp_offload_rx_hdr_dat_readdata_export => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dp_offload_rx_hdr_dat_reset_export => OPEN,
- reg_dp_offload_rx_hdr_dat_write_export => reg_dp_offload_rx_hdr_dat_mosi.wr,
- reg_dp_offload_rx_hdr_dat_writedata_export => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_bsn_monitor
- reg_bsn_monitor_address_export => reg_bsn_monitor_mosi.address(c_reg_rsp_bsn_monitor_adr_w-1 DOWNTO 0),
- reg_bsn_monitor_clk_export => OPEN,
- reg_bsn_monitor_read_export => reg_bsn_monitor_mosi.rd,
- reg_bsn_monitor_readdata_export => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_monitor_reset_export => OPEN,
- reg_bsn_monitor_write_export => reg_bsn_monitor_mosi.wr,
- reg_bsn_monitor_writedata_export => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_ram_diag_data_buffer
- ram_diag_data_buffer_address_export => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
- ram_diag_data_buffer_clk_export => OPEN,
- ram_diag_data_buffer_read_export => ram_diag_data_buf_mosi.rd,
- ram_diag_data_buffer_readdata_export => ram_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
- ram_diag_data_buffer_reset_export => OPEN,
- ram_diag_data_buffer_write_export => ram_diag_data_buf_mosi.wr,
- ram_diag_data_buffer_writedata_export => ram_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_diag_data_buffer
- reg_diag_data_buffer_address_export => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
- reg_diag_data_buffer_clk_export => OPEN,
- reg_diag_data_buffer_read_export => reg_diag_data_buf_mosi.rd,
- reg_diag_data_buffer_readdata_export => reg_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_diag_data_buffer_reset_export => OPEN,
- reg_diag_data_buffer_write_export => reg_diag_data_buf_mosi.wr,
- reg_diag_data_buffer_writedata_export => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_reg_diag_bg_1GbE
+ reg_diag_bg_1GbE_address_export => reg_diag_bg_1GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
+ reg_diag_bg_1GbE_clk_export => OPEN,
+ reg_diag_bg_1GbE_read_export => reg_diag_bg_1GbE_mosi.rd,
+ reg_diag_bg_1GbE_readdata_export => reg_diag_bg_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_1GbE_reset_export => OPEN,
+ reg_diag_bg_1GbE_write_export => reg_diag_bg_1GbE_mosi.wr,
+ reg_diag_bg_1GbE_writedata_export => reg_diag_bg_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_ram_diag_bg_1GbE
+ ram_diag_bg_1GbE_address_export => ram_diag_bg_1GbE_mosi.address(c_ram_diag_bg_1GbE_addr_w-1 DOWNTO 0),
+ ram_diag_bg_1GbE_clk_export => OPEN,
+ ram_diag_bg_1GbE_read_export => ram_diag_bg_1GbE_mosi.rd,
+ ram_diag_bg_1GbE_readdata_export => ram_diag_bg_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_bg_1GbE_reset_export => OPEN,
+ ram_diag_bg_1GbE_write_export => ram_diag_bg_1GbE_mosi.wr,
+ ram_diag_bg_1GbE_writedata_export => ram_diag_bg_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_diag_bg_10GbE
+ reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
+ reg_diag_bg_10GbE_clk_export => OPEN,
+ reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
+ reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_10GbE_reset_export => OPEN,
+ reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
+ reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_ram_diag_bg_10GbE
+ ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w-1 DOWNTO 0),
+ ram_diag_bg_10GbE_clk_export => OPEN,
+ ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
+ ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_bg_10GbE_reset_export => OPEN,
+ ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
+ ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+
+ -- the_reg_dp_offload_tx_1GbE
+ reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
+ reg_dp_offload_tx_1GbE_clk_export => OPEN,
+ reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
+ reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_1GbE_reset_export => OPEN,
+ reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
+ reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_reg_dp_offload_tx_10GbE
+ reg_dp_offload_tx_10GbE_address_export => reg_dp_offload_tx_10GbE_mosi.address(c_reg_dp_offload_tx_10GbE_multi_adr_w-1 DOWNTO 0),
+ reg_dp_offload_tx_10GbE_clk_export => OPEN,
+ reg_dp_offload_tx_10GbE_read_export => reg_dp_offload_tx_10GbE_mosi.rd,
+ reg_dp_offload_tx_10GbE_readdata_export => reg_dp_offload_tx_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_10GbE_reset_export => OPEN,
+ reg_dp_offload_tx_10GbE_write_export => reg_dp_offload_tx_10GbE_mosi.wr,
+ reg_dp_offload_tx_10GbE_writedata_export => reg_dp_offload_tx_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+
+ -- the_reg_dp_offload_tx_1GbE_hdr_dat
+ reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
+ reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
+ reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_reg_dp_offload_tx_10GbE_hdr_dat
+ reg_dp_offload_tx_10GbE_hdr_dat_address_export => reg_dp_offload_tx_10GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_10GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ reg_dp_offload_tx_10GbE_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_tx_10GbE_hdr_dat_read_export => reg_dp_offload_tx_10GbE_hdr_dat_mosi.rd,
+ reg_dp_offload_tx_10GbE_hdr_dat_readdata_export => reg_dp_offload_tx_10GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_10GbE_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_tx_10GbE_hdr_dat_write_export => reg_dp_offload_tx_10GbE_hdr_dat_mosi.wr,
+ reg_dp_offload_tx_10GbE_hdr_dat_writedata_export => reg_dp_offload_tx_10GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+
+
+ -- the_reg_dp_offload_rx_1GbE_hdr_dat
+ reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
+ reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
+ reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_reg_dp_offload_rx_10GbE_hdr_dat
+ reg_dp_offload_rx_10GbE_hdr_dat_address_export => reg_dp_offload_rx_10GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_10GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ reg_dp_offload_rx_10GbE_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_rx_10GbE_hdr_dat_read_export => reg_dp_offload_rx_10GbE_hdr_dat_mosi.rd,
+ reg_dp_offload_rx_10GbE_hdr_dat_readdata_export => reg_dp_offload_rx_10GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_rx_10GbE_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_rx_10GbE_hdr_dat_write_export => reg_dp_offload_rx_10GbE_hdr_dat_mosi.wr,
+ reg_dp_offload_rx_10GbE_hdr_dat_writedata_export => reg_dp_offload_rx_10GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+
+ -- the_reg_bsn_monitor_1GbE
+ reg_bsn_monitor_1GbE_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w-1 DOWNTO 0),
+ reg_bsn_monitor_1GbE_clk_export => OPEN,
+ reg_bsn_monitor_1GbE_read_export => reg_bsn_monitor_1GbE_mosi.rd,
+ reg_bsn_monitor_1GbE_readdata_export => reg_bsn_monitor_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_1GbE_reset_export => OPEN,
+ reg_bsn_monitor_1GbE_write_export => reg_bsn_monitor_1GbE_mosi.wr,
+ reg_bsn_monitor_1GbE_writedata_export => reg_bsn_monitor_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_reg_bsn_monitor_10GbE
+ reg_bsn_monitor_10GbE_address_export => reg_bsn_monitor_10GbE_mosi.address(c_reg_rsp_bsn_monitor_10GbE_adr_w-1 DOWNTO 0),
+ reg_bsn_monitor_10GbE_clk_export => OPEN,
+ reg_bsn_monitor_10GbE_read_export => reg_bsn_monitor_10GbE_mosi.rd,
+ reg_bsn_monitor_10GbE_readdata_export => reg_bsn_monitor_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_10GbE_reset_export => OPEN,
+ reg_bsn_monitor_10GbE_write_export => reg_bsn_monitor_10GbE_mosi.wr,
+ reg_bsn_monitor_10GbE_writedata_export => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+
+ -- the_ram_diag_data_buffer_1GbE
+ ram_diag_data_buffer_1GbE_address_export => ram_diag_data_buf_1GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_1GbE_clk_export => OPEN,
+ ram_diag_data_buffer_1GbE_read_export => ram_diag_data_buf_1GbE_mosi.rd,
+ ram_diag_data_buffer_1GbE_readdata_export => ram_diag_data_buf_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_1GbE_reset_export => OPEN,
+ ram_diag_data_buffer_1GbE_write_export => ram_diag_data_buf_1GbE_mosi.wr,
+ ram_diag_data_buffer_1GbE_writedata_export => ram_diag_data_buf_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_ram_diag_data_buffer_10GbE
+ ram_diag_data_buffer_10GbE_address_export => ram_diag_data_buf_10GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_10GbE_clk_export => OPEN,
+ ram_diag_data_buffer_10GbE_read_export => ram_diag_data_buf_10GbE_mosi.rd,
+ ram_diag_data_buffer_10GbE_readdata_export => ram_diag_data_buf_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_10GbE_reset_export => OPEN,
+ ram_diag_data_buffer_10GbE_write_export => ram_diag_data_buf_10GbE_mosi.wr,
+ ram_diag_data_buffer_10GbE_writedata_export => ram_diag_data_buf_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+
+ -- the_reg_diag_data_buffer_1GbE
+ reg_diag_data_buffer_1GbE_address_export => reg_diag_data_buf_1GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_1GbE_clk_export => OPEN,
+ reg_diag_data_buffer_1GbE_read_export => reg_diag_data_buf_1GbE_mosi.rd,
+ reg_diag_data_buffer_1GbE_readdata_export => reg_diag_data_buf_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_1GbE_reset_export => OPEN,
+ reg_diag_data_buffer_1GbE_write_export => reg_diag_data_buf_1GbE_mosi.wr,
+ reg_diag_data_buffer_1GbE_writedata_export => reg_diag_data_buf_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_reg_diag_data_buffer_10GbE
+ reg_diag_data_buffer_10GbE_address_export => reg_diag_data_buf_10GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_10GbE_clk_export => OPEN,
+ reg_diag_data_buffer_10GbE_read_export => reg_diag_data_buf_10GbE_mosi.rd,
+ reg_diag_data_buffer_10GbE_readdata_export => reg_diag_data_buf_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_10GbE_reset_export => OPEN,
+ reg_diag_data_buffer_10GbE_write_export => reg_diag_data_buf_10GbE_mosi.wr,
+ reg_diag_data_buffer_10GbE_writedata_export => reg_diag_data_buf_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- ram_ss_ss_wide
- ram_ss_ss_wide_address_export => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w-1 DOWNTO 0),
- ram_ss_ss_wide_clk_export => OPEN,
- ram_ss_ss_wide_read_export => ram_ss_ss_transp_mosi.rd,
- ram_ss_ss_wide_readdata_export => ram_ss_ss_transp_miso.rddata(c_word_w-1 DOWNTO 0),
- ram_ss_ss_wide_reset_export => OPEN,
- ram_ss_ss_wide_write_export => ram_ss_ss_transp_mosi.wr,
- ram_ss_ss_wide_writedata_export => ram_ss_ss_transp_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_ss_ss_wide_address_export => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w-1 DOWNTO 0),
+ ram_ss_ss_wide_clk_export => OPEN,
+ ram_ss_ss_wide_read_export => ram_ss_ss_transp_mosi.rd,
+ ram_ss_ss_wide_readdata_export => ram_ss_ss_transp_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_ss_ss_wide_reset_export => OPEN,
+ ram_ss_ss_wide_write_export => ram_ss_ss_transp_mosi.wr,
+ ram_ss_ss_wide_writedata_export => ram_ss_ss_transp_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- reg_io_ddr
- reg_io_ddr_address_export => reg_io_ddr_mosi.address(1 DOWNTO 0),
- reg_io_ddr_clk_export => OPEN,
- reg_io_ddr_read_export => reg_io_ddr_mosi.rd,
- reg_io_ddr_readdata_export => reg_io_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_io_ddr_reset_export => OPEN,
- reg_io_ddr_write_export => reg_io_ddr_mosi.wr,
- reg_io_ddr_writedata_export => reg_io_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ reg_io_ddr_address_export => reg_io_ddr_mosi.address(1 DOWNTO 0),
+ reg_io_ddr_clk_export => OPEN,
+ reg_io_ddr_read_export => reg_io_ddr_mosi.rd,
+ reg_io_ddr_readdata_export => reg_io_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_io_ddr_reset_export => OPEN,
+ reg_io_ddr_write_export => reg_io_ddr_mosi.wr,
+ reg_io_ddr_writedata_export => reg_io_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
index 99f3a4ba822744f480fb8ca39054b05c4253030a..1ccb9bc75c78d57f0d987f6dde547c3d6d0b98c0 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
@@ -31,208 +31,247 @@ PACKAGE qsys_unb1_test_pkg IS
COMPONENT qsys_unb1_test is
PORT (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic;--_vector(0 downto 0); -- export
- coe_waitrequest_export_to_the_reg_tr_10GbE : in std_logic := 'X'; -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_tr_xaui : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic;--_vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_tr_xaui : out std_logic_vector(10 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_waitrequest_export_to_the_reg_tr_xaui : in std_logic := 'X'; -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_reset_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic;--_vector(0 downto 0); -- export
- coe_address_export_from_the_reg_tr_10GbE : out std_logic_vector(14 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic;--_vector(0 downto 0); -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_tr_xaui : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_tr_10GbE : out std_logic_vector(31 downto 0); -- export
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_clk_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic;--_vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_clk_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic;--_vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- coe_readdata_export_to_the_reg_tr_10GbE : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reset_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_remu : out std_logic; -- export
- reg_bsn_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_read_export : out std_logic; -- export
- reg_bsn_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_write_export : out std_logic; -- export
- reg_bsn_monitor_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_clk_export : out std_logic; -- export
- reg_bsn_monitor_reset_export : out std_logic; -- export
-
- reg_dp_offload_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_read_export : out std_logic; -- export
- reg_dp_offload_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_write_export : out std_logic; -- export
- reg_dp_offload_tx_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_offload_tx_clk_export : out std_logic; -- export
- reg_dp_offload_tx_reset_export : out std_logic; -- export
- reg_dp_offload_tx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_tx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
- reg_dp_offload_tx_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_hdr_dat_reset_export : out std_logic; -- export
-
- reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_1gbe_read_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_1gbe_write_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_offload_tx_1gbe_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic; -- export
-
- reg_dp_offload_rx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_rx_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_rx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_rx_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_rx_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
- reg_dp_offload_rx_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_rx_hdr_dat_reset_export : out std_logic; -- export
- reg_diag_data_buffer_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_read_export : out std_logic; -- export
- reg_diag_data_buffer_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_write_export : out std_logic; -- export
- reg_diag_data_buffer_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_clk_export : out std_logic; -- export
- reg_diag_data_buffer_reset_export : out std_logic; -- export
- ram_diag_data_buffer_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_read_export : out std_logic; -- export
- ram_diag_data_buffer_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_write_export : out std_logic; -- export
- ram_diag_data_buffer_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_clk_export : out std_logic; -- export
- ram_diag_data_buffer_reset_export : out std_logic; -- export
- reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_read_export : out std_logic; -- export
- reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_write_export : out std_logic; -- export
- reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_clk_export : out std_logic; -- export
- reg_diag_bg_reset_export : out std_logic; -- export
- ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_read_export : out std_logic; -- export
- ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_write_export : out std_logic; -- export
- ram_diag_bg_address_export : out std_logic_vector(12 downto 0); -- export
- ram_diag_bg_clk_export : out std_logic; -- export
- ram_diag_bg_reset_export : out std_logic; -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_address_export : out std_logic_vector(1 downto 0);
- reg_io_ddr_clk_export : out std_logic;
- reg_io_ddr_read_export : out std_logic;
- reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
- reg_io_ddr_reset_export : out std_logic;
- reg_io_ddr_write_export : out std_logic;
- reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0)
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
+ coe_waitrequest_export_to_the_reg_tr_10GbE : in std_logic := 'X'; -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_tr_xaui : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_tr_xaui : out std_logic_vector(10 downto 0); -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_waitrequest_export_to_the_reg_tr_xaui : in std_logic := 'X'; -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_reset_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_tr_10GbE : out std_logic_vector(14 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_tr_xaui : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_tr_10GbE : out std_logic_vector(31 downto 0); -- export
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_clk_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic; -- export
+ coe_write_export_from_the_reg_remu : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_clk_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
+ coe_readdata_export_to_the_reg_tr_10GbE : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reset_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_remu : out std_logic; -- export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_read_export : out std_logic; -- export
+ reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_write_export : out std_logic; -- export
+ reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_io_ddr_clk_export : out std_logic; -- export
+ reg_io_ddr_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_10gbe_read_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_10gbe_write_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_offload_tx_10gbe_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_offload_tx_1gbe_write_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_1gbe_read_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
);
end component qsys_unb1_test;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index 383e8572780282a610744f42bb41c621a7d522d9..0b726ee21dcb8546b014b6b845d0268acfbf3047 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -36,10 +36,11 @@ USE diag_lib.diag_pkg.ALL;
USE eth_lib.eth_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE reorder_lib.reorder_pkg.ALL;
+USE work.unb1_test_pkg.ALL;
ENTITY unb1_test IS
GENERIC (
- g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim : BOOLEAN := FALSE; -- Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_design_name : STRING := "unb1_test"; -- set by QSF
@@ -49,7 +50,7 @@ ENTITY unb1_test IS
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
g_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
- g_use_MB_I : NATURAL := 1; -- 1: use MB_I 0: do not use
+ g_use_MB_I : NATURAL := 0; -- 1: use MB_I 0: do not use
g_use_MB_II : NATURAL := 0
);
PORT (
@@ -133,96 +134,40 @@ ARCHITECTURE str OF unb1_test IS
sel_a_b(g_use_MB_II,1, 0),
0, 1);
- CONSTANT c_lpbk_data_w : NATURAL := 32; -- 128 c_eth_data_w, c_xgmii_data_w
-
-- Revision controlled constants
- CONSTANT c_use_lpbk : BOOLEAN := FALSE;--g_design_name = "unb1_test_lpbk";
- CONSTANT c_use_1GbE : BOOLEAN := TRUE;--g_design_name = "unb1_test_1GbE";
- CONSTANT c_use_10GbE : BOOLEAN := TRUE;--g_design_name = "unb1_test_10GbE";
- CONSTANT c_nof_streams_10GbE : NATURAL := 3;
- CONSTANT c_nof_streams_1GbE : NATURAL := 1;
- CONSTANT c_nof_streams_ddr : NATURAL := 1; --2
+ CONSTANT c_use_1GbE : BOOLEAN := g_design_name = "unb1_test_1GbE" OR g_design_name = "unb1_test_10GbE";
+ CONSTANT c_use_10GbE : BOOLEAN := g_design_name = "unb1_test_10GbE";
+ CONSTANT c_nof_streams_10GbE : NATURAL := sel_a_b(c_use_10GbE,3,0);
+ CONSTANT c_nof_streams_1GbE : NATURAL := sel_a_b(c_use_1GbE,1,0);
+ CONSTANT c_nof_streams_ddr : NATURAL := sel_a_b(g_use_MB_I,sel_a_b(g_use_MB_II,2,1),0);
CONSTANT c_nof_streams : NATURAL := c_nof_streams_1GbE + c_nof_streams_10GbE + c_nof_streams_ddr;
CONSTANT c_nof_streams_eth : NATURAL := c_nof_streams_1GbE + c_nof_streams_10GbE;
- CONSTANT c_data_w : NATURAL := c_xgmii_data_w;--sel_a_b(c_use_lpbk, c_lpbk_data_w, -- Select correct c_data_w when one interface is used
- --sel_a_b(c_use_1GbE, c_eth_data_w,
- --sel_a_b(c_use_10GbE, c_xgmii_data_w, 0)));
-
+ CONSTANT c_data_w_32 : NATURAL := c_eth_data_w; -- 1GbE
+ CONSTANT c_data_w_64 : NATURAL := c_xgmii_data_w; -- 10GbE
-- ddr
CONSTANT c_ddr_master : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
CONSTANT c_ddr_slave : t_c_tech_ddr := c_tech_ddr3_4g_800m_slave;
CONSTANT c_st_dat_w : NATURAL := 64; -- Any power of two 8..256
- -- Block generator
+ -- Block generator constants
CONSTANT c_bg_block_size : NATURAL := 900;
CONSTANT c_bg_gapsize : NATURAL := 100;
CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
- CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
-
-
- -- dp_offload_tx
- CONSTANT c_nof_hdr_fields : NATURAL := 4+12+4+9; -- Total header bits = 512
- CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
- ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
- ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
- ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
- ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
- ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
- ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
- ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
- ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
-
- CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111011111100"&"0001"&"101111111";
CONSTANT c_use_jumbo_frames : BOOLEAN := FALSE;
CONSTANT c_def_1GbE_block_size : NATURAL := 0; -- 0 first so we have time to set RX demux reg in dest. node
CONSTANT c_def_10GbE_block_size : NATURAL := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
CONSTANT c_max_frame_len : NATURAL := sel_a_b(c_use_jumbo_frames, 9018, 1518);
- CONSTANT c_max_frame_nof_words : NATURAL := (c_max_frame_len * c_byte_w ) / c_data_w;
- CONSTANT c_nof_header_words : NATURAL := field_slv_len(c_hdr_field_arr) / c_data_w;
CONSTANT c_nof_header_bytes : NATURAL := field_slv_len(c_hdr_field_arr) / c_byte_w;
- CONSTANT c_nof_crc_words : NATURAL := 1;
CONSTANT c_max_udp_payload_len : NATURAL := c_max_frame_len-c_nof_header_bytes-c_network_eth_crc_len;
- CONSTANT c_max_udp_payload_nof_words : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w;
- CONSTANT c_max_nof_words_per_block : NATURAL := c_bg_block_size;
- CONSTANT c_min_nof_words_per_block : NATURAL := 1;
- CONSTANT c_max_nof_blocks_per_packet : NATURAL := c_max_udp_payload_nof_words/c_min_nof_words_per_block;
- CONSTANT c_def_nof_blocks_per_packet : NATURAL := 1;
-
- CONSTANT c_nof_dp_offload_tx : NATURAL := 2; -- 1 set 1GbE + 1 set 10GbE
-
- SIGNAL hdr_fields_in_arr : t_slv_1024_arr(c_nof_streams_eth-1 DOWNTO 0);
- SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_streams_eth-1 DOWNTO 0);
+ CONSTANT c_max_udp_payload_nof_words_1GbE : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w_32;
+ CONSTANT c_max_udp_payload_nof_words_10GbE : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w_64;
+ CONSTANT c_min_nof_words_per_block : NATURAL := 1;
+ CONSTANT c_max_nof_blocks_per_packet_1GbE : NATURAL := c_max_udp_payload_nof_words_1GbE/c_min_nof_words_per_block;
+ CONSTANT c_max_nof_blocks_per_packet_10GbE : NATURAL := c_max_udp_payload_nof_words_10GbE/c_min_nof_words_per_block;
-- System
@@ -231,10 +176,11 @@ ARCHITECTURE str OF unb1_test IS
SIGNAL xo_rst : STD_LOGIC;
SIGNAL xo_rst_n : STD_LOGIC;
SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_locked : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC;
SIGNAL cal_rec_clk : STD_LOGIC;
-
+ SIGNAL epcs_clk : STD_LOGIC;
SIGNAL sa_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC;
@@ -262,12 +208,13 @@ ARCHITECTURE str OF unb1_test IS
SIGNAL reg_unb_sens_miso : t_mem_miso;
-- eth1g
+ SIGNAL eth1g_tse_clk : STD_LOGIC;
SIGNAL eth1g_mm_rst : STD_LOGIC;
SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
SIGNAL eth1g_tse_miso : t_mem_miso;
SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
SIGNAL eth1g_reg_miso : t_mem_miso;
- SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC;
SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
SIGNAL eth1g_ram_miso : t_mem_miso;
@@ -307,84 +254,89 @@ ARCHITECTURE str OF unb1_test IS
SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
SIGNAL reg_tr_xaui_miso : t_mem_miso;
- SIGNAL reg_dp_ram_from_mm_mosi : t_mem_mosi;
- SIGNAL reg_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
-
- SIGNAL ram_dp_ram_from_mm_mosi : t_mem_mosi;
- SIGNAL ram_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
-
- SIGNAL ram_dp_ram_to_mm_mosi : t_mem_mosi;
- SIGNAL ram_dp_ram_to_mm_miso : t_mem_miso;
-
-
- SIGNAL reg_diag_bg_mosi : t_mem_mosi;
- SIGNAL reg_diag_bg_miso : t_mem_miso;
- SIGNAL ram_diag_bg_mosi : t_mem_mosi;
- SIGNAL ram_diag_bg_miso : t_mem_miso;
-
- SIGNAL reg_dp_offload_tx_mosi_arr : t_mem_mosi_arr(c_nof_dp_offload_tx-1 DOWNTO 0);
- SIGNAL reg_dp_offload_tx_miso_arr : t_mem_miso_arr(c_nof_dp_offload_tx-1 DOWNTO 0);
- SIGNAL reg_dp_offload_tx_hdr_dat_mosi_arr : t_mem_mosi_arr(c_nof_dp_offload_tx-1 DOWNTO 0);
- SIGNAL reg_dp_offload_tx_hdr_dat_miso_arr : t_mem_miso_arr(c_nof_dp_offload_tx-1 DOWNTO 0);
-
- SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
- SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
-
- SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_miso : t_mem_miso;
- SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
- SIGNAL ram_diag_data_buf_miso : t_mem_miso;
- SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
- SIGNAL reg_diag_data_buf_miso : t_mem_miso;
-
- SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL block_gen_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
-
- SIGNAL fifo_block_gen_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL fifo_block_gen_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
-
- SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(c_nof_streams_eth-1 DOWNTO 0);
- SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(c_nof_streams_eth-1 DOWNTO 0);
-
- SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_streams_eth-1 DOWNTO 0);
- SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_streams_eth-1 DOWNTO 0);
-
- SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_streams_eth-1 DOWNTO 0);
- SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_streams_eth-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
-
- SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL reg_diag_bg_1GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_bg_1GbE_miso : t_mem_miso;
+ SIGNAL ram_diag_bg_1GbE_mosi : t_mem_mosi;
+ SIGNAL ram_diag_bg_1GbE_miso : t_mem_miso;
+
+ SIGNAL reg_diag_bg_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_bg_10GbE_miso : t_mem_miso;
+ SIGNAL ram_diag_bg_10GbE_mosi : t_mem_mosi;
+ SIGNAL ram_diag_bg_10GbE_miso : t_mem_miso;
+
+ SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
+ SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
+
+ SIGNAL reg_dp_offload_tx_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_10GbE_miso : t_mem_miso;
+ SIGNAL reg_dp_offload_tx_10GbE_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_10GbE_hdr_dat_miso : t_mem_miso;
+
+ SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
+ SIGNAL reg_dp_offload_rx_10GbE_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_rx_10GbE_hdr_dat_miso : t_mem_miso;
+
+ SIGNAL reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
+ SIGNAL reg_bsn_monitor_1GbE_miso : t_mem_miso;
+ SIGNAL reg_bsn_monitor_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_bsn_monitor_10GbE_miso : t_mem_miso;
+
+ SIGNAL ram_diag_data_buf_1GbE_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_1GbE_miso : t_mem_miso;
+ SIGNAL reg_diag_data_buf_1GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_1GbE_miso : t_mem_miso;
+
+ SIGNAL ram_diag_data_buf_10GbE_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_10GbE_miso : t_mem_miso;
+ SIGNAL reg_diag_data_buf_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_10GbE_miso : t_mem_miso;
+
+ SIGNAL block_gen_1GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL block_gen_10GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+
+ SIGNAL dp_offload_tx_1GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_1GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_10GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_10GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+
+ SIGNAL dp_offload_rx_1GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_1GbE_snk_out_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_10GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_10GbE_snk_out_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
-- Interface: 1GbE UDP streaming ports
- SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
-- DDR
- SIGNAL ddr_ctlr_mosi_arr : t_mem_ctlr_mosi_arr(0 TO g_nof_MB-1);
- SIGNAL ddr_ctlr_miso_arr : t_mem_ctlr_miso_arr(0 TO g_nof_MB-1);
+ SIGNAL ddr_ctlr_mosi_arr : t_mem_ctlr_mosi_arr(0 TO g_nof_MB-1);
+ SIGNAL ddr_ctlr_miso_arr : t_mem_ctlr_miso_arr(0 TO g_nof_MB-1);
- SIGNAL ddr_ctlr_clk : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
- SIGNAL ddr_ctlr_rst : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
+ SIGNAL ddr_ctlr_clk : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
+ SIGNAL ddr_ctlr_rst : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
- SIGNAL ram_ss_ss_transp_mosi : t_mem_mosi;
- SIGNAL ram_ss_ss_transp_miso : t_mem_miso;
- SIGNAL ram_ss_ss_transp_mosi2 : t_mem_mosi;
- SIGNAL ram_ss_ss_transp_miso2 : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_ss_ss_transp_mosi : t_mem_mosi;
+ SIGNAL ram_ss_ss_transp_miso : t_mem_miso;
+ SIGNAL ram_ss_ss_transp_mosi2 : t_mem_mosi;
+ SIGNAL ram_ss_ss_transp_miso2 : t_mem_miso := c_mem_miso_rst;
- SIGNAL to_mem_siso : t_dp_siso := c_dp_siso_rdy;
- SIGNAL to_mem_sosi : t_dp_sosi;
- SIGNAL from_mem_siso : t_dp_siso := c_dp_siso_rdy;
- SIGNAL from_mem_sosi : t_dp_sosi;
+ SIGNAL to_mem_siso : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL to_mem_sosi : t_dp_sosi;
+ SIGNAL from_mem_siso : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL from_mem_sosi : t_dp_sosi;
- SIGNAL to_mem_siso2 : t_dp_siso := c_dp_siso_rdy;
- SIGNAL to_mem_sosi2 : t_dp_sosi;
- SIGNAL from_mem_siso2 : t_dp_siso := c_dp_siso_rdy;
- SIGNAL from_mem_sosi2 : t_dp_sosi;
+ SIGNAL to_mem_siso2 : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL to_mem_sosi2 : t_dp_sosi;
+ SIGNAL from_mem_siso2 : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL from_mem_sosi2 : t_dp_sosi;
- SIGNAL reg_io_ddr_mosi : t_mem_mosi;
- SIGNAL reg_io_ddr_miso : t_mem_miso;
+ SIGNAL reg_io_ddr_mosi : t_mem_mosi;
+ SIGNAL reg_io_ddr_miso : t_mem_miso;
BEGIN
-----------------------------------------------------------------------------
@@ -405,7 +357,7 @@ BEGIN
g_udp_offload => c_use_1GbE,
g_udp_offload_nof_streams => c_nof_streams_1GbE,
g_dp_clk_use_pll => TRUE,
- g_mm_clk_use_pll => TRUE
+ g_xo_clk_use_pll => TRUE
)
PORT MAP (
-- Clock and reset signals
@@ -415,8 +367,15 @@ BEGIN
xo_rst_n => xo_rst_n,
mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
mm_rst => mm_rst,
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
dp_rst => dp_rst,
dp_clk => dp_clk,
dp_pps => OPEN,
@@ -468,6 +427,8 @@ BEGIN
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
@@ -517,9 +478,7 @@ BEGIN
g_nof_streams_1GbE => c_nof_streams_1GbE,
g_nof_streams_10GbE => c_nof_streams_10GbE,
g_nof_streams_ddr => c_nof_streams_ddr,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr,
- g_nof_dp_offload_tx => c_nof_dp_offload_tx
+ g_bg_block_size => c_bg_block_size
)
PORT MAP(
mm_rst => mm_rst,
@@ -574,27 +533,53 @@ BEGIN
reg_remu_mosi => reg_remu_mosi,
reg_remu_miso => reg_remu_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
-
- reg_dp_offload_tx_mosi_arr => reg_dp_offload_tx_mosi_arr,
- reg_dp_offload_tx_miso_arr => reg_dp_offload_tx_miso_arr,
- reg_dp_offload_tx_hdr_dat_mosi_arr => reg_dp_offload_tx_hdr_dat_mosi_arr,
- reg_dp_offload_tx_hdr_dat_miso_arr => reg_dp_offload_tx_hdr_dat_miso_arr,
-
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
+ -- block gen
+ ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
+
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+
+ -- dp_offload_tx
+ reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
+ reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
+ reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+
+ reg_dp_offload_tx_10GbE_mosi => reg_dp_offload_tx_10GbE_mosi,
+ reg_dp_offload_tx_10GbE_miso => reg_dp_offload_tx_10GbE_miso,
+ reg_dp_offload_tx_10GbE_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_10GbE_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
+
+ -- dp_offload_rx
+ reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+
+ reg_dp_offload_rx_10GbE_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_10GbE_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
+
+ -- bsn
+ reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
+
+ -- databuffer
+ ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
+
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+
+ -- tr_10GbE
reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
reg_tr_10GbE_miso => reg_tr_10GbE_miso,
reg_tr_xaui_mosi => reg_tr_xaui_mosi,
@@ -608,270 +593,122 @@ BEGIN
);
- -----------------------------------------------------------------------------
- -- TX: Block generator
- -----------------------------------------------------------------------------
- u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
- GENERIC MAP (
- g_nof_streams => c_nof_streams,
- g_buf_dat_w => c_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_name_prefix => "../../counter_data_" & NATURAL'IMAGE(c_data_w),
- g_diag_block_gen_rst => c_bg_ctrl
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso
- );
-
- gen_dp_fifo_sc : FOR i IN 0 TO c_nof_streams_eth-1 GENERATE
- u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
- GENERIC MAP (
- g_data_w => c_data_w,
- g_fifo_size => 50
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
- );
- END GENERATE;
-
- -----------------------------------------------------------------------------
- -- TX: dp_offload_tx
- -----------------------------------------------------------------------------
- u_dp_offload_tx_1GbE : ENTITY dp_lib.dp_offload_tx
+ u_bgdb_stream_test_1GbE : ENTITY work.bgdb_stream_test
GENERIC MAP (
+ g_sim => g_sim,
g_nof_streams => c_nof_streams_1GbE,
- g_data_w => c_eth_data_w,
- g_use_complex => FALSE,
- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_def_nof_words_per_block => c_def_1GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet,
- g_def_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_mosi => reg_dp_offload_tx_mosi_arr(0),
- reg_miso => reg_dp_offload_tx_miso_arr(0),
-
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi_arr(0),
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso_arr(0),
-
- snk_in_arr => fifo_block_gen_src_out_arr(c_nof_streams_1GbE-1 DOWNTO 0),
- snk_out_arr => fifo_block_gen_src_in_arr(c_nof_streams_1GbE-1 DOWNTO 0),
-
- src_out_arr => dp_offload_tx_src_out_arr(c_nof_streams_1GbE-1 DOWNTO 0),
- src_in_arr => dp_offload_tx_src_in_arr(c_nof_streams_1GbE-1 DOWNTO 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(c_nof_streams_1GbE-1 DOWNTO 0)
- );
-
- u_dp_offload_tx_10GbE : ENTITY dp_lib.dp_offload_tx
- GENERIC MAP (
- g_nof_streams => c_nof_streams_10GbE,
- g_data_w => c_data_w,
- g_use_complex => FALSE,
- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_def_nof_words_per_block => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet,
- g_def_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_mosi => reg_dp_offload_tx_mosi_arr(1),
- reg_miso => reg_dp_offload_tx_miso_arr(1),
-
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi_arr(1),
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso_arr(1),
-
- snk_in_arr => fifo_block_gen_src_out_arr(c_nof_streams_eth-1 DOWNTO c_nof_streams_1GbE),
- snk_out_arr => fifo_block_gen_src_in_arr(c_nof_streams_eth-1 DOWNTO c_nof_streams_1GbE),
-
- src_out_arr => dp_offload_tx_src_out_arr(c_nof_streams_eth-1 DOWNTO c_nof_streams_1GbE),
- src_in_arr => dp_offload_tx_src_in_arr(c_nof_streams_eth-1 DOWNTO c_nof_streams_1GbE),
-
- hdr_fields_in_arr => hdr_fields_in_arr(c_nof_streams_eth-1 DOWNTO c_nof_streams_1GbE)
- );
-
-
-
- -- c_nof_streams_1GbE:
- -- dst = src
- gen_hdr_in_fields_1GbE : FOR i IN 0 TO c_nof_streams_1GbE-1 GENERATE
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_dst_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_dst_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
-
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr")) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_dst_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_dst_addr")) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
-
- -- dst port goes through 4000
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_src_port") DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= TO_UVEC(4000, 16);
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port") DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= TO_UVEC(4000, 16);
-
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_sync" ) DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )) <= slv(block_gen_src_out_arr(i).sync);
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )) <= block_gen_src_out_arr(i).bsn(59 DOWNTO 0);
- END GENERATE;
-
- -- c_nof_streams_10GbE:
- gen_hdr_in_fields_10GbE : FOR i IN 0 TO c_nof_streams_10GbE-1 GENERATE
- -- dst = src
- hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
- hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "eth_dst_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_dst_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
-
- hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr")) <= x"0A0A" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
- hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "ip_dst_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_dst_addr")) <= x"0A0A" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
-
- -- dst port goes through 4000,4001,4002
- hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "udp_src_port") DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= TO_UVEC(4000+i, 16);
- hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "udp_dst_port") DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= TO_UVEC(4000+i, 16);
-
- hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "usr_sync" ) DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )) <= slv(block_gen_src_out_arr(i+c_nof_streams_1GbE).sync);
- hdr_fields_in_arr(i+c_nof_streams_1GbE)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )) <= block_gen_src_out_arr(i+c_nof_streams_1GbE).bsn(59 DOWNTO 0);
- END GENERATE;
-
------------------------------------------------------------------------------
- -- RX: dp_offload_rx
- -----------------------------------------------------------------------------
- u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
- GENERIC MAP (
- g_nof_streams => c_nof_streams_eth,
- g_data_w => c_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => NOT(c_use_lpbk),
- g_crc_nof_words => c_nof_crc_words
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
-
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
-
- hdr_fields_out_arr => hdr_fields_out_arr
- );
-
- gen_hdr_out_fields : FOR i IN 0 TO c_nof_streams_eth-1 GENERATE
- diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )));
- diag_data_buf_snk_in_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )), c_dp_stream_bsn_w);
- END GENERATE;
-
- -----------------------------------------------------------------------------
- -- RX: Data buffers and BSN monitors
- -----------------------------------------------------------------------------
- dp_offload_rx_src_in_arr <= diag_data_buf_snk_out_arr(c_nof_streams_eth-1 downto 0);
-
- gen_bsn_mon_in : FOR i IN 0 TO c_nof_streams_eth-1 GENERATE
- diag_data_buf_snk_in_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
- diag_data_buf_snk_in_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
- diag_data_buf_snk_in_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
- diag_data_buf_snk_in_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
- diag_data_buf_snk_in_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
- END GENERATE;
-
- u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
- GENERIC MAP (
- g_nof_streams => c_nof_streams_eth,
- g_cross_clock_domain => TRUE,
- g_sync_timeout => c_bg_blocks_per_sync*(c_bg_block_size+c_bg_gapsize),
- g_cnt_sop_w => ceil_log2(c_bg_blocks_per_sync+1),
- g_cnt_valid_w => ceil_log2(c_bg_blocks_per_sync*c_bg_block_size+1),
- g_log_first_bsn => TRUE
+ g_data_w => c_data_w_32,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_1GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => TRUE
)
PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => diag_data_buf_snk_out_arr(c_nof_streams_eth-1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(c_nof_streams_eth-1 downto 0)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
+
+ -- dp_offload_tx
+ reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
+ reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+
+ -- dp_offload_rx
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso
);
- diag_data_buf_snk_out_arr <= (OTHERS=>c_dp_siso_rdy);
- u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
+ u_bgdb_stream_test_10GbE : ENTITY work.bgdb_stream_test
GENERIC MAP (
- g_nof_streams => c_nof_streams,
- g_data_w => 32, --c_data_w,
- g_buf_nof_data => 1024,
- g_buf_use_sync => FALSE -- sync by reading last address of data buffer
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams_10GbE,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => FALSE
)
PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
-
- --in_sync => diag_data_buf_snk_in_arr(0).sop,
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen mm
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+
+ -- dp_offload_tx
+ reg_dp_offload_tx_mosi => reg_dp_offload_tx_10GbE_mosi,
+ reg_dp_offload_tx_miso => reg_dp_offload_tx_10GbE_miso,
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ -- dp_offload_rx
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso
);
- -----------------------------------------------------------------------------
- -- Interface : Loopback
- -----------------------------------------------------------------------------
- gen_loopback : IF c_use_lpbk=TRUE GENERATE
- dp_offload_rx_snk_in_arr <= dp_offload_tx_src_out_arr;
- dp_offload_tx_src_in_arr <= (OTHERS=>c_dp_siso_rdy);
- END GENERATE;
-----------------------------------------------------------------------------
-- Interface : 1GbE
-----------------------------------------------------------------------------
gen_wires_1GbE : IF c_use_1GbE=TRUE GENERATE
- eth1g_udp_tx_sosi_arr(0) <= dp_offload_tx_src_out_arr(0);
- dp_offload_tx_src_in_arr(0) <= eth1g_udp_tx_siso_arr(0);
+ eth1g_udp_tx_sosi_arr(0) <= dp_offload_tx_1GbE_src_out_arr(0);
+ dp_offload_tx_1GbE_src_in_arr(0) <= eth1g_udp_tx_siso_arr(0);
- dp_offload_rx_snk_in_arr(0) <= eth1g_udp_rx_sosi_arr(0);
- eth1g_udp_rx_siso_arr(0) <= dp_offload_rx_snk_out_arr(0);
+ dp_offload_rx_1GbE_snk_in_arr(0) <= eth1g_udp_rx_sosi_arr(0);
+ eth1g_udp_rx_siso_arr(0) <= dp_offload_rx_1GbE_snk_out_arr(0);
END GENERATE;
-----------------------------------------------------------------------------
@@ -919,11 +756,11 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
- src_out_arr => dp_offload_rx_snk_in_arr(c_nof_streams_eth-1 downto c_nof_streams_1GbE),
- src_in_arr => dp_offload_rx_snk_out_arr(c_nof_streams_eth-1 downto c_nof_streams_1GbE),
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr,
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr,
- snk_out_arr => dp_offload_tx_src_in_arr(c_nof_streams_eth-1 downto c_nof_streams_1GbE),
- snk_in_arr => dp_offload_tx_src_out_arr(c_nof_streams_eth-1 downto c_nof_streams_1GbE),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
-- Serial XAUI IO
xaui_tx_arr => i_xaui_tx_arr,
@@ -972,97 +809,97 @@ BEGIN
END GENERATE;
- u_reorder: ENTITY reorder_lib.reorder_transpose
- GENERIC MAP (
- g_nof_streams => c_nof_streams_ddr,
- g_in_dat_w => c_data_w,
- g_ena_pre_transp => FALSE,
- g_use_complex => FALSE,
- g_reorder_seq => c_reorder_seq_same
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
- -- ST sinks from BG
- snk_out_arr => block_gen_src_in_arr(c_nof_streams-1 downto c_nof_streams_eth), -- -2
- snk_in_arr => block_gen_src_out_arr(c_nof_streams-1 downto c_nof_streams_eth), -- -2
- -- ST source to DB
- src_in_arr => (OTHERS=> c_dp_siso_rdy),
- src_out_arr => diag_data_buf_snk_in_arr(c_nof_streams-1 downto c_nof_streams_eth), -- -2
- -- Memory Mapped
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
- -- Control interface to the external memory
- dvr_mosi => ddr_ctlr_mosi_arr(0),
- dvr_miso => ddr_ctlr_miso_arr(0),
- -- Data interface to the external memory
- to_mem_src_out => to_mem_sosi,
- to_mem_src_in => to_mem_siso,
- from_mem_snk_in => from_mem_sosi,
- from_mem_snk_out => from_mem_siso
- );
-
- ------------------------------------------------------------------------------
- -- DDR3 MODULE 0,1
- ------------------------------------------------------------------------------
- no_MB_I : IF g_use_MB_I = 0 GENERATE
- --reg_ddr3_miso_arr(0) <= c_mem_miso_rst;
- --reg_diagnostics_miso_arr(0) <= c_mem_miso_rst;
- END GENERATE;
-
- gen_MB_I : IF g_use_MB_I = 1 GENERATE
- u_mms_ddr3_i: ENTITY io_ddr_lib.io_ddr
- GENERIC MAP (
- g_technology => g_technology,
- g_tech_ddr => c_ddr_master,
- g_wr_data_w => c_st_dat_w,
- g_rd_data_w => c_st_dat_w
- )
- PORT MAP (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- ctlr_ref_clk => dp_clk,
- ctlr_ref_rst => dp_rst,
-
- ctlr_clk_out => ddr_ctlr_clk(0),
- ctlr_clk_in => ddr_ctlr_clk(0),
-
- ctlr_rst_out => ddr_ctlr_rst(0),
- ctlr_rst_in => ddr_ctlr_rst(0),
-
- dvr_clk => dp_clk,
- dvr_rst => dp_rst,
-
- dvr_mosi => ddr_ctlr_mosi_arr(0),
- dvr_miso => ddr_ctlr_miso_arr(0),
-
- wr_clk => dp_clk,
- wr_rst => dp_rst,
-
- wr_sosi => to_mem_sosi,
- wr_siso => to_mem_siso,
-
- rd_clk => dp_clk,
- rd_rst => dp_rst,
-
- rd_sosi => from_mem_sosi,
- rd_siso => from_mem_siso,
-
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
- phy3_in => MB_I_IN,
- phy3_io => MB_I_IO,
- phy3_ou => MB_I_OU
- );
- END GENERATE;
-
+-- u_reorder: ENTITY reorder_lib.reorder_transpose
+-- GENERIC MAP (
+-- g_nof_streams => c_nof_streams_ddr,
+-- g_in_dat_w => c_data_w_32,
+-- g_ena_pre_transp => FALSE,
+-- g_use_complex => FALSE,
+-- g_reorder_seq => c_reorder_seq_same
+-- )
+-- PORT MAP (
+-- mm_rst => mm_rst,
+-- mm_clk => mm_clk,
+-- dp_clk => dp_clk,
+-- dp_rst => dp_rst,
+-- -- ST sinks from BG
+-- snk_out_arr => block_gen_src_in_arr(c_nof_streams-1 downto c_nof_streams_eth), -- -2
+-- snk_in_arr => block_gen_src_out_arr(c_nof_streams-1 downto c_nof_streams_eth), -- -2
+-- -- ST source to DB
+-- src_in_arr => (OTHERS=> c_dp_siso_rdy),
+-- src_out_arr => diag_data_buf_snk_in_arr(c_nof_streams-1 downto c_nof_streams_eth), -- -2
+-- -- Memory Mapped
+-- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+-- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+-- -- Control interface to the external memory
+-- dvr_mosi => ddr_ctlr_mosi_arr(0),
+-- dvr_miso => ddr_ctlr_miso_arr(0),
+-- -- Data interface to the external memory
+-- to_mem_src_out => to_mem_sosi,
+-- to_mem_src_in => to_mem_siso,
+-- from_mem_snk_in => from_mem_sosi,
+-- from_mem_snk_out => from_mem_siso
+-- );
+--
+-- ------------------------------------------------------------------------------
+-- -- DDR3 MODULE 0,1
+-- ------------------------------------------------------------------------------
+-- no_MB_I : IF g_use_MB_I = 0 GENERATE
+-- --reg_ddr3_miso_arr(0) <= c_mem_miso_rst;
+-- --reg_diagnostics_miso_arr(0) <= c_mem_miso_rst;
+-- END GENERATE;
+--
+-- gen_MB_I : IF g_use_MB_I = 1 GENERATE
+-- u_mms_ddr3_i: ENTITY io_ddr_lib.io_ddr
+-- GENERIC MAP (
+-- g_technology => g_technology,
+-- g_tech_ddr => c_ddr_master,
+-- g_wr_data_w => c_st_dat_w,
+-- g_rd_data_w => c_st_dat_w
+-- )
+-- PORT MAP (
+-- mm_clk => mm_clk,
+-- mm_rst => mm_rst,
+--
+-- reg_io_ddr_mosi => reg_io_ddr_mosi,
+-- reg_io_ddr_miso => reg_io_ddr_miso,
+--
+-- ctlr_ref_clk => dp_clk,
+-- ctlr_ref_rst => dp_rst,
+--
+-- ctlr_clk_out => ddr_ctlr_clk(0),
+-- ctlr_clk_in => ddr_ctlr_clk(0),
+--
+-- ctlr_rst_out => ddr_ctlr_rst(0),
+-- ctlr_rst_in => ddr_ctlr_rst(0),
+--
+-- dvr_clk => dp_clk,
+-- dvr_rst => dp_rst,
+--
+-- dvr_mosi => ddr_ctlr_mosi_arr(0),
+-- dvr_miso => ddr_ctlr_miso_arr(0),
+--
+-- wr_clk => dp_clk,
+-- wr_rst => dp_rst,
+--
+-- wr_sosi => to_mem_sosi,
+-- wr_siso => to_mem_siso,
+--
+-- rd_clk => dp_clk,
+-- rd_rst => dp_rst,
+--
+-- rd_sosi => from_mem_sosi,
+-- rd_siso => from_mem_siso,
+--
+-- term_ctrl_out => OPEN,
+-- term_ctrl_in => OPEN,
+--
+-- phy3_in => MB_I_IN,
+-- phy3_io => MB_I_IO,
+-- phy3_ou => MB_I_OU
+-- );
+-- END GENERATE;
+--
-----------------------------------------------------------------------------
-- Node function
-----------------------------------------------------------------------------
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..56a21ccbe4b9f24b7479bd80bbc720df060ae499
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
@@ -0,0 +1,63 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+
+PACKAGE unb1_test_pkg IS
+
+ -- dp_offload_tx
+ CONSTANT c_nof_hdr_fields : NATURAL := 4+12+4+9; -- Total header bits = 512
+ CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
+ ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
+
+END unb1_test_pkg;
+
diff --git a/boards/uniboard1/designs/unb1_test/tb/python/tc_unb1_test.py b/boards/uniboard1/designs/unb1_test/tb/python/tc_unb1_test.py
index 4bde6f8ba601a6e6b8f4aa6ca6cdf0db6a017362..ad313e0d7bb8109985a9c74529069b4bd90f7e8b 100644
--- a/boards/uniboard1/designs/unb1_test/tb/python/tc_unb1_test.py
+++ b/boards/uniboard1/designs/unb1_test/tb/python/tc_unb1_test.py
@@ -96,7 +96,7 @@ def test_BG_to_DB(tc,io,cmd):
tc.set_section_id('Read - ')
nof_streams=5
blocksize=0
- Bg = pi_diag_block_gen.PiDiagBlockGen(tc,io,nofChannels=nof_streams,ramSizePerChannel=blocksize)
+ Bg = pi_diag_block_gen.PiDiagBlockGen(tc,io,nofChannels=nof_streams,ramSizePerChannel=blocksize,instanceName='10GBE')
Bg.write_disable()
settings = Bg.read_block_gen_settings()
@@ -104,9 +104,9 @@ def test_BG_to_DB(tc,io,cmd):
gapsize = settings[0][3]
blocksize = pow(2, ceil_log2(samples_per_packet+gapsize))
- Bg = pi_diag_block_gen.PiDiagBlockGen(tc,io,nofChannels=nof_streams, ramSizePerChannel=blocksize)
+ Bg = pi_diag_block_gen.PiDiagBlockGen(tc,io,nofChannels=nof_streams, ramSizePerChannel=blocksize,instanceName='10GBE')
#Bg.write_block_gen_settings(samplesPerPacket=700, blocksPerSync=781250, gapSize=300, memLowAddr=0, memHighAddr=701, BSNInit=42)
- Db = pi_diag_data_buffer.PiDiagDataBuffer(tc,io,nofStreams=nof_streams,ramSizePerStream=blocksize)
+ Db = pi_diag_data_buffer.PiDiagDataBuffer(tc,io,nofStreams=nof_streams,ramSizePerStream=blocksize,instanceName='10GBE')
resetptrn = [0xc1ea1ed1]*blocksize #samples_per_packet + [0]*(blocksize-samples_per_packet)
for s in tc.gpNumbers:
Db.overwrite_data_buffer(resetptrn,streamNr=s,vLevel=9)