diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
index 9facafa00919f715c56a5b207d1b1cd2073d77f5..3c27ce464b71aa6706fd57f98d98d7a74d415cea 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
@@ -36,97 +36,97 @@ number_of_columns = 13
   -                                         -     -     -      stamp_commit                              0x00000011       3     RO       uint32     b[31:0]           -  -      -    
   -                                         -     -     -      design_note                               0x00000014      52     RO        char8     b[31:0]      b[7:0]  -      -    
   REG_WDI                                   1     1     REG    wdi_override                              0x00000c00       1     WO       uint32     b[31:0]           -  -      -    
-  REG_FPGA_TEMP_SENS                        1     1     REG    temp                                      0x0003d1f8       1     RO       uint32     b[31:0]           -  -      -    
-  REG_FPGA_VOLTAGE_SENS                     1     1     REG    voltages                                  0x0003d1d0       6     RO       uint32     b[31:0]           -  -      -    
+  REG_FPGA_TEMP_SENS                        1     1     REG    temp                                      0x00043210       1     RO       uint32     b[31:0]           -  -      -    
+  REG_FPGA_VOLTAGE_SENS                     1     1     REG    voltages                                  0x000431e0       6     RO       uint32     b[31:0]           -  -      -    
   RAM_SCRAP                                 1     1     RAM    data                                      0x00000200     512     RW       uint32     b[31:0]           -  -      -    
   AVS_ETH_0_TSE                             1     1     REG    status                                    0x00000400    1024     RO       uint32     b[31:0]           -  -      -    
   AVS_ETH_0_REG                             1     1     REG    status                                    0x00000c10      12     RO       uint32     b[31:0]           -  -      -    
   AVS_ETH_0_RAM                             1     1     RAM    data                                      0x00000800    1024     RW       uint32     b[31:0]           -  -      -    
-  PIO_PPS                                   1     1     REG    capture_cnt                               0x0003d224       1     RO       uint32     b[29:0]           -  -      -    
-  -                                         -     -     -      stable                                    0x0003d224       1     RO       uint32    b[30:30]           -  -      -    
-  -                                         -     -     -      toggle                                    0x0003d224       1     RO       uint32    b[31:31]           -  -      -    
-  -                                         -     -     -      expected_cnt                              0x0003d225       1     RW       uint32     b[27:0]           -  -      -    
-  -                                         -     -     -      edge                                      0x0003d225       1     RW       uint32    b[31:31]           -  -      -    
-  -                                         -     -     -      offset_cnt                                0x0003d226       1     RO       uint32     b[27:0]           -  -      -    
-  REG_EPCS                                  1     1     REG    addr                                      0x0003d200       1     WO       uint32     b[23:0]           -  -      -    
-  -                                         -     -     -      rden                                      0x0003d201       1     WO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      read_bit                                  0x0003d202       1     WO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      write_bit                                 0x0003d203       1     WO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      sector_erase                              0x0003d204       1     WO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      busy                                      0x0003d205       1     RO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      unprotect                                 0x0003d206       1     WO       uint32     b[31:0]           -  -      -    
-  REG_DPMM_CTRL                             1     1     REG    rd_usedw                                  0x0003d240       1     RO       uint32     b[31:0]           -  -      -    
-  REG_DPMM_DATA                             1     1     FIFO   data                                      0x0003d23e       1     RO       uint32     b[31:0]           -  -      -    
-  REG_MMDP_CTRL                             1     1     REG    wr_usedw                                  0x0003d23c       1     RO       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      wr_availw                                 0x0003d23d       1     RO       uint32     b[31:0]           -  -      -    
-  REG_MMDP_DATA                             1     1     FIFO   data                                      0x0003d23a       1     WO       uint32     b[31:0]           -  -      -    
-  REG_REMU                                  1     1     REG    reconfigure                               0x0003d208       1     WO       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      param                                     0x0003d209       1     WO       uint32      b[2:0]           -  -      -    
-  -                                         -     -     -      read_param                                0x0003d20a       1     WO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      write_param                               0x0003d20b       1     WO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      data_out                                  0x0003d20c       1     RO       uint32     b[23:0]           -  -      -    
-  -                                         -     -     -      data_in                                   0x0003d20d       1     WO       uint32     b[23:0]           -  -      -    
-  -                                         -     -     -      busy                                      0x0003d20e       1     RO       uint32      b[0:0]           -  -      -    
-  REG_SDP_INFO                              1     1     REG    block_period                              0x0003d1c0       1     RO       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      beam_repositioning_flag                   0x0003d1c1       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      fsub_type                                 0x0003d1c2       1     RO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      f_adc                                     0x0003d1c3       1     RO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      nyquist_zone_index                        0x0003d1c4       1     RW       uint32      b[1:0]           -  -      -    
-  -                                         -     -     -      observation_id                            0x0003d1c5       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      antenna_band_index                        0x0003d1c6       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      station_id                                0x0003d1c7       1     RW       uint32     b[15:0]           -  -      -    
-  REG_RING_INFO                             1     1     REG    use_cable_to_previous_rn                  0x0003d210       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      use_cable_to_next_rn                      0x0003d211       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      n_rn                                      0x0003d212       1     RW       uint32      b[7:0]           -  -      -    
-  -                                         -     -     -      o_rn                                      0x0003d213       1     RW       uint32      b[7:0]           -  -      -    
-  PIO_JESD_CTRL                             1     1     REG    enable                                    0x0003d230       1     RW       uint32     b[30:0]           -  -      -    
-  -                                         -     -     -      reset                                     0x0003d230       1     RW       uint32    b[31:31]           -  -      -    
-  JESD204B                                  1     12    REG    rx_lane_ctrl_common                       0x0003c000       1     RW       uint32      b[2:0]           -  -      256  
-  -                                         -     -     -      rx_lane_ctrl_0                            0x0003c001       1     RW       uint32      b[2:0]           -  -      -    
-  -                                         -     -     -      rx_lane_ctrl_1                            0x0003c002       1     RW       uint32      b[2:0]           -  -      -    
-  -                                         -     -     -      rx_lane_ctrl_2                            0x0003c003       1     RW       uint32      b[2:0]           -  -      -    
-  -                                         -     -     -      rx_lane_ctrl_3                            0x0003c004       1     RW       uint32      b[2:0]           -  -      -    
-  -                                         -     -     -      rx_lane_ctrl_4                            0x0003c005       1     RW       uint32      b[2:0]           -  -      -    
-  -                                         -     -     -      rx_lane_ctrl_5                            0x0003c006       1     RW       uint32      b[2:0]           -  -      -    
-  -                                         -     -     -      rx_lane_ctrl_6                            0x0003c007       1     RW       uint32      b[2:0]           -  -      -    
-  -                                         -     -     -      rx_lane_ctrl_7                            0x0003c008       1     RW       uint32      b[2:0]           -  -      -    
-  -                                         -     -     -      rx_dll_ctrl                               0x0003c014       1     RW       uint32     b[16:0]           -  -      -    
-  -                                         -     -     -      rx_syncn_sysref_ctrl                      0x0003c015       1     RW       uint32     b[24:0]           -  -      -    
-  -                                         -     -     -      rx_csr_sysref_always_on                   0x0003c015       1     RW       uint32      b[1:1]           -  -      -    
-  -                                         -     -     -      rx_csr_rbd_offset                         0x0003c015       1     RW       uint32     b[10:3]           -  -      -    
-  -                                         -     -     -      rx_csr_lmfc_offset                        0x0003c015       1     RW       uint32    b[19:12]           -  -      -    
-  -                                         -     -     -      rx_err0                                   0x0003c018       1     RW       uint32      b[8:0]           -  -      -    
-  -                                         -     -     -      rx_err1                                   0x0003c019       1     RW       uint32      b[9:0]           -  -      -    
-  -                                         -     -     -      csr_dev_syncn                             0x0003c020       1     RO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      csr_rbd_count                             0x0003c020       1     RO       uint32     b[10:3]           -  -      -    
-  -                                         -     -     -      rx_status1                                0x0003c021       1     RW       uint32     b[23:0]           -  -      -    
-  -                                         -     -     -      rx_status2                                0x0003c022       1     RW       uint32     b[23:0]           -  -      -    
-  -                                         -     -     -      rx_status3                                0x0003c023       1     RW       uint32      b[7:0]           -  -      -    
-  -                                         -     -     -      rx_ilas_csr_l                             0x0003c025       1     RW       uint32      b[4:0]           -  -      -    
-  -                                         -     -     -      rx_ilas_csr_f                             0x0003c025       1     RW       uint32     b[15:8]           -  -      -    
-  -                                         -     -     -      rx_ilas_csr_k                             0x0003c025       1     RW       uint32    b[20:16]           -  -      -    
-  -                                         -     -     -      rx_ilas_csr_m                             0x0003c025       1     RW       uint32    b[31:24]           -  -      -    
-  -                                         -     -     -      rx_ilas_csr_n                             0x0003c026       1     RW       uint32      b[4:0]           -  -      -    
-  -                                         -     -     -      rx_ilas_csr_cs                            0x0003c026       1     RW       uint32      b[7:6]           -  -      -    
-  -                                         -     -     -      rx_ilas_csr_np                            0x0003c026       1     RW       uint32     b[12:8]           -  -      -    
-  -                                         -     -     -      rx_ilas_csr_subclassv                     0x0003c026       1     RW       uint32    b[15:13]           -  -      -    
-  -                                         -     -     -      rx_ilas_csr_s                             0x0003c026       1     RW       uint32    b[20:16]           -  -      -    
-  -                                         -     -     -      rx_ilas_csr_jesdv                         0x0003c026       1     RW       uint32    b[23:21]           -  -      -    
-  -                                         -     -     -      rx_ilas_csr_cf                            0x0003c026       1     RW       uint32    b[28:24]           -  -      -    
-  -                                         -     -     -      rx_ilas_csr_hd                            0x0003c026       1     RW       uint32    b[31:31]           -  -      -    
-  -                                         -     -     -      rx_status4                                0x0003c03c       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_status5                                0x0003c03d       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_status6                                0x0003c03e       1     RW       uint32     b[23:0]           -  -      -    
-  -                                         -     -     -      rx_status7                                0x0003c03f       1     RO       uint32     b[31:0]           -  -      -    
-  REG_DP_SHIFTRAM                           1     12    REG    shift                                     0x00000c20       1     RW       uint32     b[11:0]           -  -      2    
-  REG_BSN_SOURCE_V2                         1     1     REG    dp_on                                     0x0003d1f0       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      dp_on_pps                                 0x0003d1f0       1     RW       uint32      b[1:1]           -  -      -    
-  -                                         -     -     -      nof_clk_per_sync                          0x0003d1f1       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      bsn_init                                  0x0003d1f2       1     RW       uint64     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      -                                         0x0003d1f3       -      -            -     b[31:0]    b[63:32]  -      -    
-  -                                         -     -     -      bsn_time_offset                           0x0003d1f4       1     RW       uint32      b[9:0]           -  -      -    
-  REG_BSN_SCHEDULER                         1     1     REG    scheduled_bsn                             0x0003d236       1     RW       uint64     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      -                                         0x0003d237       -      -            -     b[31:0]    b[63:32]  -      -    
+  PIO_PPS                                   1     1     REG    capture_cnt                               0x0004323c       1     RO       uint32     b[29:0]           -  -      -    
+  -                                         -     -     -      stable                                    0x0004323c       1     RO       uint32    b[30:30]           -  -      -    
+  -                                         -     -     -      toggle                                    0x0004323c       1     RO       uint32    b[31:31]           -  -      -    
+  -                                         -     -     -      expected_cnt                              0x0004323d       1     RW       uint32     b[27:0]           -  -      -    
+  -                                         -     -     -      edge                                      0x0004323d       1     RW       uint32    b[31:31]           -  -      -    
+  -                                         -     -     -      offset_cnt                                0x0004323e       1     RO       uint32     b[27:0]           -  -      -    
+  REG_EPCS                                  1     1     REG    addr                                      0x00043218       1     WO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      rden                                      0x00043219       1     WO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      read_bit                                  0x0004321a       1     WO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      write_bit                                 0x0004321b       1     WO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      sector_erase                              0x0004321c       1     WO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      busy                                      0x0004321d       1     RO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      unprotect                                 0x0004321e       1     WO       uint32     b[31:0]           -  -      -    
+  REG_DPMM_CTRL                             1     1     REG    rd_usedw                                  0x00043256       1     RO       uint32     b[31:0]           -  -      -    
+  REG_DPMM_DATA                             1     1     FIFO   data                                      0x00043254       1     RO       uint32     b[31:0]           -  -      -    
+  REG_MMDP_CTRL                             1     1     REG    wr_usedw                                  0x00043252       1     RO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      wr_availw                                 0x00043253       1     RO       uint32     b[31:0]           -  -      -    
+  REG_MMDP_DATA                             1     1     FIFO   data                                      0x00043250       1     WO       uint32     b[31:0]           -  -      -    
+  REG_REMU                                  1     1     REG    reconfigure                               0x00043220       1     WO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      param                                     0x00043221       1     WO       uint32      b[2:0]           -  -      -    
+  -                                         -     -     -      read_param                                0x00043222       1     WO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      write_param                               0x00043223       1     WO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      data_out                                  0x00043224       1     RO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      data_in                                   0x00043225       1     WO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      busy                                      0x00043226       1     RO       uint32      b[0:0]           -  -      -    
+  REG_SDP_INFO                              1     1     REG    block_period                              0x000431d0       1     RO       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      beam_repositioning_flag                   0x000431d1       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      fsub_type                                 0x000431d2       1     RO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      f_adc                                     0x000431d3       1     RO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      nyquist_zone_index                        0x000431d4       1     RW       uint32      b[1:0]           -  -      -    
+  -                                         -     -     -      observation_id                            0x000431d5       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      antenna_band_index                        0x000431d6       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      station_id                                0x000431d7       1     RW       uint32     b[15:0]           -  -      -    
+  REG_RING_INFO                             1     1     REG    use_cable_to_previous_rn                  0x00043228       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      use_cable_to_next_rn                      0x00043229       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      n_rn                                      0x0004322a       1     RW       uint32      b[7:0]           -  -      -    
+  -                                         -     -     -      o_rn                                      0x0004322b       1     RW       uint32      b[7:0]           -  -      -    
+  PIO_JESD_CTRL                             1     1     REG    enable                                    0x00043246       1     RW       uint32     b[30:0]           -  -      -    
+  -                                         -     -     -      reset                                     0x00043246       1     RW       uint32    b[31:31]           -  -      -    
+  JESD204B                                  1     12    REG    rx_lane_ctrl_common                       0x00042000       1     RW       uint32      b[2:0]           -  -      256  
+  -                                         -     -     -      rx_lane_ctrl_0                            0x00042001       1     RW       uint32      b[2:0]           -  -      -    
+  -                                         -     -     -      rx_lane_ctrl_1                            0x00042002       1     RW       uint32      b[2:0]           -  -      -    
+  -                                         -     -     -      rx_lane_ctrl_2                            0x00042003       1     RW       uint32      b[2:0]           -  -      -    
+  -                                         -     -     -      rx_lane_ctrl_3                            0x00042004       1     RW       uint32      b[2:0]           -  -      -    
+  -                                         -     -     -      rx_lane_ctrl_4                            0x00042005       1     RW       uint32      b[2:0]           -  -      -    
+  -                                         -     -     -      rx_lane_ctrl_5                            0x00042006       1     RW       uint32      b[2:0]           -  -      -    
+  -                                         -     -     -      rx_lane_ctrl_6                            0x00042007       1     RW       uint32      b[2:0]           -  -      -    
+  -                                         -     -     -      rx_lane_ctrl_7                            0x00042008       1     RW       uint32      b[2:0]           -  -      -    
+  -                                         -     -     -      rx_dll_ctrl                               0x00042014       1     RW       uint32     b[16:0]           -  -      -    
+  -                                         -     -     -      rx_syncn_sysref_ctrl                      0x00042015       1     RW       uint32     b[24:0]           -  -      -    
+  -                                         -     -     -      rx_csr_sysref_always_on                   0x00042015       1     RW       uint32      b[1:1]           -  -      -    
+  -                                         -     -     -      rx_csr_rbd_offset                         0x00042015       1     RW       uint32     b[10:3]           -  -      -    
+  -                                         -     -     -      rx_csr_lmfc_offset                        0x00042015       1     RW       uint32    b[19:12]           -  -      -    
+  -                                         -     -     -      rx_err0                                   0x00042018       1     RW       uint32      b[8:0]           -  -      -    
+  -                                         -     -     -      rx_err1                                   0x00042019       1     RW       uint32      b[9:0]           -  -      -    
+  -                                         -     -     -      csr_dev_syncn                             0x00042020       1     RO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      csr_rbd_count                             0x00042020       1     RO       uint32     b[10:3]           -  -      -    
+  -                                         -     -     -      rx_status1                                0x00042021       1     RW       uint32     b[23:0]           -  -      -    
+  -                                         -     -     -      rx_status2                                0x00042022       1     RW       uint32     b[23:0]           -  -      -    
+  -                                         -     -     -      rx_status3                                0x00042023       1     RW       uint32      b[7:0]           -  -      -    
+  -                                         -     -     -      rx_ilas_csr_l                             0x00042025       1     RW       uint32      b[4:0]           -  -      -    
+  -                                         -     -     -      rx_ilas_csr_f                             0x00042025       1     RW       uint32     b[15:8]           -  -      -    
+  -                                         -     -     -      rx_ilas_csr_k                             0x00042025       1     RW       uint32    b[20:16]           -  -      -    
+  -                                         -     -     -      rx_ilas_csr_m                             0x00042025       1     RW       uint32    b[31:24]           -  -      -    
+  -                                         -     -     -      rx_ilas_csr_n                             0x00042026       1     RW       uint32      b[4:0]           -  -      -    
+  -                                         -     -     -      rx_ilas_csr_cs                            0x00042026       1     RW       uint32      b[7:6]           -  -      -    
+  -                                         -     -     -      rx_ilas_csr_np                            0x00042026       1     RW       uint32     b[12:8]           -  -      -    
+  -                                         -     -     -      rx_ilas_csr_subclassv                     0x00042026       1     RW       uint32    b[15:13]           -  -      -    
+  -                                         -     -     -      rx_ilas_csr_s                             0x00042026       1     RW       uint32    b[20:16]           -  -      -    
+  -                                         -     -     -      rx_ilas_csr_jesdv                         0x00042026       1     RW       uint32    b[23:21]           -  -      -    
+  -                                         -     -     -      rx_ilas_csr_cf                            0x00042026       1     RW       uint32    b[28:24]           -  -      -    
+  -                                         -     -     -      rx_ilas_csr_hd                            0x00042026       1     RW       uint32    b[31:31]           -  -      -    
+  -                                         -     -     -      rx_status4                                0x0004203c       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_status5                                0x0004203d       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_status6                                0x0004203e       1     RW       uint32     b[23:0]           -  -      -    
+  -                                         -     -     -      rx_status7                                0x0004203f       1     RO       uint32     b[31:0]           -  -      -    
+  REG_DP_SHIFTRAM                           1     12    REG    shift                                     0x00043180       1     RW       uint32     b[11:0]           -  -      2    
+  REG_BSN_SOURCE_V2                         1     1     REG    dp_on                                     0x00043208       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      dp_on_pps                                 0x00043208       1     RW       uint32      b[1:1]           -  -      -    
+  -                                         -     -     -      nof_clk_per_sync                          0x00043209       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      bsn_init                                  0x0004320a       1     RW       uint64     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      -                                         0x0004320b       -      -            -     b[31:0]    b[63:32]  -      -    
+  -                                         -     -     -      bsn_time_offset                           0x0004320c       1     RW       uint32      b[9:0]           -  -      -    
+  REG_BSN_SCHEDULER                         1     1     REG    scheduled_bsn                             0x0004324c       1     RW       uint64     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      -                                         0x0004324d       -      -            -     b[31:0]    b[63:32]  -      -    
   REG_BSN_MONITOR_INPUT                     1     1     REG    xon_stable                                0x00000100       1     RO       uint32      b[0:0]           -  -      -    
   -                                         -     -     -      ready_stable                              0x00000100       1     RO       uint32      b[1:1]           -  -      -    
   -                                         -     -     -      sync_timeout                              0x00000100       1     RO       uint32      b[2:2]           -  -      -    
@@ -138,27 +138,27 @@ number_of_columns = 13
   -                                         -     -     -      bsn_first                                 0x00000106       1     RO       uint64     b[31:0]     b[31:0]  -      -    
   -                                         -     -     -      -                                         0x00000107       -      -            -     b[31:0]    b[63:32]  -      -    
   -                                         -     -     -      bsn_first_cycle_cnt                       0x00000108       1     RO       uint32     b[31:0]           -  -      -    
-  REG_WG                                    1     12    REG    mode                                      0x0003d080       1     RW       uint32      b[7:0]           -  -      4    
-  -                                         -     -     -      nof_samples                               0x0003d080       1     RW       uint32    b[31:16]           -  -      -    
-  -                                         -     -     -      phase                                     0x0003d081       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      freq                                      0x0003d082       1     RW       uint32     b[30:0]           -  -      -    
-  -                                         -     -     -      ampl                                      0x0003d083       1     RW       uint32     b[16:0]           -  -      -    
-  RAM_WG                                    1     12    RAM    data                                      0x0002c000    1024     RW       uint32     b[17:0]           -  -      1024 
-  RAM_ST_HISTOGRAM                          1     12    RAM    data                                      0x00006000     512     RW       uint32     b[31:0]     b[27:0]  -      512  
-  REG_ADUH_MONITOR                          1     12    REG    mean_sum                                  0x0003d0c0       1     RO        int64     b[31:0]     b[31:0]  -      4    
-  -                                         -     -     -      -                                         0x0003d0c1       -      -            -     b[31:0]    b[63:32]  -      -    
-  -                                         -     -     -      power_sum                                 0x0003d0c2       1     RO        int64     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      -                                         0x0003d0c3       -      -            -     b[31:0]    b[63:32]  -      -    
-  REG_DIAG_DATA_BUFFER_BSN                  1     12    REG    sync_cnt                                  0x00000020       1     RO       uint32     b[31:0]           -  -      2    
-  -                                         -     -     -      word_cnt                                  0x00000021       1     RO       uint32     b[31:0]           -  -      -    
+  REG_WG                                    1     12    REG    mode                                      0x00043080       1     RW       uint32      b[7:0]           -  -      4    
+  -                                         -     -     -      nof_samples                               0x00043080       1     RW       uint32    b[31:16]           -  -      -    
+  -                                         -     -     -      phase                                     0x00043081       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      freq                                      0x00043082       1     RW       uint32     b[30:0]           -  -      -    
+  -                                         -     -     -      ampl                                      0x00043083       1     RW       uint32     b[16:0]           -  -      -    
+  RAM_WG                                    1     12    RAM    data                                      0x00034000    1024     RW       uint32     b[17:0]           -  -      1024 
+  RAM_ST_HISTOGRAM                          1     12    RAM    data                                      0x00002000     512     RW       uint32     b[31:0]     b[27:0]  -      512  
+  REG_ADUH_MONITOR                          1     12    REG    mean_sum                                  0x000430c0       1     RO        int64     b[31:0]     b[31:0]  -      4    
+  -                                         -     -     -      -                                         0x000430c1       -      -            -     b[31:0]    b[63:32]  -      -    
+  -                                         -     -     -      power_sum                                 0x000430c2       1     RO        int64     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      -                                         0x000430c3       -      -            -     b[31:0]    b[63:32]  -      -    
+  REG_DIAG_DATA_BUFFER_BSN                  1     12    REG    sync_cnt                                  0x00000c20       1     RO       uint32     b[31:0]           -  -      2    
+  -                                         -     -     -      word_cnt                                  0x00000c21       1     RO       uint32     b[31:0]           -  -      -    
   RAM_DIAG_DATA_BUFFER_BSN                  1     12    RAM    data                                      0x00200000    1024     RW       uint32     b[31:0]     b[15:0]  -      1024 
-  REG_SI                                    1     1     REG    enable                                    0x0003d238       1     RW       uint32      b[0:0]           -  -      -    
-  RAM_FIL_COEFS                             1     16    RAM    data                                      0x00030000    1024     RW       uint32     b[15:0]           -  -      1024 
-  RAM_EQUALIZER_GAINS                       1     6     RAM    data                                      0x0003a000    1024     RW    cint16_ir     b[31:0]           -  -      1024 
-  REG_DP_SELECTOR                           1     1     REG    input_select                              0x0003d234       1     RW       uint32      b[0:0]           -  -      -    
-  RAM_ST_SST                                1     6     RAM    data                                      0x00034000    1024     RW       uint64     b[31:0]     b[31:0]  -      2048 
-  -                                         -     -     -      -                                         0x00034001       -      -            -     b[21:0]    b[53:32]  -      -    
-  REG_STAT_ENABLE_SST                       1     1     REG    enable                                    0x0003d22e       1     RW       uint32      b[0:0]           -  -      -    
+  REG_SI                                    1     1     REG    enable                                    0x0004324e       1     RW       uint32      b[0:0]           -  -      -    
+  RAM_FIL_COEFS                             1     16    RAM    data                                      0x00038000    1024     RW       uint32     b[15:0]           -  -      1024 
+  RAM_EQUALIZER_GAINS                       1     6     RAM    data                                      0x00040000    1024     RW    cint16_ir     b[31:0]           -  -      1024 
+  REG_DP_SELECTOR                           1     1     REG    input_select                              0x0004324a       1     RW       uint32      b[0:0]           -  -      -    
+  RAM_ST_SST                                1     6     RAM    data                                      0x0003c000    1024     RW       uint64     b[31:0]     b[31:0]  -      2048 
+  -                                         -     -     -      -                                         0x0003c001       -      -            -     b[21:0]    b[53:32]  -      -    
+  REG_STAT_ENABLE_SST                       1     1     REG    enable                                    0x00043244       1     RW       uint32      b[0:0]           -  -      -    
   REG_STAT_HDR_DAT_SST                      1     1     REG    bsn                                       0x00000c40       1     RW       uint64     b[31:0]     b[31:0]  -      -    
   -                                         -     -     -      -                                         0x00000c41       -      -            -     b[31:0]    b[63:32]  -      -    
   -                                         -     -     -      sdp_block_period                          0x00000c42       1     RW       uint32     b[15:0]           -  -      -    
@@ -205,27 +205,27 @@ number_of_columns = 13
   -                                         -     -     -      eth_destination_mac                       0x00000c69       1     RW       uint64     b[31:0]     b[31:0]  -      -    
   -                                         -     -     -      -                                         0x00000c6a       -      -            -     b[15:0]    b[47:32]  -      -    
   -                                         -     -     -      word_align                                0x00000c6b       1     RW       uint32     b[15:0]           -  -      -    
-  REG_BSN_SYNC_SCHEDULER_XSUB               1     1     REG    ctrl_enable                               0x0003d1a0       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      ctrl_interval_size                        0x0003d1a1       1     RW       uint32     b[30:0]           -  -      -    
-  -                                         -     -     -      ctrl_start_bsn                            0x0003d1a2       1     RW       uint64     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      -                                         0x0003d1a3       -      -            -     b[31:0]    b[63:32]  -      -    
-  -                                         -     -     -      mon_current_input_bsn                     0x0003d1a4       1     RO       uint64     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      -                                         0x0003d1a5       -      -            -     b[31:0]    b[63:32]  -      -    
-  -                                         -     -     -      mon_input_bsn_at_sync                     0x0003d1a6       1     RO       uint64     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      -                                         0x0003d1a7       -      -            -     b[31:0]    b[63:32]  -      -    
-  -                                         -     -     -      mon_output_enable                         0x0003d1a8       1     RO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      mon_output_sync_bsn                       0x0003d1a9       1     RO       uint64     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      -                                         0x0003d1aa       -      -            -     b[31:0]    b[63:32]  -      -    
-  -                                         -     -     -      block_size                                0x0003d1ab       1     RO       uint32     b[31:0]           -  -      -    
+  REG_BSN_SYNC_SCHEDULER_XSUB               1     1     REG    ctrl_enable                               0x000431b0       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      ctrl_interval_size                        0x000431b1       1     RW       uint32     b[30:0]           -  -      -    
+  -                                         -     -     -      ctrl_start_bsn                            0x000431b2       1     RW       uint64     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      -                                         0x000431b3       -      -            -     b[31:0]    b[63:32]  -      -    
+  -                                         -     -     -      mon_current_input_bsn                     0x000431b4       1     RO       uint64     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      -                                         0x000431b5       -      -            -     b[31:0]    b[63:32]  -      -    
+  -                                         -     -     -      mon_input_bsn_at_sync                     0x000431b6       1     RO       uint64     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      -                                         0x000431b7       -      -            -     b[31:0]    b[63:32]  -      -    
+  -                                         -     -     -      mon_output_enable                         0x000431b8       1     RO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      mon_output_sync_bsn                       0x000431b9       1     RO       uint64     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      -                                         0x000431ba       -      -            -     b[31:0]    b[63:32]  -      -    
+  -                                         -     -     -      block_size                                0x000431bb       1     RO       uint32     b[31:0]           -  -      -    
   RAM_ST_XSQ                                1     9     RAM    data                                      0x00010000    1008     RW    cint64_ir     b[31:0]     b[31:0]  -      4096 
   -                                         -     -     -      -                                         0x00010001       -      -            -     b[31:0]    b[63:32]  -      -    
   -                                         -     -     -      -                                         0x00010002       -      -            -     b[31:0]    b[95:64]  -      -    
   -                                         -     -     -      -                                         0x00010003       -      -            -     b[31:0]   b[127:96]  -      -    
-  REG_CROSSLETS_INFO                        1     1     REG    offset                                    0x0003d1b0      15     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      step                                      0x0003d1bf       1     RW       uint32     b[31:0]           -  -      -    
-  REG_NOF_CROSSLETS                         1     1     REG    nof_crosslets                             0x0003d22a       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      unused                                    0x0003d22b       1     RW       uint32     b[31:0]           -  -      -    
-  REG_STAT_ENABLE_XST                       1     1     REG    enable                                    0x0003d22c       1     RW       uint32      b[0:0]           -  -      -    
+  REG_CROSSLETS_INFO                        1     1     REG    offset                                    0x000431c0      15     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      step                                      0x000431cf       1     RW       uint32     b[31:0]           -  -      -    
+  REG_NOF_CROSSLETS                         1     1     REG    nof_crosslets                             0x00043240       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      unused                                    0x00043241       1     RW       uint32     b[31:0]           -  -      -    
+  REG_STAT_ENABLE_XST                       1     1     REG    enable                                    0x00043242       1     RW       uint32      b[0:0]           -  -      -    
   REG_STAT_HDR_DAT_XST                      1     1     REG    bsn                                       0x00000040       1     RW       uint64     b[31:0]     b[31:0]  -      -    
   -                                         -     -     -      -                                         0x00000041       -      -            -     b[31:0]    b[63:32]  -      -    
   -                                         -     -     -      block_period                              0x00000042       1     RW       uint32     b[15:0]           -  -      -    
@@ -274,8 +274,9 @@ number_of_columns = 13
   -                                         -     -     -      eth_destination_mac                       0x00000069       1     RW       uint64     b[31:0]     b[31:0]  -      -    
   -                                         -     -     -      -                                         0x0000006a       -      -            -     b[15:0]    b[47:32]  -      -    
   -                                         -     -     -      word_align                                0x0000006b       1     RW       uint32     b[15:0]           -  -      -    
-  REG_BSN_ALIGN                             1     9     REG    enable                                    0x0003d190       1     RW       uint32      b[0:0]           -  -      1    
-  REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT        1     9     REG    xon_stable                                0x00000d00       1     RO       uint32      b[0:0]           -  -      8    
+  REG_BSN_ALIGN_V2                          1     9     REG    enable                                    0x00000020       1     RW       uint32      b[0:0]           -  -      2    
+  -                                         -     -     -      replaced_pkt_cnt                          0x00000021       1     RO       uint32     b[31:0]           -  -      -    
+  REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT     1     9     REG    xon_stable                                0x00000d00       1     RO       uint32      b[0:0]           -  -      8    
   -                                         -     -     -      ready_stable                              0x00000d00       1     RO       uint32      b[1:1]           -  -      -    
   -                                         -     -     -      sync_timeout                              0x00000d00       1     RO       uint32      b[2:2]           -  -      -    
   -                                         -     -     -      bsn_at_sync                               0x00000d01       1     RO       uint64     b[31:0]     b[31:0]  -      -    
@@ -284,26 +285,26 @@ number_of_columns = 13
   -                                         -     -     -      nof_valid                                 0x00000d04       1     RO       uint32     b[31:0]           -  -      -    
   -                                         -     -     -      nof_err                                   0x00000d05       1     RO       uint32     b[31:0]           -  -      -    
   -                                         -     -     -      latency                                   0x00000d08       1     RO       uint32     b[31:0]           -  -      -    
-  REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT       1     1     REG    xon_stable                                0x0003d1e8       1     RO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      ready_stable                              0x0003d1e8       1     RO       uint32      b[1:1]           -  -      -    
-  -                                         -     -     -      sync_timeout                              0x0003d1e8       1     RO       uint32      b[2:2]           -  -      -    
-  -                                         -     -     -      bsn_at_sync                               0x0003d1e9       1     RO       uint64     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      -                                         0x0003d1ea       -      -            -     b[31:0]    b[63:32]  -      -    
-  -                                         -     -     -      nof_sop                                   0x0003d1eb       1     RO       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      nof_valid                                 0x0003d1ec       1     RO       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      nof_err                                   0x0003d1ed       1     RO       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      latency                                   0x0003d1f0       1     RO       uint32     b[31:0]           -  -      -    
-  REG_XST_UDP_MONITOR                       1     1     REG    xon_stable                                0x0003d1e0       1     RO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      ready_stable                              0x0003d1e0       1     RO       uint32      b[1:1]           -  -      -    
-  -                                         -     -     -      sync_timeout                              0x0003d1e0       1     RO       uint32      b[2:2]           -  -      -    
-  -                                         -     -     -      bsn_at_sync                               0x0003d1e1       1     RO       uint64     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      -                                         0x0003d1e2       -      -            -     b[31:0]    b[63:32]  -      -    
-  -                                         -     -     -      nof_sop                                   0x0003d1e3       1     RO       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      nof_valid                                 0x0003d1e4       1     RO       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      nof_err                                   0x0003d1e5       1     RO       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      latency                                   0x0003d1e8       1     RO       uint32     b[31:0]           -  -      -    
-  REG_RING_LANE_INFO_XST                    1     1     REG    lane_direction                            0x0003d228       1     RO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      transport_nof_hops                        0x0003d229       1     RW       uint32     b[31:0]           -  -      -    
+  REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT    1     1     REG    xon_stable                                0x00043200       1     RO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      ready_stable                              0x00043200       1     RO       uint32      b[1:1]           -  -      -    
+  -                                         -     -     -      sync_timeout                              0x00043200       1     RO       uint32      b[2:2]           -  -      -    
+  -                                         -     -     -      bsn_at_sync                               0x00043201       1     RO       uint64     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      -                                         0x00043202       -      -            -     b[31:0]    b[63:32]  -      -    
+  -                                         -     -     -      nof_sop                                   0x00043203       1     RO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      nof_valid                                 0x00043204       1     RO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      nof_err                                   0x00043205       1     RO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      latency                                   0x00043208       1     RO       uint32     b[31:0]           -  -      -    
+  REG_BSN_MONITOR_V2_XST_OFFLOAD            1     1     REG    xon_stable                                0x000431f8       1     RO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      ready_stable                              0x000431f8       1     RO       uint32      b[1:1]           -  -      -    
+  -                                         -     -     -      sync_timeout                              0x000431f8       1     RO       uint32      b[2:2]           -  -      -    
+  -                                         -     -     -      bsn_at_sync                               0x000431f9       1     RO       uint64     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      -                                         0x000431fa       -      -            -     b[31:0]    b[63:32]  -      -    
+  -                                         -     -     -      nof_sop                                   0x000431fb       1     RO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      nof_valid                                 0x000431fc       1     RO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      nof_err                                   0x000431fd       1     RO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      latency                                   0x00043200       1     RO       uint32     b[31:0]           -  -      -    
+  REG_RING_LANE_INFO_XST                    1     1     REG    lane_direction                            0x00000c02       1     RO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      transport_nof_hops                        0x00000c03       1     RW       uint32     b[31:0]           -  -      -    
   REG_BSN_MONITOR_V2_RING_RX_XST            1     16    REG    xon_stable                                0x00000c80       1     RO       uint32      b[0:0]           -  -      8    
   -                                         -     -     -      ready_stable                              0x00000c80       1     RO       uint32      b[1:1]           -  -      -    
   -                                         -     -     -      sync_timeout                              0x00000c80       1     RO       uint32      b[2:2]           -  -      -    
@@ -322,242 +323,242 @@ number_of_columns = 13
   -                                         -     -     -      nof_valid                                 0x00000084       1     RO       uint32     b[31:0]           -  -      -    
   -                                         -     -     -      nof_err                                   0x00000085       1     RO       uint32     b[31:0]           -  -      -    
   -                                         -     -     -      latency                                   0x00000088       1     RO       uint32     b[31:0]           -  -      -    
-  REG_DP_BLOCK_VALIDATE_ERR_XST             1     1     REG    err_count_index                           0x0003d180       8     RO       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      total_discarded_blocks                    0x0003d188       1     RO       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      total_block_count                         0x0003d189       1     RO       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      clear                                     0x0003d18a       1     RW       uint32     b[31:0]           -  -      -    
-  REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST     1     1     REG    nof_sync_discarded                        0x0003d214       1     RO       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      nof_sync                                  0x0003d215       1     RO       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      clear                                     0x0003d216       1     RW       uint32     b[31:0]           -  -      -    
-  REG_TR_10GBE_MAC                          1     3     REG    rx_transfer_control                       0x00002000       1     RW       uint32      b[0:0]           -  -      1    
-  -                                         -     -     -      rx_transfer_status                        0x00002001       1     RO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      tx_transfer_control                       0x00002002       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      rx_padcrc_control                         0x00002040       1     RW       uint32      b[1:0]           -  -      -    
-  -                                         -     -     -      rx_crccheck_control                       0x00002080       1     RW       uint32      b[1:0]           -  -      -    
-  -                                         -     -     -      rx_pktovrflow_error                       0x000020c0       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x000020c1       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_pktovrflow_etherstatsdropevents        0x000020c2       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x000020c3       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_lane_decoder_preamble_control          0x00002100       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      rx_preamble_inserter_control              0x00002140       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      rx_frame_control                          0x00002800       1     RW       uint32     b[19:0]           -  -      -    
-  -                                         -     -     -      rx_frame_maxlength                        0x00002801       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_addr0                            0x00002802       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_addr1                            0x00002803       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr0_0                        0x00002804       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr0_1                        0x00002805       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr1_0                        0x00002806       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr1_1                        0x00002807       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr2_0                        0x00002808       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr2_1                        0x00002809       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr3_0                        0x0000280a       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr3_1                        0x0000280b       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_pfc_control                            0x00002818       1     RW       uint32     b[16:0]           -  -      -    
-  -                                         -     -     -      rx_stats_clr                              0x00002c00       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      rx_stats_framesok                         0x00002c02       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c03       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_frameserr                        0x00002c04       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c05       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_framescrcerr                     0x00002c06       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c07       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_octetsok                         0x00002c08       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c09       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_pausemacctrl_frames              0x00002c0a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c0b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_iferrors                         0x00002c0c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c0d       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_unicast_framesok                 0x00002c0e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c0f       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_unicast_frameserr                0x00002c10       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c11       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_multicastframesok                0x00002c12       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c13       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_multicast_frameserr              0x00002c14       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c15       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_broadcastframesok                0x00002c16       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c17       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_broadcast_frameserr              0x00002c18       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c19       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstatsoctets                 0x00002c1a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c1b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstatspkts                   0x00002c1c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c1d       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_undersizepkts         0x00002c1e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c1f       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_oversizepkts          0x00002c20       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c21       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_pkts64octets          0x00002c22       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c23       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_pkts65to127octets     0x00002c24       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c25       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_pkts128to255octets    0x00002c26       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c27       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_pkts256to511octets    0x00002c28       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c29       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_pkts512to1023octets   0x00002c2a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c2b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstat_pkts1024to1518octets   0x00002c2c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c2d       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_pkts1519toxoctets     0x00002c2e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c2f       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_fragments             0x00002c30       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c31       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_jabbers               0x00002c32       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c33       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstatscrcerr                 0x00002c34       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c35       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_unicastmacctrlframes             0x00002c36       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c37       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_multicastmac_ctrlframes          0x00002c38       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c39       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_broadcastmac_ctrlframes          0x00002c3a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c3b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_pfcmacctrlframes                 0x00002c3c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00002c3d       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_transfer_status                        0x00003001       1     RO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      tx_padins_control                         0x00003040       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      tx_crcins_control                         0x00003080       1     RW       uint32      b[1:0]           -  -      -    
-  -                                         -     -     -      tx_pktunderflow_error                     0x000030c0       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x000030c1       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_preamble_control                       0x00003100       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      tx_pauseframe_control                     0x00003140       1     RW       uint32      b[1:0]           -  -      -    
-  -                                         -     -     -      tx_pauseframe_quanta                      0x00003141       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      tx_pauseframe_enable                      0x00003142       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_0                        0x00003180       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_1                        0x00003181       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_2                        0x00003182       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_3                        0x00003183       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_4                        0x00003184       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_5                        0x00003185       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_6                        0x00003186       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_7                        0x00003187       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_0                      0x00003190       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_1                      0x00003191       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_2                      0x00003192       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_3                      0x00003193       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_4                      0x00003194       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_5                      0x00003195       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_6                      0x00003196       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_7                      0x00003197       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      tx_pfc_priority_enable                    0x000031a0       1     RW       uint32      b[7:0]           -  -      -    
-  -                                         -     -     -      tx_addrins_control                        0x00003200       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      tx_addrins_macaddr0                       0x00003201       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      tx_addrins_macaddr1                       0x00003202       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      tx_frame_maxlength                        0x00003801       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      tx_stats_clr                              0x00003c00       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      tx_stats_framesok                         0x00003c02       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c03       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_frameserr                        0x00003c04       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c05       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_framescrcerr                     0x00003c06       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c07       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_octetsok                         0x00003c08       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c09       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_pausemacctrl_frames              0x00003c0a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c0b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_iferrors                         0x00003c0c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c0d       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_unicast_framesok                 0x00003c0e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c0f       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_unicast_frameserr                0x00003c10       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c11       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_multicastframesok                0x00003c12       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c13       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_multicast_frameserr              0x00003c14       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c15       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_broadcastframesok                0x00003c16       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c17       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_broadcast_frameserr              0x00003c18       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c19       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstatsoctets                 0x00003c1a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c1b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstatspkts                   0x00003c1c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c1d       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_undersizepkts         0x00003c1e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c1f       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_oversizepkts          0x00003c20       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c21       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_pkts64octets          0x00003c22       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c23       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_pkts65to127octets     0x00003c24       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c25       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_pkts128to255octets    0x00003c26       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c27       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_pkts256to511octets    0x00003c28       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c29       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_pkts512to1023octets   0x00003c2a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c2b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstat_pkts1024to1518octets   0x00003c2c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c2d       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_pkts1519toxoctets     0x00003c2e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c2f       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_fragments             0x00003c30       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c31       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_jabbers               0x00003c32       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c33       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstatscrcerr                 0x00003c34       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c35       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_unicastmacctrlframes             0x00003c36       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c37       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_multicastmac_ctrlframes          0x00003c38       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c39       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_broadcastmac_ctrlframes          0x00003c3a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c3b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_pfcmacctrlframes                 0x00003c3c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00003c3d       -      -            -     b[31:0]     b[31:0]  -      -    
-  REG_TR_10GBE_ETH10G                       1     3     REG    tx_snk_out_xon                            0x00000c02       1     RO       uint32      b[0:0]           -  -      1    
-  -                                         -     -     -      xgmii_tx_ready                            0x00000c02       1     RO       uint32      b[1:1]           -  -      -    
-  -                                         -     -     -      xgmii_link_status                         0x00000c02       1     RO       uint32      b[3:2]           -  -      -    
-  RAM_SS_SS_WIDE                            2     6     RAM    data                                      0x00028000     976     RW       uint32      b[9:0]           -  8192   1024 
-  RAM_BF_WEIGHTS                            2     12    RAM    data                                      0x00020000     976     RW    cint16_ir     b[31:0]           -  16384  1024 
-  REG_BF_SCALE                              2     1     REG    scale                                     0x0003d220       1     RW       uint32     b[15:0]           -  2      2    
-  -                                         -     -     -      unused                                    0x0003d221       1     RW       uint32     b[31:0]           -  -      -    
-  REG_HDR_DAT                               2     1     REG    bsn                                       0x0003d000       1     RW       uint64     b[31:0]     b[31:0]  64     64   
-  -                                         -     -     -      -                                         0x0003d001       -      -            -     b[31:0]    b[63:32]  -      -    
-  -                                         -     -     -      sdp_block_period                          0x0003d002       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      sdp_nof_beamlets_per_block                0x0003d003       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      sdp_nof_blocks_per_packet                 0x0003d004       1     RW       uint32      b[7:0]           -  -      -    
-  -                                         -     -     -      sdp_beamlet_index                         0x0003d005       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      sdp_beamlet_scale                         0x0003d006       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      sdp_reserved                              0x0003d007       1     RW       uint64     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      -                                         0x0003d008       -      -            -      b[7:0]    b[39:32]  -      -    
-  -                                         -     -     -      sdp_source_info_gn_index                  0x0003d009       1     RW       uint32      b[4:0]           -  -      -    
-  -                                         -     -     -      sdp_source_info_beamlet_width             0x0003d00a       1     RW       uint32      b[7:5]           -  -      -    
-  -                                         -     -     -      sdp_source_info_repositioning_flag        0x0003d00b       1     RW       uint32      b[9:9]           -  -      -    
-  -                                         -     -     -      sdp_source_info_payload_error             0x0003d00c       1     RW       uint32    b[10:10]           -  -      -    
-  -                                         -     -     -      sdp_source_info_fsub_type                 0x0003d00d       1     RW       uint32    b[11:11]           -  -      -    
-  -                                         -     -     -      sdp_source_info_f_adc                     0x0003d00e       1     RW       uint32    b[12:12]           -  -      -    
-  -                                         -     -     -      sdp_source_info_nyquist_zone_index        0x0003d00f       1     RW       uint32    b[14:13]           -  -      -    
-  -                                         -     -     -      sdp_source_info_antenna_band_index        0x0003d010       1     RW       uint32    b[15:15]           -  -      -    
-  -                                         -     -     -      sdp_station_id                            0x0003d011       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      sdp_observation_id                        0x0003d012       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      sdp_version_id                            0x0003d013       1     RO       uint32      b[7:0]           -  -      -    
-  -                                         -     -     -      sdp_marker                                0x0003d014       1     RO       uint32      b[7:0]           -  -      -    
-  -                                         -     -     -      udp_checksum                              0x0003d015       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      udp_length                                0x0003d016       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      udp_destination_port                      0x0003d017       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      udp_source_port                           0x0003d018       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      ip_destination_address                    0x0003d019       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      ip_source_address                         0x0003d01a       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      ip_header_checksum                        0x0003d01b       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      ip_protocol                               0x0003d01c       1     RW       uint32      b[7:0]           -  -      -    
-  -                                         -     -     -      ip_time_to_live                           0x0003d01d       1     RW       uint32      b[7:0]           -  -      -    
-  -                                         -     -     -      ip_fragment_offset                        0x0003d01e       1     RW       uint32     b[12:0]           -  -      -    
-  -                                         -     -     -      ip_flags                                  0x0003d01f       1     RW       uint32      b[2:0]           -  -      -    
-  -                                         -     -     -      ip_identification                         0x0003d020       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      ip_total_length                           0x0003d021       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      ip_services                               0x0003d022       1     RW       uint32      b[7:0]           -  -      -    
-  -                                         -     -     -      ip_header_length                          0x0003d023       1     RW       uint32      b[3:0]           -  -      -    
-  -                                         -     -     -      ip_version                                0x0003d024       1     RW       uint32      b[3:0]           -  -      -    
-  -                                         -     -     -      eth_type                                  0x0003d025       1     RO       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      eth_source_mac                            0x0003d026       1     RO       uint64     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      -                                         0x0003d027       -      -            -     b[15:0]    b[47:32]  -      -    
-  -                                         -     -     -      eth_destination_mac                       0x0003d028       1     RW       uint64     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      -                                         0x0003d029       -      -            -     b[15:0]    b[47:32]  -      -    
-  REG_DP_XONOFF                             2     1     REG    enable_stream                             0x0003d21c       1     RW       uint32      b[0:0]           -  2      2    
+  REG_DP_BLOCK_VALIDATE_ERR_XST             1     1     REG    err_count_index                           0x000431a0       8     RO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      total_discarded_blocks                    0x000431a8       1     RO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      total_block_count                         0x000431a9       1     RO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      clear                                     0x000431aa       1     RW       uint32     b[31:0]           -  -      -    
+  REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST     1     1     REG    nof_sync_discarded                        0x0004322c       1     RO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      nof_sync                                  0x0004322d       1     RO       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      clear                                     0x0004322e       1     RW       uint32     b[31:0]           -  -      -    
+  REG_TR_10GBE_MAC                          1     3     REG    rx_transfer_control                       0x00020000       1     RW       uint32      b[0:0]           -  -      1    
+  -                                         -     -     -      rx_transfer_status                        0x00020001       1     RO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      tx_transfer_control                       0x00020002       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      rx_padcrc_control                         0x00020040       1     RW       uint32      b[1:0]           -  -      -    
+  -                                         -     -     -      rx_crccheck_control                       0x00020080       1     RW       uint32      b[1:0]           -  -      -    
+  -                                         -     -     -      rx_pktovrflow_error                       0x000200c0       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x000200c1       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_pktovrflow_etherstatsdropevents        0x000200c2       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x000200c3       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_lane_decoder_preamble_control          0x00020100       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      rx_preamble_inserter_control              0x00020140       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      rx_frame_control                          0x00020800       1     RW       uint32     b[19:0]           -  -      -    
+  -                                         -     -     -      rx_frame_maxlength                        0x00020801       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_addr0                            0x00020802       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_addr1                            0x00020803       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr0_0                        0x00020804       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr0_1                        0x00020805       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr1_0                        0x00020806       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr1_1                        0x00020807       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr2_0                        0x00020808       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr2_1                        0x00020809       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr3_0                        0x0002080a       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr3_1                        0x0002080b       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_pfc_control                            0x00020818       1     RW       uint32     b[16:0]           -  -      -    
+  -                                         -     -     -      rx_stats_clr                              0x00020c00       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      rx_stats_framesok                         0x00020c02       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c03       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_frameserr                        0x00020c04       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c05       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_framescrcerr                     0x00020c06       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c07       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_octetsok                         0x00020c08       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c09       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_pausemacctrl_frames              0x00020c0a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c0b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_iferrors                         0x00020c0c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c0d       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_unicast_framesok                 0x00020c0e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c0f       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_unicast_frameserr                0x00020c10       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c11       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_multicastframesok                0x00020c12       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c13       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_multicast_frameserr              0x00020c14       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c15       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_broadcastframesok                0x00020c16       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c17       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_broadcast_frameserr              0x00020c18       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c19       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstatsoctets                 0x00020c1a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c1b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstatspkts                   0x00020c1c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c1d       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_undersizepkts         0x00020c1e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c1f       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_oversizepkts          0x00020c20       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c21       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_pkts64octets          0x00020c22       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c23       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_pkts65to127octets     0x00020c24       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c25       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_pkts128to255octets    0x00020c26       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c27       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_pkts256to511octets    0x00020c28       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c29       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_pkts512to1023octets   0x00020c2a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c2b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstat_pkts1024to1518octets   0x00020c2c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c2d       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_pkts1519toxoctets     0x00020c2e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c2f       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_fragments             0x00020c30       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c31       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_jabbers               0x00020c32       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c33       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstatscrcerr                 0x00020c34       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c35       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_unicastmacctrlframes             0x00020c36       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c37       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_multicastmac_ctrlframes          0x00020c38       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c39       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_broadcastmac_ctrlframes          0x00020c3a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c3b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_pfcmacctrlframes                 0x00020c3c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00020c3d       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_transfer_status                        0x00021001       1     RO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      tx_padins_control                         0x00021040       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      tx_crcins_control                         0x00021080       1     RW       uint32      b[1:0]           -  -      -    
+  -                                         -     -     -      tx_pktunderflow_error                     0x000210c0       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x000210c1       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_preamble_control                       0x00021100       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      tx_pauseframe_control                     0x00021140       1     RW       uint32      b[1:0]           -  -      -    
+  -                                         -     -     -      tx_pauseframe_quanta                      0x00021141       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      tx_pauseframe_enable                      0x00021142       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_0                        0x00021180       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_1                        0x00021181       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_2                        0x00021182       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_3                        0x00021183       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_4                        0x00021184       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_5                        0x00021185       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_6                        0x00021186       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_7                        0x00021187       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_0                      0x00021190       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_1                      0x00021191       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_2                      0x00021192       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_3                      0x00021193       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_4                      0x00021194       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_5                      0x00021195       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_6                      0x00021196       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_7                      0x00021197       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      tx_pfc_priority_enable                    0x000211a0       1     RW       uint32      b[7:0]           -  -      -    
+  -                                         -     -     -      tx_addrins_control                        0x00021200       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      tx_addrins_macaddr0                       0x00021201       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      tx_addrins_macaddr1                       0x00021202       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      tx_frame_maxlength                        0x00021801       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      tx_stats_clr                              0x00021c00       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      tx_stats_framesok                         0x00021c02       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c03       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_frameserr                        0x00021c04       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c05       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_framescrcerr                     0x00021c06       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c07       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_octetsok                         0x00021c08       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c09       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_pausemacctrl_frames              0x00021c0a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c0b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_iferrors                         0x00021c0c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c0d       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_unicast_framesok                 0x00021c0e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c0f       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_unicast_frameserr                0x00021c10       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c11       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_multicastframesok                0x00021c12       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c13       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_multicast_frameserr              0x00021c14       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c15       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_broadcastframesok                0x00021c16       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c17       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_broadcast_frameserr              0x00021c18       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c19       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstatsoctets                 0x00021c1a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c1b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstatspkts                   0x00021c1c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c1d       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_undersizepkts         0x00021c1e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c1f       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_oversizepkts          0x00021c20       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c21       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_pkts64octets          0x00021c22       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c23       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_pkts65to127octets     0x00021c24       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c25       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_pkts128to255octets    0x00021c26       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c27       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_pkts256to511octets    0x00021c28       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c29       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_pkts512to1023octets   0x00021c2a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c2b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstat_pkts1024to1518octets   0x00021c2c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c2d       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_pkts1519toxoctets     0x00021c2e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c2f       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_fragments             0x00021c30       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c31       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_jabbers               0x00021c32       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c33       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstatscrcerr                 0x00021c34       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c35       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_unicastmacctrlframes             0x00021c36       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c37       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_multicastmac_ctrlframes          0x00021c38       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c39       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_broadcastmac_ctrlframes          0x00021c3a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c3b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_pfcmacctrlframes                 0x00021c3c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00021c3d       -      -            -     b[31:0]     b[31:0]  -      -    
+  REG_TR_10GBE_ETH10G                       1     3     REG    tx_snk_out_xon                            0x000431f0       1     RO       uint32      b[0:0]           -  -      1    
+  -                                         -     -     -      xgmii_tx_ready                            0x000431f0       1     RO       uint32      b[1:1]           -  -      -    
+  -                                         -     -     -      xgmii_link_status                         0x000431f0       1     RO       uint32      b[3:2]           -  -      -    
+  RAM_SS_SS_WIDE                            2     6     RAM    data                                      0x00030000     976     RW       uint32      b[9:0]           -  8192   1024 
+  RAM_BF_WEIGHTS                            2     12    RAM    data                                      0x00028000     976     RW    cint16_ir     b[31:0]           -  16384  1024 
+  REG_BF_SCALE                              2     1     REG    scale                                     0x00043238       1     RW       uint32     b[15:0]           -  2      2    
+  -                                         -     -     -      unused                                    0x00043239       1     RW       uint32     b[31:0]           -  -      -    
+  REG_HDR_DAT                               2     1     REG    bsn                                       0x00043000       1     RW       uint64     b[31:0]     b[31:0]  64     64   
+  -                                         -     -     -      -                                         0x00043001       -      -            -     b[31:0]    b[63:32]  -      -    
+  -                                         -     -     -      sdp_block_period                          0x00043002       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      sdp_nof_beamlets_per_block                0x00043003       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      sdp_nof_blocks_per_packet                 0x00043004       1     RW       uint32      b[7:0]           -  -      -    
+  -                                         -     -     -      sdp_beamlet_index                         0x00043005       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      sdp_beamlet_scale                         0x00043006       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      sdp_reserved                              0x00043007       1     RW       uint64     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      -                                         0x00043008       -      -            -      b[7:0]    b[39:32]  -      -    
+  -                                         -     -     -      sdp_source_info_gn_index                  0x00043009       1     RW       uint32      b[4:0]           -  -      -    
+  -                                         -     -     -      sdp_source_info_beamlet_width             0x0004300a       1     RW       uint32      b[7:5]           -  -      -    
+  -                                         -     -     -      sdp_source_info_repositioning_flag        0x0004300b       1     RW       uint32      b[9:9]           -  -      -    
+  -                                         -     -     -      sdp_source_info_payload_error             0x0004300c       1     RW       uint32    b[10:10]           -  -      -    
+  -                                         -     -     -      sdp_source_info_fsub_type                 0x0004300d       1     RW       uint32    b[11:11]           -  -      -    
+  -                                         -     -     -      sdp_source_info_f_adc                     0x0004300e       1     RW       uint32    b[12:12]           -  -      -    
+  -                                         -     -     -      sdp_source_info_nyquist_zone_index        0x0004300f       1     RW       uint32    b[14:13]           -  -      -    
+  -                                         -     -     -      sdp_source_info_antenna_band_index        0x00043010       1     RW       uint32    b[15:15]           -  -      -    
+  -                                         -     -     -      sdp_station_id                            0x00043011       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      sdp_observation_id                        0x00043012       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      sdp_version_id                            0x00043013       1     RO       uint32      b[7:0]           -  -      -    
+  -                                         -     -     -      sdp_marker                                0x00043014       1     RO       uint32      b[7:0]           -  -      -    
+  -                                         -     -     -      udp_checksum                              0x00043015       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      udp_length                                0x00043016       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      udp_destination_port                      0x00043017       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      udp_source_port                           0x00043018       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      ip_destination_address                    0x00043019       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      ip_source_address                         0x0004301a       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      ip_header_checksum                        0x0004301b       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      ip_protocol                               0x0004301c       1     RW       uint32      b[7:0]           -  -      -    
+  -                                         -     -     -      ip_time_to_live                           0x0004301d       1     RW       uint32      b[7:0]           -  -      -    
+  -                                         -     -     -      ip_fragment_offset                        0x0004301e       1     RW       uint32     b[12:0]           -  -      -    
+  -                                         -     -     -      ip_flags                                  0x0004301f       1     RW       uint32      b[2:0]           -  -      -    
+  -                                         -     -     -      ip_identification                         0x00043020       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      ip_total_length                           0x00043021       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      ip_services                               0x00043022       1     RW       uint32      b[7:0]           -  -      -    
+  -                                         -     -     -      ip_header_length                          0x00043023       1     RW       uint32      b[3:0]           -  -      -    
+  -                                         -     -     -      ip_version                                0x00043024       1     RW       uint32      b[3:0]           -  -      -    
+  -                                         -     -     -      eth_type                                  0x00043025       1     RO       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      eth_source_mac                            0x00043026       1     RO       uint64     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      -                                         0x00043027       -      -            -     b[15:0]    b[47:32]  -      -    
+  -                                         -     -     -      eth_destination_mac                       0x00043028       1     RW       uint64     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      -                                         0x00043029       -      -            -     b[15:0]    b[47:32]  -      -    
+  REG_DP_XONOFF                             2     1     REG    enable_stream                             0x00043234       1     RW       uint32      b[0:0]           -  2      2    
   RAM_ST_BST                                2     1     RAM    data                                      0x00001000     976     RW       uint64     b[31:0]     b[31:0]  2048   2048 
   -                                         -     -     -      -                                         0x00001001       -      -            -     b[21:0]    b[53:32]  -      -    
-  REG_STAT_ENABLE_BST                       2     1     REG    enable                                    0x0003d218       1     RW       uint32      b[0:0]           -  2      2    
+  REG_STAT_ENABLE_BST                       2     1     REG    enable                                    0x00043230       1     RW       uint32      b[0:0]           -  2      2    
   REG_STAT_HDR_DAT_BST                      2     1     REG    bsn                                       0x00000d80       1     RW       uint64     b[31:0]     b[31:0]  64     64   
   -                                         -     -     -      -                                         0x00000d81       -      -            -     b[31:0]    b[63:32]  -      -    
   -                                         -     -     -      block_period                              0x00000d82       1     RW       uint32     b[15:0]           -  -      -    
@@ -604,182 +605,182 @@ number_of_columns = 13
   -                                         -     -     -      eth_destination_mac                       0x00000da9       1     RW       uint64     b[31:0]     b[31:0]  -      -    
   -                                         -     -     -      -                                         0x00000daa       -      -            -     b[15:0]    b[47:32]  -      -    
   -                                         -     -     -      word_align                                0x00000dab       1     RW       uint32     b[15:0]           -  -      -    
-  REG_NW_10GBE_MAC                          1     1     REG    rx_transfer_control                       0x00038000       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      rx_transfer_status                        0x00038001       1     RO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      tx_transfer_control                       0x00038002       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      rx_padcrc_control                         0x00038040       1     RW       uint32      b[1:0]           -  -      -    
-  -                                         -     -     -      rx_crccheck_control                       0x00038080       1     RW       uint32      b[1:0]           -  -      -    
-  -                                         -     -     -      rx_pktovrflow_error                       0x000380c0       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x000380c1       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_pktovrflow_etherstatsdropevents        0x000380c2       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x000380c3       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_lane_decoder_preamble_control          0x00038100       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      rx_preamble_inserter_control              0x00038140       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      rx_frame_control                          0x00038800       1     RW       uint32     b[19:0]           -  -      -    
-  -                                         -     -     -      rx_frame_maxlength                        0x00038801       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_addr0                            0x00038802       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_addr1                            0x00038803       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr0_0                        0x00038804       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr0_1                        0x00038805       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr1_0                        0x00038806       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr1_1                        0x00038807       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr2_0                        0x00038808       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr2_1                        0x00038809       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr3_0                        0x0003880a       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_frame_spaddr3_1                        0x0003880b       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      rx_pfc_control                            0x00038818       1     RW       uint32     b[16:0]           -  -      -    
-  -                                         -     -     -      rx_stats_clr                              0x00038c00       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      rx_stats_framesok                         0x00038c02       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c03       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_frameserr                        0x00038c04       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c05       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_framescrcerr                     0x00038c06       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c07       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_octetsok                         0x00038c08       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c09       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_pausemacctrl_frames              0x00038c0a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c0b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_iferrors                         0x00038c0c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c0d       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_unicast_framesok                 0x00038c0e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c0f       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_unicast_frameserr                0x00038c10       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c11       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_multicastframesok                0x00038c12       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c13       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_multicast_frameserr              0x00038c14       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c15       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_broadcastframesok                0x00038c16       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c17       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_broadcast_frameserr              0x00038c18       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c19       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstatsoctets                 0x00038c1a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c1b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstatspkts                   0x00038c1c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c1d       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_undersizepkts         0x00038c1e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c1f       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_oversizepkts          0x00038c20       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c21       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_pkts64octets          0x00038c22       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c23       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_pkts65to127octets     0x00038c24       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c25       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_pkts128to255octets    0x00038c26       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c27       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_pkts256to511octets    0x00038c28       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c29       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_pkts512to1023octets   0x00038c2a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c2b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstat_pkts1024to1518octets   0x00038c2c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c2d       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_pkts1519toxoctets     0x00038c2e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c2f       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_fragments             0x00038c30       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c31       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstats_jabbers               0x00038c32       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c33       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_etherstatscrcerr                 0x00038c34       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c35       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_unicastmacctrlframes             0x00038c36       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c37       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_multicastmac_ctrlframes          0x00038c38       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c39       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_broadcastmac_ctrlframes          0x00038c3a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c3b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      rx_stats_pfcmacctrlframes                 0x00038c3c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00038c3d       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_transfer_status                        0x00039001       1     RO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      tx_padins_control                         0x00039040       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      tx_crcins_control                         0x00039080       1     RW       uint32      b[1:0]           -  -      -    
-  -                                         -     -     -      tx_pktunderflow_error                     0x000390c0       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x000390c1       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_preamble_control                       0x00039100       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      tx_pauseframe_control                     0x00039140       1     RW       uint32      b[1:0]           -  -      -    
-  -                                         -     -     -      tx_pauseframe_quanta                      0x00039141       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      tx_pauseframe_enable                      0x00039142       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_0                        0x00039180       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_1                        0x00039181       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_2                        0x00039182       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_3                        0x00039183       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_4                        0x00039184       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_5                        0x00039185       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_6                        0x00039186       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_pause_quanta_7                        0x00039187       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_0                      0x00039190       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_1                      0x00039191       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_2                      0x00039192       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_3                      0x00039193       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_4                      0x00039194       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_5                      0x00039195       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_6                      0x00039196       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      pfc_holdoff_quanta_7                      0x00039197       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      tx_pfc_priority_enable                    0x000391a0       1     RW       uint32      b[7:0]           -  -      -    
-  -                                         -     -     -      tx_addrins_control                        0x00039200       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      tx_addrins_macaddr0                       0x00039201       1     RW       uint32     b[31:0]           -  -      -    
-  -                                         -     -     -      tx_addrins_macaddr1                       0x00039202       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      tx_frame_maxlength                        0x00039801       1     RW       uint32     b[15:0]           -  -      -    
-  -                                         -     -     -      tx_stats_clr                              0x00039c00       1     RW       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      tx_stats_framesok                         0x00039c02       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c03       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_frameserr                        0x00039c04       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c05       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_framescrcerr                     0x00039c06       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c07       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_octetsok                         0x00039c08       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c09       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_pausemacctrl_frames              0x00039c0a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c0b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_iferrors                         0x00039c0c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c0d       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_unicast_framesok                 0x00039c0e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c0f       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_unicast_frameserr                0x00039c10       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c11       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_multicastframesok                0x00039c12       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c13       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_multicast_frameserr              0x00039c14       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c15       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_broadcastframesok                0x00039c16       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c17       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_broadcast_frameserr              0x00039c18       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c19       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstatsoctets                 0x00039c1a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c1b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstatspkts                   0x00039c1c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c1d       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_undersizepkts         0x00039c1e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c1f       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_oversizepkts          0x00039c20       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c21       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_pkts64octets          0x00039c22       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c23       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_pkts65to127octets     0x00039c24       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c25       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_pkts128to255octets    0x00039c26       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c27       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_pkts256to511octets    0x00039c28       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c29       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_pkts512to1023octets   0x00039c2a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c2b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstat_pkts1024to1518octets   0x00039c2c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c2d       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_pkts1519toxoctets     0x00039c2e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c2f       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_fragments             0x00039c30       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c31       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstats_jabbers               0x00039c32       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c33       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_etherstatscrcerr                 0x00039c34       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c35       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_unicastmacctrlframes             0x00039c36       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c37       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_multicastmac_ctrlframes          0x00039c38       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c39       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_broadcastmac_ctrlframes          0x00039c3a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c3b       -      -            -     b[31:0]     b[31:0]  -      -    
-  -                                         -     -     -      tx_stats_pfcmacctrlframes                 0x00039c3c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
-  -                                         -     -     -      -                                         0x00039c3d       -      -            -     b[31:0]     b[31:0]  -      -    
-  REG_NW_10GBE_ETH10G                       1     1     REG    tx_snk_out_xon                            0x0003d232       1     RO       uint32      b[0:0]           -  -      -    
-  -                                         -     -     -      xgmii_tx_ready                            0x0003d232       1     RO       uint32      b[1:1]           -  -      -    
-  -                                         -     -     -      xgmii_link_status                         0x0003d232       1     RO       uint32      b[3:2]           -  -      -    
\ No newline at end of file
+  REG_NW_10GBE_MAC                          1     1     REG    rx_transfer_control                       0x00006000       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      rx_transfer_status                        0x00006001       1     RO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      tx_transfer_control                       0x00006002       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      rx_padcrc_control                         0x00006040       1     RW       uint32      b[1:0]           -  -      -    
+  -                                         -     -     -      rx_crccheck_control                       0x00006080       1     RW       uint32      b[1:0]           -  -      -    
+  -                                         -     -     -      rx_pktovrflow_error                       0x000060c0       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x000060c1       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_pktovrflow_etherstatsdropevents        0x000060c2       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x000060c3       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_lane_decoder_preamble_control          0x00006100       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      rx_preamble_inserter_control              0x00006140       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      rx_frame_control                          0x00006800       1     RW       uint32     b[19:0]           -  -      -    
+  -                                         -     -     -      rx_frame_maxlength                        0x00006801       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_addr0                            0x00006802       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_addr1                            0x00006803       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr0_0                        0x00006804       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr0_1                        0x00006805       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr1_0                        0x00006806       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr1_1                        0x00006807       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr2_0                        0x00006808       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr2_1                        0x00006809       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr3_0                        0x0000680a       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_frame_spaddr3_1                        0x0000680b       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      rx_pfc_control                            0x00006818       1     RW       uint32     b[16:0]           -  -      -    
+  -                                         -     -     -      rx_stats_clr                              0x00006c00       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      rx_stats_framesok                         0x00006c02       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c03       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_frameserr                        0x00006c04       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c05       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_framescrcerr                     0x00006c06       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c07       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_octetsok                         0x00006c08       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c09       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_pausemacctrl_frames              0x00006c0a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c0b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_iferrors                         0x00006c0c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c0d       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_unicast_framesok                 0x00006c0e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c0f       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_unicast_frameserr                0x00006c10       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c11       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_multicastframesok                0x00006c12       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c13       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_multicast_frameserr              0x00006c14       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c15       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_broadcastframesok                0x00006c16       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c17       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_broadcast_frameserr              0x00006c18       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c19       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstatsoctets                 0x00006c1a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c1b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstatspkts                   0x00006c1c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c1d       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_undersizepkts         0x00006c1e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c1f       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_oversizepkts          0x00006c20       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c21       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_pkts64octets          0x00006c22       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c23       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_pkts65to127octets     0x00006c24       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c25       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_pkts128to255octets    0x00006c26       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c27       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_pkts256to511octets    0x00006c28       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c29       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_pkts512to1023octets   0x00006c2a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c2b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstat_pkts1024to1518octets   0x00006c2c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c2d       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_pkts1519toxoctets     0x00006c2e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c2f       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_fragments             0x00006c30       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c31       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstats_jabbers               0x00006c32       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c33       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_etherstatscrcerr                 0x00006c34       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c35       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_unicastmacctrlframes             0x00006c36       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c37       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_multicastmac_ctrlframes          0x00006c38       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c39       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_broadcastmac_ctrlframes          0x00006c3a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c3b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      rx_stats_pfcmacctrlframes                 0x00006c3c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00006c3d       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_transfer_status                        0x00007001       1     RO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      tx_padins_control                         0x00007040       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      tx_crcins_control                         0x00007080       1     RW       uint32      b[1:0]           -  -      -    
+  -                                         -     -     -      tx_pktunderflow_error                     0x000070c0       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x000070c1       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_preamble_control                       0x00007100       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      tx_pauseframe_control                     0x00007140       1     RW       uint32      b[1:0]           -  -      -    
+  -                                         -     -     -      tx_pauseframe_quanta                      0x00007141       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      tx_pauseframe_enable                      0x00007142       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_0                        0x00007180       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_1                        0x00007181       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_2                        0x00007182       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_3                        0x00007183       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_4                        0x00007184       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_5                        0x00007185       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_6                        0x00007186       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_pause_quanta_7                        0x00007187       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_0                      0x00007190       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_1                      0x00007191       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_2                      0x00007192       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_3                      0x00007193       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_4                      0x00007194       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_5                      0x00007195       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_6                      0x00007196       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      pfc_holdoff_quanta_7                      0x00007197       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      tx_pfc_priority_enable                    0x000071a0       1     RW       uint32      b[7:0]           -  -      -    
+  -                                         -     -     -      tx_addrins_control                        0x00007200       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      tx_addrins_macaddr0                       0x00007201       1     RW       uint32     b[31:0]           -  -      -    
+  -                                         -     -     -      tx_addrins_macaddr1                       0x00007202       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      tx_frame_maxlength                        0x00007801       1     RW       uint32     b[15:0]           -  -      -    
+  -                                         -     -     -      tx_stats_clr                              0x00007c00       1     RW       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      tx_stats_framesok                         0x00007c02       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c03       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_frameserr                        0x00007c04       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c05       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_framescrcerr                     0x00007c06       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c07       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_octetsok                         0x00007c08       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c09       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_pausemacctrl_frames              0x00007c0a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c0b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_iferrors                         0x00007c0c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c0d       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_unicast_framesok                 0x00007c0e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c0f       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_unicast_frameserr                0x00007c10       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c11       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_multicastframesok                0x00007c12       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c13       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_multicast_frameserr              0x00007c14       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c15       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_broadcastframesok                0x00007c16       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c17       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_broadcast_frameserr              0x00007c18       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c19       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstatsoctets                 0x00007c1a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c1b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstatspkts                   0x00007c1c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c1d       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_undersizepkts         0x00007c1e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c1f       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_oversizepkts          0x00007c20       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c21       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_pkts64octets          0x00007c22       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c23       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_pkts65to127octets     0x00007c24       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c25       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_pkts128to255octets    0x00007c26       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c27       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_pkts256to511octets    0x00007c28       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c29       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_pkts512to1023octets   0x00007c2a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c2b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstat_pkts1024to1518octets   0x00007c2c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c2d       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_pkts1519toxoctets     0x00007c2e       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c2f       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_fragments             0x00007c30       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c31       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstats_jabbers               0x00007c32       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c33       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_etherstatscrcerr                 0x00007c34       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c35       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_unicastmacctrlframes             0x00007c36       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c37       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_multicastmac_ctrlframes          0x00007c38       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c39       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_broadcastmac_ctrlframes          0x00007c3a       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c3b       -      -            -     b[31:0]     b[31:0]  -      -    
+  -                                         -     -     -      tx_stats_pfcmacctrlframes                 0x00007c3c       1     RO       uint64      b[3:0]    b[35:32]  -      -    
+  -                                         -     -     -      -                                         0x00007c3d       -      -            -     b[31:0]     b[31:0]  -      -    
+  REG_NW_10GBE_ETH10G                       1     1     REG    tx_snk_out_xon                            0x00043248       1     RO       uint32      b[0:0]           -  -      -    
+  -                                         -     -     -      xgmii_tx_ready                            0x00043248       1     RO       uint32      b[1:1]           -  -      -    
+  -                                         -     -     -      xgmii_link_status                         0x00043248       1     RO       uint32      b[3:2]           -  -      -    
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
index 0cb79ffa8d282485cbfc55251f525e82e892af25..bbbc8a82eef50ed16480476f7e03f31e83dc0e42 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
@@ -68,13 +68,22 @@ ENTITY lofar2_unb2c_sdp_station_full IS
     -- Transceiver clocks
     SA_CLK        : IN    STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
 
-    -- front transceivers
-    QSFP_1_RX     : IN    STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-    QSFP_1_TX     : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
+    -- front transceivers QSFP0 for Ring.
+    QSFP_0_RX     : IN    STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+    QSFP_0_TX     : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
 
+    -- front transceivers QSFP1 for 10GbE output to CEP.
+    QSFP_1_RX     : IN    STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+    QSFP_1_TX     : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
     -- LEDs
     QSFP_LED     : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
 
+    -- ring transceivers
+    RING_0_RX    : IN    STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces
+    RING_0_TX    : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
+    RING_1_RX    : IN    STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+    RING_1_TX    : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
+
      -- back transceivers (note only 12 are used in unb2c)
     BCK_RX       : IN    STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b-1 DOWNTO 0);  -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
     BCK_REF_CLK  : IN    STD_LOGIC; -- Use as JESD204B_REFCLK
@@ -130,13 +139,22 @@ BEGIN
     -- Transceiver clocks
     SA_CLK       => SA_CLK,
 
-    -- front transceivers
+    -- front transceivers QSFP0 for Ring.
+    QSFP_0_RX    => QSFP_0_RX,   
+    QSFP_0_TX    => QSFP_0_TX,   
+
+    -- front transceivers QSFP1 for 10GbE output to CEP.
     QSFP_1_RX    => QSFP_1_RX, 
     QSFP_1_TX    => QSFP_1_TX,
-
     -- LEDs
     QSFP_LED     => QSFP_LED,
 
+    -- ring transceivers
+    RING_0_RX    => RING_0_RX,
+    RING_0_TX    => RING_0_TX,
+    RING_1_RX    => RING_1_RX,
+    RING_1_TX    => RING_1_TX,
+
     -- back transceivers
     JESD204B_SERIAL_DATA   => JESD204B_SERIAL_DATA,
     JESD204B_REFCLK        => JESD204B_REFCLK,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
index 4096edca0155055493049fae3e62864dba5ab5d2..1cf8f2d16ef84f2aaa5a4cb31ae35ef44100b90c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
@@ -45,7 +45,7 @@ PACKAGE lofar2_unb2c_sdp_station_pkg IS
   CONSTANT c_bf        : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE,  TRUE,  FALSE, FALSE, 0);
   CONSTANT c_xsub_one  : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE,  FALSE, TRUE,  FALSE, 1);
   CONSTANT c_xsub_ring : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE,  FALSE, TRUE,  TRUE,  9);
-  CONSTANT c_full      : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE,  TRUE,  TRUE,  FALSE, 1);
+  CONSTANT c_full      : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE,  TRUE,  TRUE,  TRUE,  9);
   
   -- Function to select the revision configuration. 
   FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2c_sdp_station_config;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index ec61c554e1d9224213f550744994132598d0feea..11f71912060c66fd2d324bd4a0530a103d6b1738 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -258,7 +258,7 @@ END ctrl_unb2b_board;
 
 ARCHITECTURE str OF ctrl_unb2b_board IS
 
-  CONSTANT c_rom_version : NATURAL := 2; -- Only increment when something changes to the register map of rom_system_info. 
+  CONSTANT c_rom_version : NATURAL := 3; -- Only increment when something changes to the register map of rom_system_info. 
 
   CONSTANT c_reset_len   : NATURAL := 4;  -- >= c_meta_delay_len from common_pkg
   CONSTANT c_mm_clk_freq : NATURAL := sel_a_b(g_sim=FALSE,g_mm_clk_freq,c_unb2b_board_mm_clk_freq_10M);
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index 105a8f3b95a2d81afb8253ca857262316c2b60ab..20c4278e6951dfa1f2b727784a5ee751ebf87523 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -241,7 +241,7 @@ END ctrl_unb2c_board;
 
 ARCHITECTURE str OF ctrl_unb2c_board IS
 
-  CONSTANT c_rom_version : NATURAL := 2; -- Only increment when something changes to the register map of rom_system_info. 
+  CONSTANT c_rom_version : NATURAL := 3; -- Only increment when something changes to the register map of rom_system_info. 
 
   CONSTANT c_reset_len   : NATURAL := 4;  -- >= c_meta_delay_len from common_pkg
   CONSTANT c_mm_clk_freq : NATURAL := sel_a_b(g_sim=FALSE,g_mm_clk_freq,c_unb2c_board_mm_clk_freq_10M);
diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
index 6a8deef3b0251bc4dc8d5a8401c9b93e470c8ff9..22c74c8f3c500407dc23967c1eb4e18e1388e999 100644
--- a/libraries/base/common/hdllib.cfg
+++ b/libraries/base/common/hdllib.cfg
@@ -45,6 +45,7 @@ synth_files =
     src/vhdl/common_ddio_in.vhd
     src/vhdl/common_ddio_out.vhd
     
+    src/vhdl/common_create_strobes_from_valid.vhd
     src/vhdl/common_wideband_data_scope.vhd
     src/vhdl/common_iobuf_in.vhd
     #$UNB/Firmware/modules/common/src/vhdl/common_iobuf_in_a_stratix4.vhd
@@ -195,7 +196,8 @@ test_bench_files =
     tb/vhdl/tb_common_to_sreal.vhd
     tb/vhdl/tb_delta_cycle_demo.vhd
     tb/vhdl/tb_mms_common_variable_delay.vhd
-    
+    tb/vhdl/tb_common_create_strobes_from_valid.vhd
+
     tb/vhdl/tb_tb_resize.vhd
     tb/vhdl/tb_tb_round.vhd
     tb/vhdl/tb_tb_common_add_sub.vhd
@@ -209,6 +211,7 @@ test_bench_files =
     tb/vhdl/tb_tb_common_rl.vhd
     tb/vhdl/tb_tb_common_rl_register.vhd
     tb/vhdl/tb_tb_common_transpose.vhd
+    tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
 
 regression_test_vhdl = 
     tb/vhdl/tb_common_fifo_rd.vhd
@@ -236,7 +239,8 @@ regression_test_vhdl =
     tb/vhdl/tb_tb_common_rl.vhd
     tb/vhdl/tb_tb_common_rl_register.vhd
     tb/vhdl/tb_tb_common_transpose.vhd
-    
+    tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
+
 [modelsim_project_file]
 modelsim_copy_files =
     data data
diff --git a/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd b/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2474c75da3e6754b73419668b1d3d4e04bec78d4
--- /dev/null
+++ b/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
@@ -0,0 +1,160 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Eric Kooistra
+-- Purpose: Create sync interval by counting input valids
+-- Description:
+--
+--  The first out_sync is created at the first inval after rst release. The
+--  subsequent out_sync are created every m in_val, at the start of a block.
+--
+--    n = g_nof_clk_per_block
+--    m = g_nof_clk_per_sync
+--                _____________________________________________________
+--    in_val   __|
+--
+--    blk_cnt    |    0    |    1    |    2    |    3    |    4    |
+--
+--    val_cnt    |0        |n        |n*2      |n*3 - m  |         |0
+--                _                       _                         _
+--    out_sync __| |_____________________| |_______________________| |_
+--                _____________________________________________________
+--    out_val  __|
+--                _         _         _         _         _         _
+--    out_sop  __| |_______| |_______| |_______| |_______| |_______| |_
+--                        _         _         _         _         _
+--    out_eop  __________| |_______| |_______| |_______| |_______| |___
+--
+-- Remark:
+-- . Use VHDL coding template from:
+--   https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
+-- . The out_sop and out_eop are created as well, for reference.
+-- . The out_sync1 for LOFAR1 style is only avaiable if g_pipeline = TRUE,
+--   because the pipeline is needed to let the out_sync1 preceed the
+--   out_sop and other strobes.
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE work.common_pkg.ALL;
+
+ENTITY common_create_strobes_from_valid IS
+  GENERIC (
+    g_pipeline           : BOOLEAN := TRUE;
+    g_nof_clk_per_sync   : NATURAL := 200*10**6;
+    g_nof_clk_per_block  : NATURAL := 1024
+  );
+  PORT (
+    rst       : IN  STD_LOGIC := '0';
+    clk       : IN  STD_LOGIC;
+    in_val    : IN  STD_LOGIC;
+    out_val   : OUT STD_LOGIC;
+    out_sop   : OUT STD_LOGIC;
+    out_eop   : OUT STD_LOGIC;
+    out_sync  : OUT STD_LOGIC;  -- DP style: sync at sop
+    out_sync1 : OUT STD_LOGIC   -- LOFAR1 style: sync before sop
+  );
+END common_create_strobes_from_valid;
+
+
+ARCHITECTURE rtl OF common_create_strobes_from_valid IS
+
+  TYPE t_state IS RECORD  -- function state registers
+    val_cnt : NATURAL RANGE 0 TO g_nof_clk_per_sync-1;
+    blk_cnt : NATURAL RANGE 0 TO g_nof_clk_per_block-1;
+  END RECORD;
+
+  TYPE t_outputs IS RECORD  -- copy of entity outputs
+    out_val  : STD_LOGIC;
+    out_sop  : STD_LOGIC;
+    out_eop  : STD_LOGIC;
+    out_sync : STD_LOGIC;
+  END RECORD;
+
+  CONSTANT c_state_rst   : t_state := (val_cnt => 0, blk_cnt => 0);
+  CONSTANT c_outputs_rst : t_outputs := ('0', '0', '0', '0');
+
+  SIGNAL q : t_state := c_state_rst;  -- stored state with latency one
+  SIGNAL d : t_state := c_state_rst;  -- zero latency state
+
+  SIGNAL o : t_outputs := c_outputs_rst;  -- zero latency outputs
+  SIGNAL p : t_outputs := c_outputs_rst;  -- pipelined outputs
+
+BEGIN
+
+  -- p_state
+  q <= d WHEN rising_edge(clk);
+
+  p_comb : PROCESS(rst, q, in_val)
+    VARIABLE v : t_state;
+  BEGIN
+    -- Default
+    v := q;
+    o.out_val <= in_val;
+    o.out_sop <= '0';
+    o.out_eop <= '0';
+    o.out_sync <= '0';
+
+    -- Function
+    IF in_val = '1' THEN
+      -- maintain in_val counters
+      IF q.val_cnt >= g_nof_clk_per_sync-1 THEN
+        v.val_cnt := 0;
+      ELSE
+        v.val_cnt := v.val_cnt + 1;
+      END IF;
+      IF q.blk_cnt >= g_nof_clk_per_block-1 THEN
+        v.blk_cnt := 0;
+      ELSE
+        v.blk_cnt := v.blk_cnt + 1;
+      END IF;
+      -- create out_sop at start of block
+      IF q.blk_cnt = 0 THEN
+        o.out_sop <= '1';
+      END IF;
+      -- create out_eop at end of block
+      IF q.blk_cnt = g_nof_clk_per_block-1 THEN
+        o.out_eop <= '1';
+      END IF;
+      -- create out_sync at start of first block of sync interval
+      IF q.blk_cnt = 0 AND q.val_cnt < g_nof_clk_per_block THEN
+        o.out_sync <= '1';
+      END IF;
+    END IF;
+
+    -- Reset
+    IF rst = '1' THEN
+      v := c_state_rst;
+    END IF;
+
+    -- Result
+    d <= v;
+
+  END PROCESS;
+
+  -- Output
+  p <= o WHEN rising_edge(clk);
+
+  out_val  <= o.out_val  WHEN g_pipeline = FALSE ELSE p.out_val;
+  out_sop  <= o.out_sop  WHEN g_pipeline = FALSE ELSE p.out_sop;
+  out_eop  <= o.out_eop  WHEN g_pipeline = FALSE ELSE p.out_eop;
+  out_sync <= o.out_sync WHEN g_pipeline = FALSE ELSE p.out_sync;
+
+  out_sync1 <= '0' WHEN g_pipeline = FALSE ELSE o.out_sync;
+
+END rtl;
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 791cfb39682d6e1fd94b0469e18c4d6582ae0e1d..6153caf04a8c55f7cfdb2b77674b7407161229a4 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -2177,9 +2177,8 @@ PACKAGE BODY common_pkg IS
   END;
   
   FUNCTION INCR_SVEC(vec : STD_LOGIC_VECTOR; dec : INTEGER) RETURN STD_LOGIC_VECTOR IS
-    VARIABLE v_dec : INTEGER;
   BEGIN
-    RETURN STD_LOGIC_VECTOR(SIGNED(vec) + v_dec);  -- uses function "+" (L : SIGNED, R : INTEGER)
+    RETURN STD_LOGIC_VECTOR(SIGNED(vec) + dec);  -- uses function "+" (L : SIGNED, R : INTEGER)
   END;
 
   FUNCTION INCR_SVEC(vec : STD_LOGIC_VECTOR; dec : SIGNED) RETURN STD_LOGIC_VECTOR IS   
diff --git a/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd b/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c29143fc533451d52612349f67b33e05fd4d2626
--- /dev/null
+++ b/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
@@ -0,0 +1,142 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Eric Kooistra
+-- Purpose: Self checking and self-stopping tb for common_create_strobes_from_valid.vhd
+-- Usage:
+-- > as 3
+-- > run -a
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE work.common_pkg.ALL;
+USE work.tb_common_pkg.ALL;
+
+ENTITY tb_common_create_strobes_from_valid IS
+  GENERIC (
+    g_pipeline           : BOOLEAN := FALSE;
+    g_in_val_gaps        : BOOLEAN := TRUE;
+    g_nof_clk_per_sync   : NATURAL := 10;
+    g_nof_clk_per_block  : NATURAL := 5
+  );
+END tb_common_create_strobes_from_valid;
+
+ARCHITECTURE tb OF tb_common_create_strobes_from_valid IS
+
+  CONSTANT clk_period     : TIME := 10 ns;
+    
+  CONSTANT c_nof_block_per_sync_max : NATURAL := ceil_div(g_nof_clk_per_sync, g_nof_clk_per_block);
+  CONSTANT c_nof_block_per_sync_min : NATURAL := g_nof_clk_per_sync / g_nof_clk_per_block;
+  CONSTANT c_fractional             : BOOLEAN := c_nof_block_per_sync_min /= c_nof_block_per_sync_max;
+
+  CONSTANT c_nof_sync               : NATURAL := sel_a_b(c_fractional, g_nof_clk_per_block, 1) * 3;
+
+  SIGNAL tb_end      : STD_LOGIC := '0';
+  SIGNAL rst         : STD_LOGIC := '1';
+  SIGNAL clk         : STD_LOGIC := '0';
+  SIGNAL in_val      : STD_LOGIC := '0';
+  SIGNAL out_val     : STD_LOGIC;
+  SIGNAL out_sop     : STD_LOGIC;
+  SIGNAL out_eop     : STD_LOGIC;
+  SIGNAL out_sync    : STD_LOGIC;
+  SIGNAL out_val_cnt : NATURAL := 0;
+
+BEGIN
+
+  clk <= NOT clk OR tb_end AFTER clk_period/2;
+    
+  p_in_stimuli : PROCESS
+  BEGIN
+    rst <= '1';
+    proc_common_wait_some_cycles(clk, 10);
+    rst <= '0';
+    proc_common_wait_some_cycles(clk, 10);
+    FOR I IN 0 TO c_nof_sync-1 LOOP
+      FOR J IN 0 TO c_nof_block_per_sync_max-1 LOOP
+        FOR K IN 0 TO g_nof_clk_per_block-1 LOOP
+          IF g_in_val_gaps AND K = 0 THEN
+            in_val <= '0';  -- insert a one cycle gap
+            proc_common_wait_some_cycles(clk, 1);
+          END IF;
+          in_val <= '1';
+          proc_common_wait_some_cycles(clk, 1);
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    proc_common_wait_some_cycles(clk, g_nof_clk_per_sync*2);
+    tb_end <= '1';
+    WAIT;
+  END PROCESS;
+
+  out_val_cnt <= out_val_cnt + 1 WHEN rising_edge(clk) AND out_val = '1';
+
+  p_verify : PROCESS(clk)
+  BEGIN
+    IF rising_edge(clk) THEN
+      IF out_val = '1' THEN
+        -- Verify out_eop
+        IF out_val_cnt MOD g_nof_clk_per_block = g_nof_clk_per_block-1 THEN
+          ASSERT out_eop = '1' REPORT "Missing out_eop." SEVERITY ERROR;
+        ELSE
+          ASSERT out_eop = '0' REPORT "Unexpected out_eop." SEVERITY ERROR;
+        END IF;
+
+        -- Verify out_sop
+        IF out_val_cnt MOD g_nof_clk_per_block = 0 THEN
+          ASSERT out_sop = '1' REPORT "Missing out_sop." SEVERITY ERROR;
+        ELSE
+          ASSERT out_sop = '0' REPORT "Unexpected out_sop." SEVERITY ERROR;
+        END IF;
+
+        -- Verify out_sync
+        IF out_val_cnt MOD g_nof_clk_per_block = 0 THEN
+          IF out_val_cnt MOD g_nof_clk_per_sync <= g_nof_clk_per_block-1 THEN
+            ASSERT out_sync = '1' REPORT "Missing out_sync." SEVERITY ERROR;
+          ELSE
+            ASSERT out_sync = '0' REPORT "Unexpected out_sync." SEVERITY ERROR;
+          END IF;
+        ELSE
+          ASSERT out_sync = '0' REPORT "Unexpected out_sync." SEVERITY ERROR;
+        END IF;
+      ELSE
+        -- Illegal strobe when out_val = '0'
+        ASSERT out_eop = '0' REPORT "Illegal out_eop." SEVERITY ERROR;
+        ASSERT out_sop = '0' REPORT "Illegal out_sop." SEVERITY ERROR;
+        ASSERT out_sync = '0' REPORT "Illegal out_sync." SEVERITY ERROR;
+      END IF;
+    END IF;
+  END PROCESS;
+
+  u_in_sync : ENTITY work.common_create_strobes_from_valid
+  GENERIC MAP (
+    g_pipeline          => g_pipeline,
+    g_nof_clk_per_sync  => g_nof_clk_per_sync,
+    g_nof_clk_per_block => g_nof_clk_per_block
+  )
+  PORT MAP (
+    rst      => rst,
+    clk      => clk,
+    in_val   => in_val,
+    out_val  => out_val,
+    out_sop  => out_sop,
+    out_eop  => out_eop,
+    out_sync => out_sync
+  );
+
+END tb;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..78ddd2e363d5b6171087eacc372db0a557b6a2ce
--- /dev/null
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
@@ -0,0 +1,48 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Eric Kooistra
+-- Purpose: Multi tb for common_create_strobes_from_valid.vhd
+-- Usage:
+-- > as 3
+-- > run -a
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY tb_tb_common_create_strobes_from_valid IS
+END tb_tb_common_create_strobes_from_valid;
+
+ARCHITECTURE tb OF tb_tb_common_create_strobes_from_valid IS
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+
+  -- g_pipeline           : BOOLEAN := FALSE;
+  -- g_in_val_gaps        : BOOLEAN := FALSE;
+  -- g_nof_clk_per_sync   : NATURAL := 17;
+  -- g_nof_clk_per_block  : NATURAL := 7
+
+  u_integer_interval                   : ENTITY work.tb_common_create_strobes_from_valid GENERIC MAP (FALSE, FALSE, 10, 5);
+  u_integer_interval_with_gaps         : ENTITY work.tb_common_create_strobes_from_valid GENERIC MAP (FALSE,  TRUE, 10, 5);
+  u_integer_interval_with_gaps_pipe    : ENTITY work.tb_common_create_strobes_from_valid GENERIC MAP ( TRUE,  TRUE, 10, 5);
+  u_fractional_interval                : ENTITY work.tb_common_create_strobes_from_valid GENERIC MAP (FALSE, FALSE, 17, 7);
+  u_fractional_interval_with_gaps      : ENTITY work.tb_common_create_strobes_from_valid GENERIC MAP (FALSE,  TRUE, 17, 7);
+  u_fractional_interval_with_gaps_pipe : ENTITY work.tb_common_create_strobes_from_valid GENERIC MAP ( TRUE,  TRUE, 17, 7);
+
+END tb;
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index 64e18fe4e39c713ae535859a07f67f936db76315..9cca7c30d99b6efd5ea8c17f1b7c3d549c246ff1 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -129,7 +129,6 @@ peripherals:
               address_offset: 1 * MM_BUS_SIZE
               access_mode: RO
 
-
   - peripheral_name: dp_bsn_source    # pi_dp_bsn_source.py
     peripheral_description: "Block Sequence Number (BSN) source for timestamping blocks of data samples."
     parameters:
diff --git a/libraries/dsp/fft/hdllib.cfg b/libraries/dsp/fft/hdllib.cfg
index dc054d8a66804073a951df9d113fbfe6e8300ef7..a75778467bbdea6b49354de1f431115a5b5dd9d8 100644
--- a/libraries/dsp/fft/hdllib.cfg
+++ b/libraries/dsp/fft/hdllib.cfg
@@ -6,7 +6,10 @@ hdl_lib_technology =
 
 synth_files =
     src/vhdl/fft_pkg.vhd 
-    src/vhdl/fft_sepa.vhd 
+    src/vhdl/fft_lfsr.vhd
+    src/vhdl/fft_switch.vhd
+    src/vhdl/fft_unswitch.vhd
+    src/vhdl/fft_sepa.vhd
     src/vhdl/fft_reorder_sepa_pipe.vhd 
     src/vhdl/fft_sepa_wide.vhd 
     src/vhdl/fft_r2_bf_par.vhd
@@ -19,7 +22,8 @@ synth_files =
 test_bench_files = 
     tb/vhdl/tb_fft_pkg.vhd 
     tb/vhdl/tb_fft_functions.vhd 
-    tb/vhdl/tb_fft_sepa.vhd 
+    tb/vhdl/tb_fft_switch.vhd
+    tb/vhdl/tb_fft_sepa.vhd
     tb/vhdl/tb_fft_reorder_sepa_pipe.vhd 
     tb/vhdl/tb_fft_r2_bf_par.vhd 
     tb/vhdl/tb_fft_r2_pipe.vhd 
@@ -33,6 +37,7 @@ test_bench_files =
     tb/vhdl/tb_tb_fft_r2_wide.vhd
 
 regression_test_vhdl = 
+    tb/vhdl/tb_fft_switch.vhd
     tb/vhdl/tb_tb_fft_r2_pipe.vhd
     tb/vhdl/tb_tb_fft_r2_par.vhd
     tb/vhdl/tb_tb_fft_r2_wide.vhd
diff --git a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..56f5b5e453f9a2e009a05c2418f6890ee6aa22e3
--- /dev/null
+++ b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
@@ -0,0 +1,92 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+--
+-- Author: ported by E. Kooistra, original 2004 by W. Lubberhuizen / W. Poeisz
+-- Purpose: Scramble quantization noise crosstalk between two real inputs
+-- Description: Ported from LOFAR1, see readme_lofar1.txt
+-- Remark: Copy from applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY fft_lfsr IS
+  PORT (
+    in_en          : IN  STD_LOGIC;
+    out_bit1       : OUT STD_LOGIC;
+    out_bit2       : OUT STD_LOGIC;
+    clk            : IN  STD_LOGIC;
+    rst            : IN  STD_LOGIC
+  );
+END fft_lfsr;
+
+
+ARCHITECTURE rtl OF fft_lfsr IS
+  
+  -- uses preferred pair of pritive trinomials
+  -- x^41 + x^20 + 1  and x^41 + x^3 + 1  
+  -- see XAPP217
+  
+  CONSTANT c_max : NATURAL := 41;
+  CONSTANT c1    : NATURAL := 20;
+  CONSTANT c2    : NATURAL := 3;  
+    
+  SIGNAL s1      : STD_LOGIC_VECTOR(c_max-1 DOWNTO 0);
+  SIGNAL nxt_s1  : STD_LOGIC_VECTOR(c_max-1 DOWNTO 0);
+  
+  SIGNAL s2      : STD_LOGIC_VECTOR(c_max-1 DOWNTO 0);
+  SIGNAL nxt_s2  : STD_LOGIC_VECTOR(c_max-1 DOWNTO 0);
+  
+  
+BEGIN
+  p_reg : PROCESS(rst,clk)
+  BEGIN
+    IF rst='1' THEN
+      s1 <= "01000101011101110101001011111000101100001";
+      s2 <= "11011001000101001011011001110101100101100";
+    ELSIF rising_edge(clk) THEN
+      s1 <= nxt_s1;      
+      s2 <= nxt_s2;      
+    END IF;
+  END PROCESS;
+  
+  out_bit1 <= s1(s1'HIGH); 
+  out_bit2 <= s2(s2'HIGH);      
+  
+  p_seed : PROCESS(in_en,s1,s2)
+  BEGIN
+    nxt_s1 <= s1;    
+    nxt_s2 <= s2;    
+    IF in_en='1' THEN
+      -- shift      
+      nxt_s1(c_max-1 DOWNTO 1) <= s1(c_max-2 DOWNTO 0);      
+      nxt_s2(c_max-1 DOWNTO 1) <= s2(c_max-2 DOWNTO 0);      
+      
+      -- feedback 1
+      nxt_s1(0) <= s1(c_max-1);
+      nxt_s2(0) <= s2(c_max-1);
+      
+      -- feedback 2
+      nxt_s1(c1) <= s1(c_max-1) xor s1(c1-1);
+      nxt_s2(c2) <= s2(c_max-1) xor s2(c2-1);
+    END IF;
+  END PROCESS;
+
+end rtl;
+
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
index 317095e9c7782275905d7452814afd6cc8567373..c9ed7f72c558ac588935c3670265363a810f4b5f 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
@@ -39,15 +39,22 @@
 --                            an alternating way: A(0), B(0), A(1), B(1).... etc
 --
 --
--- Remarks: When g_fft.nof_chan is used the spectrums at the output will be interleaved
---          per spectrum and NOT per sample. So in case g_fft.nof_chan = 1 there will be
---          two multiplexed channels at the input (c0t0 means channel 0, timestamp 0) :
+-- Remarks:
+-- . When g_fft.use_separate = TRUE, then the two real inputs are pseudo randomly
+--   multiplied by +1 or -1 every block of input samples in fft_switch. At the
+--   FFT output this is undone by fft_unswitch. In this way any crosstalk due
+--   to quantization noise between the two real inputs gets scrambled and thus
+--   averages to zero when integrated over multiple blocks.
+--
+-- . When g_fft.nof_chan is used the spectrums at the output will be interleaved
+--   per spectrum and NOT per sample. So in case g_fft.nof_chan = 1 there will be
+--   two multiplexed channels at the input (c0t0 means channel 0, timestamp 0) :
 --         
---          c0t0 c1t0s c0t1 c1t1 c0t2 c1t2 ... c0t15 c1t15 
+--     c0t0 c1t0s c0t1 c1t1 c0t2 c1t2 ... c0t15 c1t15
 --
---          At the output will find: 
+--   At the output will find:
 --
---          c0f0 c0f1 c0f2 ... c0f15 c1f0 c1f1 c1f2 ... c1f15  (c0f0 means channel 0, frequency bin 0)
+--   c0f0 c0f1 c0f2 ... c0f15 c1f0 c1f1 c1f2 ... c1f15  (c0f0 means channel 0, frequency bin 0)
 --
 --           
 
@@ -81,18 +88,30 @@ architecture str of fft_r2_pipe is
 
   constant c_pipeline_remove_lsb : natural := 0;
   
+  constant c_switch_en          : boolean := g_fft.use_separate;  -- default do apply switch/unswitch per real input to mitigate quantization crosstalk
+  constant c_switch_sz_w        : natural := ceil_log2(g_fft.nof_points) + g_fft.nof_chan;
+  constant c_switch_dat_w       : natural := g_fft.in_dat_w + 1;  -- add 1 extra bit to fit negation of most negative value per real input switch function
+  constant c_unswitch_dat_w     : natural := g_fft.out_dat_w;  -- no need for extra bit, because most negative value cannot occur in output
   constant c_nof_stages         : natural := ceil_log2(g_fft.nof_points);
   constant c_stage_offset       : natural := true_log2(g_fft.wb_factor);                         -- Stage offset is required for twiddle generation in wideband fft
   constant c_in_scale_w         : natural := g_fft.stage_dat_w - g_fft.in_dat_w - sel_a_b(g_fft.guard_enable, g_fft.guard_w, 0);              
   constant c_out_scale_w        : integer := g_fft.stage_dat_w - g_fft.out_dat_w - g_fft.out_gain_w;  -- Estimate number of LSBs to throw throw away when > 0 or insert when < 0
   constant c_raw_dat_extra_w    : natural := sel_a_b(g_fft.use_separate, g_sepa_extra_w, 0);
   constant c_raw_dat_w          : natural := g_fft.stage_dat_w + c_raw_dat_extra_w;
-  
+
   -- number the stage instances from c_nof_stages:1
   -- . the data input for the first stage has index c_nof_stages
   -- . the data output of the last stage has index 0
   type t_data_arr is array(c_nof_stages downto 0) of std_logic_vector(g_fft.stage_dat_w-1 downto 0);
 
+  signal in_dat_re    : std_logic_vector(c_switch_dat_w-1 downto 0);
+  signal in_dat_im    : std_logic_vector(c_switch_dat_w-1 downto 0);
+  signal in_dat_val   : std_logic;
+
+  signal switch_re    : std_logic_vector(c_switch_dat_w-1 downto 0);
+  signal switch_im    : std_logic_vector(c_switch_dat_w-1 downto 0);
+  signal switch_val   : std_logic;
+
   signal data_re      : t_data_arr;
   signal data_im      : t_data_arr;
   signal last_re      : std_logic_vector(c_raw_dat_w-1 downto 0);
@@ -105,13 +124,43 @@ architecture str of fft_r2_pipe is
   signal raw_out_im   : std_logic_vector(c_raw_dat_w-1 downto 0);
   signal raw_out_val  : std_logic;
 
+  signal quant_re     : std_logic_vector(g_fft.out_dat_w-1 downto 0);
+  signal quant_im     : std_logic_vector(g_fft.out_dat_w-1 downto 0);
+  signal quant_val    : std_logic;
+
 begin
  
+  ------------------------------------------------------------------------------
+  -- Mitigate quantization noise crosstalk between two real inputs by negating
+  -- the inputs per lock in a random pattern, when g_fft.use_separate = TRUE.
+  ------------------------------------------------------------------------------
+
   -- Inputs
-  data_re( c_nof_stages) <= scale_and_resize_svec(in_re, c_in_scale_w, g_fft.stage_dat_w);
-  data_im( c_nof_stages) <= scale_and_resize_svec(in_im, c_in_scale_w, g_fft.stage_dat_w);
-  data_val(c_nof_stages) <= in_val;
-  
+  in_dat_re  <= RESIZE_SVEC(in_re, c_switch_dat_w);
+  in_dat_im  <= RESIZE_SVEC(in_im, c_switch_dat_w);
+  in_dat_val <= in_val;
+
+  u_switch : ENTITY work.fft_switch
+  GENERIC MAP (
+    g_switch_en => c_switch_en,
+    g_fft_sz_w  => c_switch_sz_w,
+    g_dat_w     => c_switch_dat_w
+  )
+  PORT MAP (
+    in_re      => in_dat_re,
+    in_im      => in_dat_im,
+    in_val     => in_dat_val,
+    out_re     => switch_re,
+    out_im     => switch_im,
+    out_val    => switch_val,
+    clk        => clk,
+    rst        => rst
+  );
+
+  data_re( c_nof_stages) <= scale_and_resize_svec(switch_re, c_in_scale_w, g_fft.stage_dat_w);
+  data_im( c_nof_stages) <= scale_and_resize_svec(switch_im, c_in_scale_w, g_fft.stage_dat_w);
+  data_val(c_nof_stages) <= switch_val;
+
   ------------------------------------------------------------------------------
   -- pipelined FFT stages
   ------------------------------------------------------------------------------
@@ -155,12 +204,11 @@ begin
     in_re     => data_re(1),
     in_im     => data_im(1),
     in_val    => data_val(1),
-    out_re    => last_re,
-    out_im    => last_im,
+    out_re    => last_re,  -- = data_re(0), but may instead have c_raw_dat_w bits
+    out_im    => last_im,  -- = data_im(0), but may instead have c_raw_dat_w bits
     out_val   => data_val(0)
   );
 
-
   ------------------------------------------------------------------------------
   -- Optional output reorder and separation
   ------------------------------------------------------------------------------
@@ -190,7 +238,7 @@ begin
    
   end generate;
   
-  no_reorder_no_generate : if(g_fft.use_separate=false and g_fft.use_reorder=false) generate 
+  no_reorder_no_seperate : if(g_fft.use_separate=false and g_fft.use_reorder=false) generate
     raw_out_re  <= last_re;
     raw_out_im  <= last_im;
     raw_out_val <= data_val(0);
@@ -215,7 +263,7 @@ begin
   port map (
     clk        => clk,
     in_dat     => raw_out_re,
-    out_dat    => out_re, 
+    out_dat    => quant_re,
     out_ovr    => open
   );       
 
@@ -235,7 +283,7 @@ begin
   port map (
     clk        => clk,
     in_dat     => raw_out_im,
-    out_dat    => out_im, 
+    out_dat    => quant_im,
     out_ovr    => open
   );
   
@@ -248,8 +296,26 @@ begin
     rst     => rst,
     clk     => clk,
     in_dat  => raw_out_val,
-    out_dat => out_val
+    out_dat => quant_val
   );
   
+  -- Undo input random negation of u_switch at output when g_fft.use_separate = TRUE
+  u_unswitch : ENTITY work.fft_unswitch
+  GENERIC MAP (
+    g_switch_en => c_switch_en,
+    g_fft_sz_w  => c_switch_sz_w,
+    g_dat_w     => c_unswitch_dat_w
+  )
+  PORT MAP (
+    in_re      => quant_re,
+    in_im      => quant_im,
+    in_val     => quant_val,
+    out_re     => out_re,
+    out_im     => out_im,
+    out_val    => out_val,
+    clk        => clk,
+    rst        => rst
+  );
+
 end str;
 
diff --git a/libraries/dsp/fft/src/vhdl/fft_switch.vhd b/libraries/dsp/fft/src/vhdl/fft_switch.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cad57405ab3b2c03ed84834171fab082b2ed6b51
--- /dev/null
+++ b/libraries/dsp/fft/src/vhdl/fft_switch.vhd
@@ -0,0 +1,168 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+--
+-- Author: ported by E. Kooistra, original 2004 by W. Lubberhuizen / W. Poeisz
+-- Purpose: Scramble quantization noise crosstalk between two real inputs
+-- Description:
+-- . Ported from LOFAR1, see readme_lofar1.txt
+-- . The fft_switch multiplies the samples from two real inputs A and B in a
+--   block by +1 or -1. The fft_unswitch undoes this by multiplying the FFT
+--   output again by +1 and -1. The fft_unswitch takes account of that the FFT
+--   has time mutliplexed the two spectra of the two inputs.
+-- . The input switching is pseudo random base on a LFSR (linear feedback
+--   shift register) sequence. The fft_switch and fft_unswitch start at the
+--   first in_val = '1' and then continue 'forever' until a next power cycle
+--   by rst ='1'.
+-- Remark:
+-- . Copy from applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
+-- . Removed in_sync, because the in_val are guaranteed to arrive in blocks of
+--   c_nof_clk_per_block samples, forever after rst release.
+--   The purpose of  the in_sync is to recover from an fractional input block,
+--   but that cannot occur. The other parts of the FFT also rely on this block
+--   processing, without need for in_sync to recover from fractional blocks.
+--   The application that uses the FFT must guarantee to only pass on complete
+--   blocks of c_nof_clk_per_block samples to the FFT.
+-- . The two real inputs each use another LFSR sequence, like for LOFAR1.
+--   For the crosstalk mitigation purpose scrambling only one input would be
+--   enough, but scrambling both inputs is fine too.
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+ENTITY fft_switch IS
+  GENERIC (
+    g_switch_en : BOOLEAN := FALSE;
+    g_fft_sz_w  : NATURAL;
+    g_dat_w     : NATURAL
+  );
+  PORT (
+    in_re       : IN  STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);  -- real input A
+    in_im       : IN  STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);  -- real input B
+    in_val      : IN  STD_LOGIC;
+    out_re      : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+    out_im      : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+    out_val     : OUT STD_LOGIC;
+    clk         : IN  STD_LOGIC;
+    rst         : IN  STD_LOGIC
+  );
+END fft_switch;
+
+
+ARCHITECTURE rtl OF fft_switch IS
+
+  CONSTANT c_nof_clk_per_block  : NATURAL := 2**g_fft_sz_w;
+
+  SIGNAL in_sop        : STD_LOGIC;
+  SIGNAL in_eop        : STD_LOGIC;
+
+  SIGNAL cnt           : STD_LOGIC_VECTOR(g_fft_sz_w DOWNTO 0) := (OTHERS => '0');
+  SIGNAL nxt_cnt       : STD_LOGIC_VECTOR(cnt'RANGE);
+
+  SIGNAL lfsr_bit1     : STD_LOGIC;
+  SIGNAL lfsr_bit2     : STD_LOGIC;
+  SIGNAL lfsr_en       : STD_LOGIC;
+
+  SIGNAL nxt_out_re    : STD_LOGIC_VECTOR(in_re'RANGE);
+  SIGNAL nxt_out_im    : STD_LOGIC_VECTOR(in_im'RANGE);
+
+BEGIN
+
+  -- Create input strobes to view data blocks for debugging
+  u_in_strobes : ENTITY common_lib.common_create_strobes_from_valid
+  GENERIC MAP (
+    g_pipeline          => FALSE,
+    g_nof_clk_per_sync  => c_nof_clk_per_block * 16,  -- void value, sync is not used
+    g_nof_clk_per_block => c_nof_clk_per_block
+  )
+  PORT MAP (
+    rst       => rst,
+    clk       => clk,
+    in_val    => in_val,
+    out_val   => OPEN,  -- out_val = in_val, because g_pipeline = FALSE
+    out_sop   => in_sop,
+    out_eop   => in_eop,
+    out_sync  => OPEN
+  );
+
+  no_switch : IF g_switch_en = FALSE GENERATE
+    -- wire inputs to outputs
+    out_re <= in_re;
+    out_im <= in_im;
+    out_val <= in_val;
+  END GENERATE;
+
+  gen_switch : IF g_switch_en = TRUE GENERATE
+    p_reg : PROCESS (rst, clk)
+    BEGIN
+      IF rst = '1' THEN
+        cnt       <= (OTHERS => '0');
+        out_val   <= '0';
+        out_re    <= (OTHERS => '0');
+        out_im    <= (OTHERS => '0');
+      ELSIF rising_edge(clk) THEN
+        cnt       <= nxt_cnt;
+        out_val   <= in_val;
+        out_re    <= nxt_out_re;
+        out_im    <= nxt_out_im;
+      END IF;
+    END PROCESS;
+
+    p_counter: PROCESS(cnt, in_val)
+    BEGIN
+      nxt_cnt <= cnt;
+      IF in_val = '1' THEN
+        nxt_cnt <= INCR_UVEC(cnt, 1);
+      END IF;
+    END PROCESS;
+
+    p_lfsr_ctrl: PROCESS(cnt, in_val)
+    BEGIN
+      if TO_SINT(cnt) = -1 AND in_val = '1' THEN
+        lfsr_en <= '1';
+      ELSE
+        lfsr_en <= '0';
+      END IF;
+    END PROCESS;
+
+    p_out: PROCESS(in_re, in_im, cnt, lfsr_bit1, lfsr_bit2)
+    BEGIN
+      nxt_out_re <= in_re;
+      nxt_out_im <= in_im;
+
+      IF lfsr_bit1 = cnt(cnt'HIGH) THEN
+        nxt_out_re <= NEGATE_SVEC(in_re, g_dat_w);  -- negate block of input A samples
+      END IF;
+      IF lfsr_bit2 = cnt(cnt'HIGH) THEN
+        nxt_out_im <= NEGATE_SVEC(in_im, g_dat_w);  -- negate block of input B samples
+      END IF;
+    END PROCESS;
+
+    u_fft_lfsr: ENTITY work.fft_lfsr
+    PORT MAP (
+      clk      => clk,
+      rst      => rst,
+      in_en    => lfsr_en,
+      out_bit1 => lfsr_bit1,
+      out_bit2 => lfsr_bit2
+    );
+  END GENERATE;
+
+END rtl;
diff --git a/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd b/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6d9f561a15e7ca184f70c418810bd85f9b1ac6d6
--- /dev/null
+++ b/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
@@ -0,0 +1,159 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+--
+-- Author: ported by E. Kooistra, original 2004 by W. Lubberhuizen / W. Poeisz
+-- Purpose: Scramble quantization noise crosstalk between two real inputs
+-- Description:
+-- . Ported from LOFAR1, see readme_lofar1.txt
+-- . See fft_switch.vhd
+-- Remark:
+-- . Copy from applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
+-- . Removed in_sync, because the in_val are guaranteed to arrive in blocks of
+--   c_nof_clk_per_block samples, forever after rst release.
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+ENTITY fft_unswitch IS
+  GENERIC (
+    g_switch_en : BOOLEAN := FALSE;
+    g_fft_sz_w  : NATURAL;
+    g_dat_w     : NATURAL
+  );
+  PORT (
+    in_re       : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+    in_im       : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+    in_val      : IN STD_LOGIC;
+    out_re      : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+    out_im      : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+    out_val     : OUT STD_LOGIC;
+    clk         : IN STD_LOGIC;
+    rst         : IN STD_LOGIC
+  );
+END fft_unswitch;
+
+ARCHITECTURE rtl OF fft_unswitch IS
+
+  CONSTANT c_nof_clk_per_block  : NATURAL := 2**g_fft_sz_w;
+
+  SIGNAL in_sop        : STD_LOGIC;
+  SIGNAL in_eop        : STD_LOGIC;
+
+  SIGNAL cnt           : STD_LOGIC_VECTOR(g_fft_sz_w DOWNTO 0) := (OTHERS => '0');
+  SIGNAL nxt_cnt       : STD_LOGIC_VECTOR(cnt'RANGE);
+
+  SIGNAL lfsr_bit1     : STD_LOGIC;
+  SIGNAL lfsr_bit2     : STD_LOGIC;
+
+  SIGNAL lfsr_en       : STD_LOGIC;
+
+  SIGNAL nxt_out_re    : STD_LOGIC_VECTOR(in_re'RANGE);
+  SIGNAL nxt_out_im    : STD_LOGIC_VECTOR(in_im'RANGE);
+
+BEGIN
+
+  -- Create input strobes to view data blocks for debugging
+  u_in_strobes : ENTITY common_lib.common_create_strobes_from_valid
+  GENERIC MAP (
+    g_pipeline          => FALSE,
+    g_nof_clk_per_sync  => c_nof_clk_per_block * 16,  -- void value, sync is not used
+    g_nof_clk_per_block => c_nof_clk_per_block
+  )
+  PORT MAP (
+    rst       => rst,
+    clk       => clk,
+    in_val    => in_val,
+    out_val   => OPEN,  -- out_val = in_val, because g_pipeline = FALSE
+    out_sop   => in_sop,
+    out_eop   => in_eop,
+    out_sync  => OPEN
+  );
+
+  no_switch : IF g_switch_en = FALSE GENERATE
+    -- wire inputs to outputs
+    out_re <= in_re;
+    out_im <= in_im;
+    out_val <= in_val;
+  END GENERATE;
+
+  gen_switch : IF g_switch_en = TRUE GENERATE
+    p_reg : PROCESS (rst, clk)
+    BEGIN
+      IF rst = '1' THEN
+        cnt       <= (OTHERS => '0');
+        out_val   <= '0';
+        out_re    <= (OTHERS => '0');
+        out_im    <= (OTHERS => '0');
+      ELSIF rising_edge(clk) THEN
+        cnt       <= nxt_cnt;
+        out_val   <= in_val;
+        out_re    <= nxt_out_re;
+        out_im    <= nxt_out_im;
+      END IF;
+    END PROCESS;
+
+    p_counter: PROCESS(cnt, in_val)
+    BEGIN
+      nxt_cnt <= cnt;
+      IF in_val = '1' THEN
+        nxt_cnt <= INCR_UVEC(cnt, 1);
+      END IF;
+    END PROCESS;
+
+    p_lfsr_ctrl: PROCESS(cnt, in_val)
+    BEGIN
+      if TO_SINT(cnt) = -1 AND in_val = '1' THEN
+        lfsr_en <= '1';
+      ELSE
+        lfsr_en <= '0';
+      END IF;
+    END PROCESS;
+
+    p_out: PROCESS(in_re, in_im, cnt, lfsr_bit1, lfsr_bit2)
+    BEGIN
+      nxt_out_re  <= in_re;
+      nxt_out_im  <= in_im;
+
+      -- multiplexed spectrum for input A at index 0, B at index 1
+      IF cnt(0) = '0' THEN
+        IF cnt(cnt'HIGH) = lfsr_bit1 THEN  -- negate spectrum to undo negate of block of real input A
+          nxt_out_re <= NEGATE_SVEC(in_re, g_dat_w);
+          nxt_out_im <= NEGATE_SVEC(in_im, g_dat_w);
+        END IF;
+      ELSE
+        IF cnt(cnt'HIGH) = lfsr_bit2 THEN  -- negate spectrum to undo negate of block of real input B
+          nxt_out_re <= NEGATE_SVEC(in_re, g_dat_w);
+          nxt_out_im <= NEGATE_SVEC(in_im, g_dat_w);
+        END IF;
+      END IF;
+    END PROCESS;
+
+    u_fft_lfsr: ENTITY work.fft_lfsr
+    PORT MAP (
+      clk      => clk,
+      rst      => rst,
+      in_en    => lfsr_en,
+      out_bit1 => lfsr_bit1,
+      out_bit2 => lfsr_bit2
+    );
+  END GENERATE;
+
+END rtl;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..08d04ee3e9bae1ffaea762e535be0d38d97395f6
--- /dev/null
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
@@ -0,0 +1,311 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Tb for fft_switch.vhd + fft_unswitch.vhd
+-- Description:
+--
+--  p_in_val --> u_fft_switch --> mux --> u_fft_unswitch --> demux --> p_verify
+--
+--  . p_in_val creates blocks of in_val, with or without g_in_val_gaps
+--  . in_a and in_b are offset counter data that increment at in_val
+--  . fft_switch uses an lfsr per input to randomly negate or keep the input
+--  . mux models that the FFT complex output is multiplexes a, b in time
+--  . fft_unswitch use the same lfsr as fft_switch to undo the random negate
+--    on the multiplexed a, b output
+--  . demux demultiplexes the output so that it can be compared to the delayed
+--    input
+--  . p_verify checks that the output is equal to the delayed input.
+--
+-- Remark:
+-- . The fft_switch and fft_unswitch only use in_val, the other strobes sop,
+--   eop and sync are only for tb debugging purposes to recognize the in_val
+--   data blocks of c_nof_clk_per_block samples in the Wave window.
+-- . The g_increment_at_val determines whether the in_re, in_im increment at
+--   every sample (at in_val), or at every block of samples (at in_eop).
+--   Default use g_increment_at_val = TRUE. Increment at eop is for debugging
+--   purposes.
+--
+-- Usage:
+-- > as 5
+-- > run -a
+-- # view a,b and re,im signals in radix decimal
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_fft_switch IS
+  GENERIC (
+    g_switch_en          : BOOLEAN := TRUE;
+    g_in_val_gaps        : BOOLEAN := TRUE;
+    g_increment_at_val   : BOOLEAN := TRUE;
+    g_fft_size_w         : NATURAL := 3;
+    g_nof_clk_per_sync   : NATURAL := 32;
+    g_nof_sync           : NATURAL := 2
+  );
+END tb_fft_switch;
+
+ARCHITECTURE tb OF tb_fft_switch IS
+
+  CONSTANT clk_period     : TIME := 10 ns;
+
+  CONSTANT c_dat_w        : NATURAL := 16;
+
+  CONSTANT c_nof_clk_per_block      : NATURAL := 2**g_fft_size_w;
+  CONSTANT c_nof_block_per_sync_max : NATURAL := ceil_div(g_nof_clk_per_sync, c_nof_clk_per_block);
+  CONSTANT c_nof_block_per_sync_min : NATURAL := g_nof_clk_per_sync / c_nof_clk_per_block;
+
+  CONSTANT c_dly           : NATURAL := 4;  -- pipeling in fft_switch, mux,  fft_unswitch and demux
+
+  SIGNAL tb_end            : STD_LOGIC := '0';
+  SIGNAL rst               : STD_LOGIC := '1';
+  SIGNAL clk               : STD_LOGIC := '0';
+
+  -- Use fixed input A, B values
+  SIGNAL in_a              : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0) := TO_SVEC(3, c_dat_w);
+  SIGNAL in_b              : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0) := TO_SVEC(13, c_dat_w);
+  SIGNAL in_val            : STD_LOGIC := '0';
+  SIGNAL in_sop            : STD_LOGIC := '0';
+  SIGNAL in_eop            : STD_LOGIC := '0';
+  SIGNAL in_sync           : STD_LOGIC := '0';
+
+  SIGNAL switch_a          : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+  SIGNAL switch_b          : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+  SIGNAL switch_val        : STD_LOGIC;
+  SIGNAL prev1_switch_a    : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+  SIGNAL prev1_switch_b    : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+  SIGNAL prev2_switch_a    : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+  SIGNAL prev2_switch_b    : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+
+  SIGNAL mux_toggle        : STD_LOGIC := '0';
+  SIGNAL mux_re            : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL mux_im            : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL mux_val           : STD_LOGIC := '0';
+
+  SIGNAL unswitch_re       : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+  SIGNAL unswitch_im       : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+  SIGNAL unswitch_val      : STD_LOGIC := '0';
+  SIGNAL prev1_unswitch_re : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+  SIGNAL prev1_unswitch_im : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+  SIGNAL prev2_unswitch_re : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+  SIGNAL prev2_unswitch_im : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+
+  SIGNAL out_toggle        : STD_LOGIC := '0';
+  SIGNAL out_a             : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+  SIGNAL out_b             : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+  SIGNAL out_val           : STD_LOGIC;
+  SIGNAL out_sop           : STD_LOGIC := '0';
+  SIGNAL out_eop           : STD_LOGIC := '0';
+  SIGNAL out_sync          : STD_LOGIC := '0';
+
+  SIGNAL dly_val           : STD_LOGIC_VECTOR(0 TO c_dly) := (OTHERS => '0');
+  SIGNAL dly_a             : t_integer_arr(0 TO c_dly) := (OTHERS => 0);
+  SIGNAL dly_b             : t_integer_arr(0 TO c_dly) := (OTHERS => 0);
+  SIGNAL exp_val           : STD_LOGIC := '0';
+  SIGNAL exp_a             : INTEGER;
+  SIGNAL exp_b             : INTEGER;
+
+  SIGNAL verify_en         : STD_LOGIC := '0';
+
+BEGIN
+
+  clk <= NOT clk OR tb_end AFTER clk_period/2;
+
+  p_in_val : PROCESS
+  BEGIN
+    rst <= '1';
+    in_val <= '0';
+    proc_common_wait_some_cycles(clk, 10);
+    rst <= '0';
+    proc_common_wait_some_cycles(clk, 10);
+    FOR I IN 0 TO g_nof_sync-1 LOOP
+      FOR J IN 0 TO c_nof_block_per_sync_max-1 LOOP
+        FOR K IN 0 TO c_nof_clk_per_block-1 LOOP
+          IF g_in_val_gaps AND K = 0 THEN
+            in_val <= '0';  -- insert a one cycle gap
+            proc_common_wait_some_cycles(clk, 1);
+          END IF;
+          in_val <= '1';
+          proc_common_wait_some_cycles(clk, 1);
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    proc_common_wait_some_cycles(clk, g_nof_clk_per_sync*g_nof_sync);
+    tb_end <= '1';
+    WAIT;
+  END PROCESS;
+
+  -- Create in strobes for debugging
+  u_in_strobes : ENTITY common_lib.common_create_strobes_from_valid
+  GENERIC MAP (
+    g_pipeline          => FALSE,
+    g_nof_clk_per_sync  => g_nof_clk_per_sync,
+    g_nof_clk_per_block => c_nof_clk_per_block
+  )
+  PORT MAP (
+    rst       => rst,
+    clk       => clk,
+    in_val    => in_val,
+    out_val   => OPEN,  -- out_val = in_val, because g_pipeline = FALSE
+    out_sop   => in_sop,
+    out_eop   => in_eop,
+    out_sync  => in_sync
+  );
+
+
+  gen_increment_at_val : IF g_increment_at_val = TRUE GENERATE
+    in_a <= INCR_SVEC(in_a, 1) WHEN rising_edge(clk) AND in_val = '1';
+    in_b <= INCR_SVEC(in_b, 1) WHEN rising_edge(clk) AND in_val = '1';
+  END GENERATE;
+  gen_increment_at_eop : IF g_increment_at_val = FALSE GENERATE
+    in_a <= INCR_SVEC(in_a, 1) WHEN rising_edge(clk) AND in_eop = '1';
+    in_b <= INCR_SVEC(in_b, 1) WHEN rising_edge(clk) AND in_eop = '1';
+  END GENERATE;
+
+
+  u_fft_switch : ENTITY work.fft_switch
+  GENERIC MAP (
+    g_switch_en => g_switch_en,
+    g_fft_sz_w  => g_fft_size_w,
+    g_dat_w     => c_dat_w
+  )
+  PORT MAP (
+    in_re      => in_a,
+    in_im      => in_b,
+    in_val     => in_val,
+    out_re     => switch_a,
+    out_im     => switch_b,
+    out_val    => switch_val,
+    clk        => clk,
+    rst        => rst
+  );
+
+  -- Model A, B multiplexing part of FFT
+  --                   0  1  2 ..  N-1
+  --        switch_a: a0 a1 a2 .. aN-1
+  --        switch_b: b0 b1 b2 .. bN-1
+  --  prev1_switch_a:    a0 a1 ..      aN-1
+  --  prev1_switch_b:    b0 b1 ..      bN-1
+  --  prev2_switch_a:       a0 ..           aN-1
+  --  prev2_switch_b:       b0 ..           bN-1
+  --      mux_toggle:  0  1  0  1  0 ..  1    0
+  --                      0  1  2  3 ..  N-2  N-1
+  --          mux_re:    a0 b0 a2 b2 .. aN-2 bN-2
+  --          mux_im:    a1 b1 a3 b3 .. aN-1 bN-1
+
+  prev1_switch_a <=       switch_a WHEN rising_edge(clk) AND switch_val = '1';
+  prev1_switch_b <=       switch_b WHEN rising_edge(clk) AND switch_val = '1';
+  prev2_switch_a <= prev1_switch_a WHEN rising_edge(clk) AND switch_val = '1';
+  prev2_switch_b <= prev1_switch_b WHEN rising_edge(clk) AND switch_val = '1';
+
+  mux_toggle <= NOT mux_toggle WHEN rising_edge(clk) AND switch_val = '1';
+
+  mux_re  <= prev1_switch_a WHEN mux_toggle = '1' ELSE prev2_switch_b;  -- a0, b0, ..
+  mux_im  <=       switch_a WHEN mux_toggle = '1' ELSE prev1_switch_b;  -- a1, b1, ..
+  mux_val <= switch_val WHEN rising_edge(clk);
+
+
+  u_fft_unswitch : ENTITY work.fft_unswitch
+  GENERIC MAP (
+    g_switch_en => g_switch_en,
+    g_fft_sz_w  => g_fft_size_w,
+    g_dat_w     => c_dat_w
+  )
+  PORT MAP (
+    in_re      => mux_re,
+    in_im      => mux_im,
+    in_val     => mux_val,
+    out_re     => unswitch_re,
+    out_im     => unswitch_im,
+    out_val    => unswitch_val,
+    clk        => clk,
+    rst        => rst
+  );
+
+  -- Demultiplex output to ease verification
+  --                      0  1  2  3 ..  N-2  N-1
+  --        unswitch_re: a0 b0 a2 b2 .. aN-2 bN-2
+  --        unswitch_im: a1 b1 a3 b3 .. aN-1 bN-1
+  --  prev1_unswitch_re:    a0 b0 a2 b2 .. aN-2 bN-2
+  --  prev1_unswitch_im:    a1 b1 a3 b3 .. aN-1 bN-1
+  --  prev2_unswitch_re:       a0 b0 a2 b2 .. aN-2 bN-2
+  --  prev2_unswitch_im:       a1 b1 a3 b3 .. aN-1 bN-1
+  --        out_toggle:   0  1  0  1  0
+  --                         0  1 .. N-1
+  --             out_a:     a0 a1 ..aN-1
+  --             out_b:     b0 b1 ..bN-1
+
+  prev1_unswitch_re <=       unswitch_re WHEN rising_edge(clk) AND unswitch_val = '1';
+  prev1_unswitch_im <=       unswitch_im WHEN rising_edge(clk) AND unswitch_val = '1';
+  prev2_unswitch_re <= prev1_unswitch_re WHEN rising_edge(clk) AND unswitch_val = '1';
+  prev2_unswitch_im <= prev1_unswitch_im WHEN rising_edge(clk) AND unswitch_val = '1';
+
+  out_toggle <= NOT out_toggle WHEN rising_edge(clk) AND unswitch_val = '1';
+
+  out_a     <= prev1_unswitch_re WHEN out_toggle = '1' ELSE prev2_unswitch_im;  -- a0, a1, ..
+  out_b     <=       unswitch_re WHEN out_toggle = '1' ELSE prev1_unswitch_im;  -- b0, b1, ..
+  out_val   <= unswitch_val WHEN rising_edge(clk);
+
+  -- Create out strobes for debugging
+  u_out_strobes : ENTITY common_lib.common_create_strobes_from_valid
+  GENERIC MAP (
+    g_pipeline          => FALSE,
+    g_nof_clk_per_sync  => g_nof_clk_per_sync,
+    g_nof_clk_per_block => c_nof_clk_per_block
+  )
+  PORT MAP (
+    rst       => rst,
+    clk       => clk,
+    in_val    => out_val,
+    out_val   => OPEN,  -- out_val = in_val, because g_pipeline = FALSE
+    out_sop   => out_sop,
+    out_eop   => out_eop,
+    out_sync  => out_sync
+  );
+
+  -- Account for pipeling in fft_switch, mux,  fft_unswitch and demux
+  dly_val(0) <= in_val;
+  dly_a(0) <= TO_SINT(in_a);
+  dly_b(0) <= TO_SINT(in_b);
+  dly_val(1 TO c_dly) <= dly_val(0 TO c_dly-1) WHEN rising_edge(clk);
+  dly_a(1 TO c_dly) <= dly_a(0 TO c_dly-1) WHEN rising_edge(clk);
+  dly_b(1 TO c_dly) <= dly_b(0 TO c_dly-1) WHEN rising_edge(clk);
+  exp_val <= dly_val(c_dly);
+  exp_a <= dly_a(c_dly);
+  exp_b <= dly_b(c_dly);
+
+  verify_en <= '1' WHEN exp_val = '1';
+
+  p_verify : PROCESS(clk)
+  BEGIN
+    IF rising_edge(clk) THEN
+      IF verify_en = '1' THEN
+        IF exp_val = '1' THEN
+          ASSERT TO_SINT(out_a) = exp_a   REPORT "Wrong out_re" SEVERITY ERROR;
+          ASSERT TO_SINT(out_b) = exp_b   REPORT "Wrong out_im" SEVERITY ERROR;
+        END IF;
+        ASSERT out_val        = exp_val REPORT "Wrong out_val" SEVERITY ERROR;
+      END IF;
+    END IF;
+  END PROCESS;
+
+END tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
index 3efd0d0917221ec7c194f8916c34f543a0f8a585..ba5514038feb271e308a479e1a4e1959f447af46 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
@@ -53,6 +53,7 @@ ARCHITECTURE tb OF tb_tb_fft_r2_pipe IS
   -- Real input  
   CONSTANT c_impulse_chirp  : string := "data/run_pfft_m_impulse_chirp_8b_128points_16b.dat";          -- 25600 lines
   CONSTANT c_sinusoid_chirp : string := "data/run_pfft_m_sinusoid_chirp_8b_128points_16b.dat";         -- 25600 lines
+  CONSTANT c_sinusoid       : string := "data/run_pfft_m_sinusoid_8b_128points_16b.dat";               --   640 lines
   CONSTANT c_noise          : string := "data/run_pfft_m_noise_8b_128points_16b.dat";                  --  1280 lines
   CONSTANT c_dc_agwn        : string := "data/run_pfft_m_dc_agwn_8b_128points_16b.dat";                --  1280 lines
   -- Complex input  
@@ -104,9 +105,10 @@ BEGIN
   u_act_two_real_chirp    : ENTITY work.tb_fft_r2_pipe GENERIC MAP (c_fft_two_real,               c_diff_margin, c_sinusoid_chirp, 25600, c_impulse_chirp, 25600, c_unused, 0, 25600, FALSE);
   u_act_two_real_a0       : ENTITY work.tb_fft_r2_pipe GENERIC MAP (c_fft_two_real,               c_diff_margin, c_zero,           25600, c_impulse_chirp, 25600, c_unused, 0,  5120, FALSE);
   u_act_two_real_b0       : ENTITY work.tb_fft_r2_pipe GENERIC MAP (c_fft_two_real,               c_diff_margin, c_sinusoid_chirp, 25600, c_zero,          25600, c_unused, 0,  5120, FALSE);
+  u_act_two_real_sinus    : ENTITY work.tb_fft_r2_pipe GENERIC MAP (c_fft_two_real,               c_diff_margin, c_sinusoid,         640, c_zero,            640, c_unused, 0,   640, FALSE);
   u_rnd_two_real_noise    : ENTITY work.tb_fft_r2_pipe GENERIC MAP (c_fft_two_real,               c_diff_margin, c_noise,           1280, c_dc_agwn,        1280, c_unused, 0,  1280, TRUE);
   u_rnd_two_real_channels : ENTITY work.tb_fft_r2_pipe GENERIC MAP (c_fft_two_real_more_channels, c_diff_margin, c_noise,           1280, c_dc_agwn,        1280, c_unused, 0,  1280, TRUE);
-  
+
   -- Complex input data
   u_act_complex_chirp              : ENTITY work.tb_fft_r2_pipe GENERIC MAP (c_fft_complex,                         c_diff_margin, c_unused, 0, c_unused, 0, c_phasor_chirp,  12800, 12800, FALSE);
   u_act_complex_channels           : ENTITY work.tb_fft_r2_pipe GENERIC MAP (c_fft_complex_more_channels,           c_diff_margin, c_unused, 0, c_unused, 0, c_phasor_chirp,  12800,  1280, FALSE);
diff --git a/libraries/io/eth/src/vhdl/eth_control.vhd b/libraries/io/eth/src/vhdl/eth_control.vhd
index c9f05abf52f6ac95e75079241ce81108207231b5..7efb2fa35a64090f2c818feb9785306d92d3b35d 100644
--- a/libraries/io/eth/src/vhdl/eth_control.vhd
+++ b/libraries/io/eth/src/vhdl/eth_control.vhd
@@ -187,6 +187,8 @@ BEGIN
       nxt_hdr_response_arr <= func_network_total_header_response_arp( rcv_hdr_words_arr, reg_config.mac_address, reg_config.ip_address);
     ELSIF rcv_hdr_status.is_icmp='1' THEN
       nxt_hdr_response_arr <= func_network_total_header_response_icmp(rcv_hdr_words_arr, reg_config.mac_address);
+      -- Calculate icmp checksum = original checksum + 0x0800.
+      nxt_hdr_response_arr(9)(c_halfword_w-1 DOWNTO 0) <= TO_UVEC( 2048 + TO_UINT(rcv_hdr_words_arr(9)(c_halfword_w-1 DOWNTO 0)), c_halfword_w);
     ELSIF rcv_hdr_status.is_udp='1' THEN
       nxt_hdr_response_arr <= func_network_total_header_response_udp( rcv_hdr_words_arr, reg_config.mac_address);
     ELSIF rcv_hdr_status.is_ip='1' THEN
diff --git a/libraries/io/eth/tb/vhdl/tb_eth.vhd b/libraries/io/eth/tb/vhdl/tb_eth.vhd
index 22387c22d9d90beb359e0e2513ef85bd8ef065a2..8274212a952de0465c56fedb596507b4b2148018 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth.vhd
@@ -181,9 +181,13 @@ ARCHITECTURE tb OF tb_eth IS
                                                              checksum => TO_UVEC(c_network_icmp_checksum,         c_network_icmp_checksum_w),  -- init value
                                                              id       => TO_UVEC(c_network_icmp_id,               c_network_icmp_id_w),
                                                              sequence => TO_UVEC(c_network_icmp_sequence,         c_network_icmp_sequence_w));
+
+  -- checksum is 0x0800 + original checksum
+  CONSTANT c_exp_icmp_checksum   : STD_LOGIC_VECTOR(c_network_icmp_checksum_w-1 DOWNTO 0) := TO_UVEC( 2048 + TO_UINT(c_tx_icmp_header.checksum), c_network_icmp_checksum_w);
+
   CONSTANT c_exp_icmp_header     : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply,   c_network_icmp_msg_type_w),  -- ping reply
                                                              code     => c_tx_icmp_header.code,
-                                                             checksum => c_tx_icmp_header.checksum,          -- init value
+                                                             checksum => c_exp_icmp_checksum,
                                                              id       => c_tx_icmp_header.id,
                                                              sequence => c_tx_icmp_header.sequence);
   
diff --git a/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd b/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
index 956e61a07e4262b35df42a61d4f4eda7dc69a995..ad31f6993c05a73b70d8178512ce05d7e6468c2d 100644
--- a/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
+++ b/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
@@ -181,9 +181,13 @@ ARCHITECTURE tb OF tb_eth1g IS
                                                              checksum => TO_UVEC(c_network_icmp_checksum,         c_network_icmp_checksum_w),  -- init value
                                                              id       => TO_UVEC(c_network_icmp_id,               c_network_icmp_id_w),
                                                              sequence => TO_UVEC(c_network_icmp_sequence,         c_network_icmp_sequence_w));
+
+  -- checksum is 0x0800 + original checksum
+  CONSTANT c_exp_icmp_checksum   : STD_LOGIC_VECTOR(c_network_icmp_checksum_w-1 DOWNTO 0) := TO_UVEC( 2048 + TO_UINT(c_tx_icmp_header.checksum), c_network_icmp_checksum_w);
+
   CONSTANT c_exp_icmp_header     : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply,   c_network_icmp_msg_type_w),  -- ping reply
                                                              code     => c_tx_icmp_header.code,
-                                                             checksum => c_tx_icmp_header.checksum,          -- init value
+                                                             checksum => c_exp_icmp_checksum,
                                                              id       => c_tx_icmp_header.id,
                                                              sequence => c_tx_icmp_header.sequence);