diff --git a/applications/arts/designs/arts_unb2b_sc3/revisions/arts_unb2b_sc3_partial/arts_unb2b_sc3_partial.vhd b/applications/arts/designs/arts_unb2b_sc3/revisions/arts_unb2b_sc3_partial/arts_unb2b_sc3_partial.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2df4e11577dffa81e7c6f54b44b04f6f74c9c73a
--- /dev/null
+++ b/applications/arts/designs/arts_unb2b_sc3/revisions/arts_unb2b_sc3_partial/arts_unb2b_sc3_partial.vhd
@@ -0,0 +1,189 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2018
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2_board_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+
+ENTITY arts_unb2b_sc3_partial IS
+ GENERIC (
+ g_design_name : STRING := "arts_unb2b_sc3_partial";
+ g_design_note : STRING := "UNUSED";
+ g_technology : NATURAL := c_tech_arria10_e1sg;
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_sim_model_ddr : BOOLEAN := FALSE;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
+ g_factory_image : BOOLEAN := FALSE
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ SB_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE back upper 24 lines
+ BCK_REF_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE back lower 24 lines
+
+ -- DDR reference clocks
+ MB_I_REF_CLK : IN STD_LOGIC := '0'; -- Reference clock for MB_I
+ MB_II_REF_CLK : IN STD_LOGIC := '0'; -- Reference clock for MB_II
+
+ -- pmbus
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- front transceivers
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Inputs 0..3
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Outputs 0..3
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Inputs 4..7
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Outputs 4..7
+ QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Inputs 8..11
+ QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Inputs 12..15
+ QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Inputs 16..19
+ QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Inputs 20..23
+ QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+
+ QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ QSFP_RST : INOUT STD_LOGIC;
+
+ -- Leds
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0) --2 LEDs per QSFP so not usable in quad 10G mode
+ );
+END arts_unb2b_sc3_partial;
+
+
+ARCHITECTURE str OF arts_unb2b_sc3_partial IS
+
+ CONSTANT c_design_name : STRING := "arts_unb2b_sc3_partial";
+
+BEGIN
+
+ u_revision : ENTITY work.arts_unb2b_sc3
+ GENERIC MAP (
+ g_design_name => c_design_name,
+ g_design_note => g_design_note,
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_factory_image => g_factory_image
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+ QSFP_RST => QSFP_RST,
+
+ -- Leds
+ QSFP_LED => QSFP_LED
+ );
+
+END str;
diff --git a/applications/arts/designs/arts_unb2b_sc3/revisions/arts_unb2b_sc3_partial/arts_unb2b_sc3_partial_pins.tcl b/applications/arts/designs/arts_unb2b_sc3/revisions/arts_unb2b_sc3_partial/arts_unb2b_sc3_partial_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..fe232c6c04215b54b8a460c2a16db7e3755a0660
--- /dev/null
+++ b/applications/arts/designs/arts_unb2b_sc3/revisions/arts_unb2b_sc3_partial/arts_unb2b_sc3_partial_pins.tcl
@@ -0,0 +1,245 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+
+#set_location_assignment PIN_AL32 -to CLKUSR
+#
+#
+#set_location_assignment PIN_Y36 -to SA_CLK
+#set_instance_assignment -name IO_STANDARD LVDS -to SA_CLK
+## internal termination should be enabled.
+#set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SA_CLK
+#
+#
+#set_location_assignment PIN_AH9 -to SB_CLK
+#set_instance_assignment -name IO_STANDARD LVDS -to SB_CLK
+## internal termination should be enabled.
+#set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SB_CLK
+#
+#
+#set_location_assignment PIN_V9 -to BCK_REF_CLK
+#set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
+#set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
+#set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
+#
+#
+#
+#set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
+#
+## QSFP_0_RX
+#set_location_assignment PIN_AN38 -to QSFP_0_RX[0]
+#set_location_assignment PIN_AM40 -to QSFP_0_RX[1]
+#set_location_assignment PIN_AK40 -to QSFP_0_RX[2]
+#set_location_assignment PIN_AJ38 -to QSFP_0_RX[3]
+#
+##set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_RX[0]
+##set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_RX[1]
+##set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_RX[2]
+##set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_RX[3]
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0]
+#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[0]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[0]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[0]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[0]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[0]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[0]
+#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[0]
+#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[0]
+#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[0]
+#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[0]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[0]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[1]
+#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[1]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[1]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[1]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[1]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[1]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[1]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[1]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[1]
+#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[1]
+#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[1]
+#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[1]
+#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[1]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[1]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[2]
+#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[2]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[2]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[2]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[2]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[2]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[2]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[2]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[2]
+#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[2]
+#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[2]
+#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[2]
+#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[2]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[2]
+#
+#
+## QSFP_0_TX
+#set_location_assignment PIN_AN42 -to QSFP_0_TX[0]
+#set_location_assignment PIN_AM44 -to QSFP_0_TX[1]
+#set_location_assignment PIN_AK44 -to QSFP_0_TX[2]
+#set_location_assignment PIN_AJ42 -to QSFP_0_TX[3]
+#
+##set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_TX[0]
+##set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_TX[1]
+##set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_TX[2]
+##set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to QSFP_0_TX[3]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[0]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[0]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[0]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[0]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[1]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[1]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[1]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[1]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[1]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[1]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[2]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[2]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[2]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[2]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[2]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[2]
+#
+## QSFP_1_RX
+#set_location_assignment PIN_AC38 -to QSFP_1_RX[0]
+#set_location_assignment PIN_AD40 -to QSFP_1_RX[1]
+#set_location_assignment PIN_AF40 -to QSFP_1_RX[2]
+#set_location_assignment PIN_AG38 -to QSFP_1_RX[3]
+#
+## QSFP_1_TX
+#set_location_assignment PIN_AC42 -to QSFP_1_TX[0]
+#set_location_assignment PIN_AD44 -to QSFP_1_TX[1]
+#set_location_assignment PIN_AF44 -to QSFP_1_TX[2]
+#set_location_assignment PIN_AG42 -to QSFP_1_TX[3]
+#
+## QSFP_2_RX
+#set_location_assignment PIN_AL38 -to QSFP_2_RX[0]
+#set_location_assignment PIN_AH40 -to QSFP_2_RX[1]
+#set_location_assignment PIN_AE38 -to QSFP_2_RX[2]
+#set_location_assignment PIN_AB40 -to QSFP_2_RX[3]
+#
+## QSFP_2_TX
+#set_location_assignment PIN_AL42 -to QSFP_2_TX[0]
+#set_location_assignment PIN_AH44 -to QSFP_2_TX[1]
+#set_location_assignment PIN_AE42 -to QSFP_2_TX[2]
+#set_location_assignment PIN_AB44 -to QSFP_2_TX[3]
+#
+## QSFP_3_RX
+#set_location_assignment PIN_W38 -to QSFP_3_RX[0]
+#set_location_assignment PIN_T40 -to QSFP_3_RX[1]
+#set_location_assignment PIN_N38 -to QSFP_3_RX[2]
+#set_location_assignment PIN_K40 -to QSFP_3_RX[3]
+#
+## QSFP_3_TX
+#set_location_assignment PIN_W42 -to QSFP_3_TX[0]
+#set_location_assignment PIN_T44 -to QSFP_3_TX[1]
+#set_location_assignment PIN_N42 -to QSFP_3_TX[2]
+#set_location_assignment PIN_K44 -to QSFP_3_TX[3]
+#
+## QSFP_4_RX
+#set_location_assignment PIN_AA38 -to QSFP_4_RX[0]
+#set_location_assignment PIN_Y40 -to QSFP_4_RX[1]
+#set_location_assignment PIN_V40 -to QSFP_4_RX[2]
+#set_location_assignment PIN_U38 -to QSFP_4_RX[3]
+#
+## QSFP_4_TX
+#set_location_assignment PIN_AA42 -to QSFP_4_TX[0]
+#set_location_assignment PIN_Y44 -to QSFP_4_TX[1]
+#set_location_assignment PIN_V44 -to QSFP_4_TX[2]
+#set_location_assignment PIN_U42 -to QSFP_4_TX[3]
+#
+## QSFP_5_RX
+#set_location_assignment PIN_L38 -to QSFP_5_RX[0]
+#set_location_assignment PIN_M40 -to QSFP_5_RX[1]
+#set_location_assignment PIN_P40 -to QSFP_5_RX[2]
+#set_location_assignment PIN_R38 -to QSFP_5_RX[3]
+#
+## QSFP_5_TX
+#set_location_assignment PIN_L42 -to QSFP_5_TX[0]
+#set_location_assignment PIN_M44 -to QSFP_5_TX[1]
+#set_location_assignment PIN_P44 -to QSFP_5_TX[2]
+#set_location_assignment PIN_R42 -to QSFP_5_TX[3]
+#
+#
+#
+#set_location_assignment PIN_R14 -to BCK_SCL[0]
+#set_location_assignment PIN_Y13 -to BCK_SCL[1]
+#set_location_assignment PIN_U14 -to BCK_SCL[2]
+#set_location_assignment PIN_P14 -to BCK_SDA[0]
+#set_location_assignment PIN_T12 -to BCK_SDA[1]
+#set_location_assignment PIN_V12 -to BCK_SDA[2]
+#
+#set_location_assignment PIN_AT31 -to QSFP_RST
+#
+#set_location_assignment PIN_AY33 -to QSFP_SCL[0]
+#set_location_assignment PIN_AY32 -to QSFP_SCL[1]
+#set_location_assignment PIN_AY30 -to QSFP_SCL[2]
+#set_location_assignment PIN_AN33 -to QSFP_SCL[3]
+#set_location_assignment PIN_AN31 -to QSFP_SCL[4]
+#set_location_assignment PIN_AJ33 -to QSFP_SCL[5]
+#set_location_assignment PIN_BA32 -to QSFP_SDA[0]
+#set_location_assignment PIN_BA31 -to QSFP_SDA[1]
+#set_location_assignment PIN_AP33 -to QSFP_SDA[2]
+#set_location_assignment PIN_AM33 -to QSFP_SDA[3]
+#set_location_assignment PIN_AK33 -to QSFP_SDA[4]
+#set_location_assignment PIN_AH32 -to QSFP_SDA[5]
+#set_location_assignment PIN_M13 -to BCK_ERR[0]
+#set_location_assignment PIN_R13 -to BCK_ERR[1]
+#set_location_assignment PIN_U12 -to BCK_ERR[2]
+#
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[5]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[5]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[0]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[0]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[1]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[1]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[2]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[2]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[0]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[1]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[0]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[1]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[2]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[3]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[4]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[2]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[3]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[4]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[0]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[1]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[2]
diff --git a/applications/arts/designs/arts_unb2b_sc3/revisions/arts_unb2b_sc3_partial/hdllib.cfg b/applications/arts/designs/arts_unb2b_sc3/revisions/arts_unb2b_sc3_partial/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..e4572e30348ae99955db1d04a33422466654ffdb
--- /dev/null
+++ b/applications/arts/designs/arts_unb2b_sc3/revisions/arts_unb2b_sc3_partial/hdllib.cfg
@@ -0,0 +1,70 @@
+hdl_lib_name = arts_unb2b_sc3_partial
+hdl_library_clause_name = arts_unb2b_sc3_partial_lib
+hdl_lib_uses_synth = common technology mm unb2b_board unb2b_board_10gbe dp eth tech_tse tr_10GbE diagnostics diag tech_mac_10g arts_unb1_sc4 apertif arts arts_tab_beamformer iquv
+hdl_lib_uses_sim = arts_unb2b_xc_emu
+hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_include_ip =
+ # Comment all IP that is not used in this design
+ # 10GbE
+ ip_arria10_e1sg_mac_10g
+ ip_arria10_e1sg_pll_xgmii_mac_clocks
+ ip_arria10_e1sg_transceiver_pll_10g
+
+ ip_arria10_e1sg_phy_10gbase_r
+ ip_arria10_e1sg_phy_10gbase_r_3
+ ip_arria10_e1sg_phy_10gbase_r_4
+ ip_arria10_e1sg_phy_10gbase_r_12
+ ip_arria10_e1sg_phy_10gbase_r_24
+ ip_arria10_e1sg_phy_10gbase_r_48
+
+ ip_arria10_e1sg_transceiver_reset_controller_1
+ ip_arria10_e1sg_transceiver_reset_controller_3
+ ip_arria10_e1sg_transceiver_reset_controller_4
+ ip_arria10_e1sg_transceiver_reset_controller_12
+ ip_arria10_e1sg_transceiver_reset_controller_24
+ ip_arria10_e1sg_transceiver_reset_controller_48
+
+synth_files =
+ ../../src/vhdl/arts_unb2b_sc3_pkg.vhd
+ ../../src/vhdl/qsys_arts_unb2b_sc3_pkg.vhd
+ ../../src/vhdl/arts_unb2b_sc3_mm_master.vhd
+ ../../src/vhdl/arts_unb2b_sc3_input.vhd
+ ../../src/vhdl/arts_unb2b_sc3_processing.vhd
+ # Workaround; we can't use unb1 libs in unb2b Questasim (yet).
+ $RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_reorder.vhd
+ $RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd
+ $RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd
+ $RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_packetizer.vhd
+ $RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab.vhd
+ ../../src/vhdl/arts_unb2b_sc3_output.vhd
+ ../../src/vhdl/arts_unb2b_sc3.vhd
+ arts_unb2b_sc3_partial.vhd
+
+test_bench_files =
+
+regression_test_vhdl =
+
+[modelsim_project_file]
+modelsim_copy_files =
+# hex hex # Hex files for beamformer weights
+# ../../../arts_unb2b_xc_emu/src/hex hex/. # Hex files for correlator emulator
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus .
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_files =
+ $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+ arts_unb2b_sc3_partial_pins.tcl
+
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $HDL_BUILD_DIR/unb2b/quartus/arts_unb2b_sc3_single/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3.qip
diff --git a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_pkg.vhd b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_pkg.vhd
index 86369c5899d6c12504084863ff7c4046891196fc..0c7e56d9ec9cada62b99d54987506ec8e1f84ada 100644
--- a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_pkg.vhd
+++ b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_pkg.vhd
@@ -44,6 +44,7 @@ PACKAGE arts_unb2b_sc3_pkg IS
-- -- |
CONSTANT c_full : t_arts_unb2b_sc3_config := ( nof_cbsets => 8 );
CONSTANT c_single : t_arts_unb2b_sc3_config := ( nof_cbsets => 1 );
+ CONSTANT c_partial : t_arts_unb2b_sc3_config := ( nof_cbsets => 7 ); -- can edit to try different values
-- Function to select the revision configuration.
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_arts_unb2b_sc3_config;
@@ -57,8 +58,9 @@ PACKAGE BODY arts_unb2b_sc3_pkg IS
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_arts_unb2b_sc3_config IS
BEGIN
- IF g_design_name = "arts_unb2b_sc3_full" THEN RETURN c_full;
- ELSIF g_design_name = "arts_unb2b_sc3_single" THEN RETURN c_single;
+ IF g_design_name = "arts_unb2b_sc3_full" THEN RETURN c_full;
+ ELSIF g_design_name = "arts_unb2b_sc3_single" THEN RETURN c_single;
+ ELSIF g_design_name = "arts_unb2b_sc3_partial" THEN RETURN c_partial;
ELSE RETURN c_full;
END IF;
END;