From 548bb8faa22b14c6fec07665023cc9182a1b9759 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Wed, 6 Jan 2021 11:37:13 +0100
Subject: [PATCH] fixed manual reset. Reset diag_data_buffer as well
---
.../src/vhdl/node_adc_input_and_timing.vhd | 22 ++++++++++---------
.../jesd204b/ip_arria10_e1sg_jesd204b.vhd | 4 ++--
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 4b8ab7405d..cd964ead4b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -165,10 +165,12 @@ ARCHITECTURE str OF node_adc_input_and_timing IS
SIGNAL nxt_mux_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL st_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
-
+ SIGNAL mm_rst_internal : STD_LOGIC;
BEGIN
+ mm_rst_internal <= mm_rst OR jesd204b_reset;
+
-----------------------------------------------------------------------------
-- JESD204B IP (ADC Handler)
-----------------------------------------------------------------------------
@@ -195,7 +197,7 @@ BEGIN
-- MM
mm_clk => mm_clk,
- mm_rst => mm_rst,
+ mm_rst => mm_rst_internal,
jesd204b_mosi => jesd204b_mosi,
jesd204b_miso => jesd204b_miso,
@@ -229,7 +231,7 @@ BEGIN
g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
)
PORT MAP (
- mm_rst => mm_rst,
+ mm_rst => mm_rst_internal,
mm_clk => mm_clk,
dp_rst => rx_rst,
dp_clk => rx_clk,
@@ -270,7 +272,7 @@ BEGIN
dp_rst => rx_rst,
dp_clk => rx_clk,
- mm_rst => mm_rst,
+ mm_rst => mm_rst_internal,
mm_clk => mm_clk,
sync_in => bs_sosi.sync,
@@ -295,7 +297,7 @@ BEGIN
)
PORT MAP (
-- Clocks and reset
- mm_rst => mm_rst,
+ mm_rst => mm_rst_internal,
mm_clk => mm_clk,
dp_rst => rx_rst,
dp_clk => rx_clk,
@@ -316,7 +318,7 @@ BEGIN
)
PORT MAP (
-- Memory-mapped clock domain
- mm_rst => mm_rst,
+ mm_rst => mm_rst_internal,
mm_clk => mm_clk,
reg_mosi => reg_bsn_scheduler_wg_mosi,
@@ -353,7 +355,7 @@ BEGIN
)
PORT MAP (
-- Memory-mapped clock domain
- mm_rst => mm_rst,
+ mm_rst => mm_rst_internal,
mm_clk => mm_clk,
reg_mosi => reg_wg_mosi,
@@ -422,7 +424,7 @@ BEGIN
)
PORT MAP (
-- Memory-mapped clock domain
- mm_rst => mm_rst,
+ mm_rst => mm_rst_internal,
mm_clk => mm_clk,
reg_mosi => reg_bsn_monitor_input_mosi,
reg_miso => reg_bsn_monitor_input_miso,
@@ -449,7 +451,7 @@ BEGIN
)
PORT MAP (
-- Memory-mapped clock domain
- mm_rst => mm_rst,
+ mm_rst => mm_rst_internal,
mm_clk => mm_clk,
reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
@@ -478,7 +480,7 @@ BEGIN
g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
)
PORT MAP (
- mm_rst => mm_rst,
+ mm_rst => mm_rst_internal,
mm_clk => mm_clk,
dp_rst => rx_rst,
dp_clk => rx_clk,
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 65b6407595..8a3bbea4dc 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -236,7 +236,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
BEGIN
- mm_rst_internal <= mm_rst OR jesd204b_reset;
+ mm_rst_internal <= mm_rst; -- OR jesd204b_reset;
rx_clk <= rxframe_clk;
rx_rst <= not core_pll_locked;
@@ -330,7 +330,7 @@ BEGIN
reset5_dsrt_qual => rx_xcvr_ready_in_arr(i),
reset_in0 => mm_rst_internal,
reset_out0 => pll_reset_arr(i), -- Use channel 0 to reset the core pll
- reset_out1 => xcvr_rst_arr(i), -- Use channel 0 to reset the transceiver reset controller
+ reset_out1 => xcvr_rst_arr(i), -- Use channel 1 to reset the transceiver reset controller
reset_out2 => open,
reset_out3 => open,
reset_out4 => open,
--
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