diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index e802791e80385d64d2cdfbcd960fa1e5f9a91e3e..a771f00bfca6ab032377cd1987902fec203da70d 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -128,6 +128,7 @@ ARCHITECTURE str OF ddrctrl IS
SIGNAL inp_bsn_adr : NATURAL;
SIGNAL outp_ds : NATURAL;
SIGNAL outp_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+ SIGNAL data_stopped : STD_LOGIC;
BEGIN
@@ -153,7 +154,8 @@ BEGIN
out_sosi => out_sosi,
out_adr => out_adr,
out_bsn_ds => inp_ds,
- out_bsn_adr => inp_bsn_adr
+ out_bsn_adr => inp_bsn_adr,
+ out_data_stopped => data_stopped
);
-- functions as a fifo buffer for input data into the sdram stick. also manages input to sdram stick.
@@ -278,6 +280,7 @@ BEGIN
inp_adr => out_adr,
inp_ds => inp_ds,
inp_bsn_adr => inp_bsn_adr,
+ inp_data_stopped => data_stopped,
rst_ddrctrl_input => rst_ddrctrl_input,
-- io_ddr
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index df90236414b18368ced333370d4287aca3246515..a5b7994fc174ef6139c42b1d38dc6032500252a2 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -61,6 +61,7 @@ ENTITY ddrctrl_controller IS
inp_adr : IN NATURAL;
inp_ds : IN NATURAL;
inp_bsn_adr : IN NATURAL;
+ inp_data_stopped : IN STD_LOGIC;
rst_ddrctrl_input : OUT STD_LOGIC;
-- io_ddr
@@ -104,7 +105,6 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
stop_adr : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
stopped : STD_LOGIC;
rst_ddrctrl_input : STD_LOGIC;
- cooling_down : NATURAL;
-- writing signals
need_burst : STD_LOGIC;
@@ -120,7 +120,7 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
wr_sosi : t_dp_sosi;
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, '0', TO_UVEC(g_max_adr, c_adr_w), '1', '1', 8, '0', 0, (OTHERS => '0'), 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
+ CONSTANT c_t_reg_init : t_reg := (RESET, '0', TO_UVEC(g_max_adr, c_adr_w), '1', '1', '0', 0, (OTHERS => '0'), 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
-- signals for readability
@@ -132,7 +132,7 @@ BEGIN
q_reg <= d_reg WHEN rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
- p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr, inp_ds, inp_bsn_adr, dvr_miso, rd_fifo_usedw, stop_in)
+ p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr, inp_ds, inp_bsn_adr, inp_data_stopped, dvr_miso, rd_fifo_usedw, stop_in)
VARIABLE v : t_reg := c_t_reg_init;
@@ -183,7 +183,6 @@ BEGIN
v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_adr) := TO_UVEC(inp_adr+c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO c_bitshift_adr);
END IF;
v.stop_adr(c_bitshift_adr-1 DOWNTO 0) := c_zeros;
- v.cooling_down := 8;
-- still a write cyle
-- if adr mod g_burstsize = 0
@@ -212,16 +211,15 @@ BEGIN
WHEN STOP_WRITING =>
v.dvr_mosi.burstbegin := '0';
+ v.stopped := '1';
-- wait until the write burst is finished
- IF NOT (q_reg.cooling_down = 0) THEN
- v.cooling_down := q_reg.cooling_down-1;
+ IF inp_data_stopped = '0' THEN
v.state := STOP_WRITING;
- ELSIF dvr_miso.done = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
- v.stopped := '1';
+ ELSIF dvr_miso.done = '1' AND q_reg.dvr_mosi.burstbegin = '0' AND q_reg.need_burst = '0' THEN
v.wr_sosi.valid := '0';
v.state := START_READING;
ELSE
- v.state := STOP_WRITING;
+ v.state := STOP_WRITING;
END IF;
-- still receiving write data.
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
index d4cb0309ce79cdf4a08bcaaeb4ec5c7e1818d9ea..208780472a0e4df9cfc607de8f8f3e87e0ffb783 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
@@ -60,7 +60,8 @@ ENTITY ddrctrl_input IS
out_sosi : OUT t_dp_sosi; -- output data
out_adr : OUT NATURAL;
out_bsn_ds : OUT NATURAL;
- out_bsn_adr : OUT NATURAL
+ out_bsn_adr : OUT NATURAL;
+ out_data_stopped : OUT STD_LOGIC
);
END ddrctrl_input;
@@ -72,11 +73,12 @@ ARCHITECTURE str OF ddrctrl_input IS
-- signals for connecting the components
- SIGNAL sosi_p_rp : t_dp_sosi := c_dp_sosi_init;
- SIGNAL sosi_rp_ac : t_dp_sosi := c_dp_sosi_init;
- SIGNAL adr : NATURAL := 0;
- SIGNAL bsn_ds : NATURAL := 0;
- SIGNAL valid : STD_LOGIC := '0';
+ SIGNAL sosi_p_rp : t_dp_sosi := c_dp_sosi_init;
+ SIGNAL sosi_rp_ac : t_dp_sosi := c_dp_sosi_init;
+ SIGNAL adr : NATURAL := 0;
+ SIGNAL bsn_ds : NATURAL := 0;
+ SIGNAL valid : STD_LOGIC := '0';
+ SIGNAL data_stopped_rp_ac : STD_LOGIC := '0';
BEGIN
@@ -108,7 +110,8 @@ BEGIN
in_sosi => sosi_p_rp, -- input data
in_stop => in_stop,
out_sosi => sosi_rp_ac, -- output data
- out_bsn_ds => bsn_ds -- amount of bits between adr [0] and sosi_arr[0][0] where bsn is assigned to
+ out_bsn_ds => bsn_ds, -- amount of bits between adr [0] and sosi_arr[0][0] where bsn is assigned to
+ out_data_stopped => data_stopped_rp_ac
);
-- creates address by counting input valids
@@ -122,10 +125,12 @@ BEGIN
rst => rst,
in_sosi => sosi_rp_ac, -- input data
in_bsn_ds => bsn_ds,
+ in_data_stopped => data_stopped_rp_ac,
out_sosi => out_sosi, -- output data
out_adr => adr,
out_bsn_adr => out_bsn_adr,
- out_bsn_ds => out_bsn_ds
+ out_bsn_ds => out_bsn_ds,
+ out_data_stopped => out_data_stopped
);
END str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
index 43cb85d273a95ca7e971c36aafc7347959e93a51..dda45ab77071c8e4385e84497e00df11e775e6f1 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
@@ -49,10 +49,12 @@ ENTITY ddrctrl_input_address_counter IS
rst : IN STD_LOGIC;
in_sosi : IN t_dp_sosi; -- input data
in_bsn_ds : IN NATURAL;
+ in_data_stopped : IN STD_LOGIC;
out_sosi : OUT t_dp_sosi := c_dp_sosi_init; -- output data
out_adr : OUT NATURAL;
out_bsn_adr : OUT NATURAL;
- out_bsn_ds : OUT NATURAL
+ out_bsn_ds : OUT NATURAL;
+ out_data_stopped : OUT STD_LOGIC
);
END ddrctrl_input_address_counter;
@@ -72,12 +74,14 @@ ARCHITECTURE rtl OF ddrctrl_input_address_counter IS
out_sosi : t_dp_sosi;
out_bsn_adr : NATURAL;
out_bsn_ds : NATURAL;
+ out_data_stopped : STD_LOGIC;
s_in_sosi : t_dp_sosi;
s_in_bsn_ds : NATURAL;
+ s_in_data_stopped : STD_LOGIC;
s_adr : NATURAL;
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, '0', c_dp_sosi_init, 0, 0, c_dp_sosi_init, 0, 0);
+ CONSTANT c_t_reg_init : t_reg := (RESET, '0', c_dp_sosi_init, 0, 0, '0', c_dp_sosi_init, 0, '0', 0);
-- signals for readability
@@ -89,7 +93,7 @@ BEGIN
q_reg <= d_reg WHEN rising_edge(clk);
-- Increments the address each time in_sosi.valid = '1', if address = g_max_adr the address is reset to 0.
- p_adr : PROCESS(rst, in_sosi, q_reg)
+ p_adr : PROCESS(rst, in_sosi, in_bsn_ds, in_data_stopped, q_reg)
VARIABLE v : t_reg;
@@ -99,8 +103,10 @@ BEGIN
-- compensate for delay in ddrctrl_input_address_counter
v.out_sosi := q_reg.s_in_sosi;
v.out_bsn_ds := q_reg.s_in_bsn_ds;
+ v.out_data_stopped := q_reg.s_in_data_stopped;
v.s_in_sosi := in_sosi;
v.s_in_bsn_ds := in_bsn_ds;
+ v.s_in_data_stopped := in_data_stopped;
CASE q_reg.state IS
@@ -129,7 +135,7 @@ BEGIN
WHEN IDLE =>
- -- after a reset skip the first data block so the ddr memory can calm down.
+ -- after a reset skip the first data block so the ddr memory can initialize.
IF NOT(q_reg.s_in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN
v.bsn_passed := '1';
END IF;
@@ -151,10 +157,11 @@ BEGIN
END PROCESS;
-- fill outputs
- out_sosi <= q_reg.out_sosi;
- out_adr <= q_reg.s_adr;
- out_bsn_adr <= q_reg.out_bsn_adr;
- out_bsn_ds <= q_reg.out_bsn_ds;
- out_sosi.bsn <= q_reg.out_sosi.bsn;
+ out_sosi <= q_reg.out_sosi;
+ out_adr <= q_reg.s_adr;
+ out_bsn_adr <= q_reg.out_bsn_adr;
+ out_bsn_ds <= q_reg.out_bsn_ds;
+ out_sosi.bsn <= q_reg.out_sosi.bsn;
+ out_data_stopped <= q_reg.out_data_stopped;
END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
index 6bcf139147a7f82a2914cc2b6741897a55f8355b..7b7a3ed0d98c5229929b4d25982b3aa41910a258 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
@@ -49,7 +49,8 @@ ENTITY ddrctrl_input_repack IS
in_stop : IN STD_LOGIC := '0';
out_sosi : OUT t_dp_sosi := c_dp_sosi_init; -- output data
out_bsn_ds : OUT NATURAL := 0;
- out_bsn_wr : OUT STD_LOGIC := '0'
+ out_bsn_wr : OUT STD_LOGIC := '0';
+ out_data_stopped : OUT STD_LOGIC := '0'
);
END ddrctrl_input_repack;
@@ -77,9 +78,10 @@ ARCHITECTURE rtl OF ddrctrl_input_repack IS
out_data_count : STD_LOGIC; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
out_sosi : t_dp_sosi; -- this is the sosi stream that contains the data
out_bsn_ds : NATURAL; -- this is the amount of bits that the data corresponding to out_bsn is shifted from the first bit in that data word
+ out_data_stopped : STD_LOGIC; -- this signal is '1' when there is no more data comming form ddrctrl_input_pack
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, (OTHERS => '0'), 0, 0, (OTHERS => '0'), '0', 0, 0, 0, '0', c_dp_sosi_init, 0);
+ CONSTANT c_t_reg_init : t_reg := (RESET, (OTHERS => '0'), 0, 0, (OTHERS => '0'), '0', 0, 0, 0, '0', c_dp_sosi_init, 0, '0');
-- signals for readability
@@ -107,6 +109,7 @@ BEGIN
v.s_input_cnt := q_reg.s_input_cnt+1;
v.out_sosi.sop := '0';
v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
@@ -139,6 +142,7 @@ BEGIN
v.out_bsn_ds := q_reg.q_out_bsn_ds;
v.out_sosi.sop := q_reg.q_sop;
v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
IF rst = '1' THEN
@@ -169,6 +173,7 @@ BEGIN
v.q_sop := '0';
v.out_sosi.sop := '0';
v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
IF rst = '1' THEN
@@ -242,7 +247,8 @@ BEGIN
WHEN STOP =>
v.out_sosi.valid := '0';
- v.q_sop := '0';
+ v.q_sop := '0';
+ v.out_data_stopped := '1';
IF rst = '1' THEN
v.state := RESET;
ELSIF in_stop = '1' OR in_sosi.valid = '0' THEN
@@ -263,7 +269,8 @@ BEGIN
END PROCESS;
-- fill outputs
- out_sosi <= q_reg.out_sosi;
- out_bsn_ds <= q_reg.out_bsn_ds;
+ out_sosi <= q_reg.out_sosi;
+ out_bsn_ds <= q_reg.out_bsn_ds;
+ out_data_stopped <= q_reg.out_data_stopped;
END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index fb535d7ad956b2600e5a2a5e545cd2aeebdeda85..9689c0450ca13f0d4f6369dcb8a931ccf81977fa 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -176,7 +176,7 @@ BEGIN
-- wr fifo has delay of 4 clockcylces after reset
-- filling the input data vectors with the corresponding numbers
- run_multiple_times : FOR K in 0 TO 4 LOOP
+ run_multiple_times : FOR K in 0 TO 3 LOOP
make_data : FOR J IN 0 TO c_bim*g_block_size-1 LOOP
in_data_cnt <= in_data_cnt+1;
fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP