From 5165efa90f33452aff22c762b58c4626cb5de394 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Mon, 26 Jan 2015 14:58:18 +0000
Subject: [PATCH] SVN copy-renamed unb2_board_pulser.vhd into
common_pulser_us_ms_s.vhd. Added tb_common_pulser_us_ms_s.vhd.
---
libraries/base/common/hdllib.cfg | 2 +
.../common/src/vhdl/common_pulser_us_ms_s.vhd | 117 ++++++++++++++++++
.../tb/vhdl/tb_common_pulser_us_ms_s.vhd | 98 +++++++++++++++
3 files changed, 217 insertions(+)
create mode 100644 libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
create mode 100644 libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
index c8cf1ec89b..e39164c39e 100644
--- a/libraries/base/common/hdllib.cfg
+++ b/libraries/base/common/hdllib.cfg
@@ -70,6 +70,7 @@ synth_files =
$UNB/Firmware/modules/common/src/vhdl/common_counter.vhd
$UNB/Firmware/modules/common/src/vhdl/common_init.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pulser.vhd
+ src/vhdl/common_pulser_us_ms_s.vhd
$UNB/Firmware/modules/common/src/vhdl/common_debounce.vhd
$UNB/Firmware/modules/common/src/vhdl/common_frame_busy.vhd
$UNB/Firmware/modules/common/src/vhdl/common_stable_delayed.vhd
@@ -190,6 +191,7 @@ test_bench_files =
$UNB/Firmware/modules/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_pulse_extend.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_pulser.vhd
+ tb/vhdl/tb_common_pulser_us_ms_s.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_reg_cross_domain.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_reinterleave.vhd
$UNB/Firmware/modules/common/tb/vhdl/tb_common_reorder_symbol.vhd
diff --git a/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd b/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
new file mode 100644
index 0000000000..04560dbf77
--- /dev/null
+++ b/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
@@ -0,0 +1,117 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+-- Purpose: Provide timing pulses for interval 1 us, 1 ms and 1 s
+
+ENTITY common_pulser_us_ms_s IS
+ GENERIC (
+ g_pulse_us : NATURAL := 125/(10**6); -- nof clk cycles to get us period
+ g_pulse_ms : NATURAL := 1000; -- nof pulse_us pulses to get ms period
+ g_pulse_s : NATURAL := 1000 -- nof pulse_ms pulses to get s period
+ );
+ PORT (
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ sync : IN STD_LOGIC := '0';
+ pulse_us : OUT STD_LOGIC; -- pulses after every g_pulse_us clock cycles
+ pulse_ms : OUT STD_LOGIC; -- pulses after every g_pulse_us*g_pulse_ms clock cycles
+ pulse_s : OUT STD_LOGIC -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
+ );
+END common_pulser_us_ms_s;
+
+
+ARCHITECTURE str OF common_pulser_us_ms_s IS
+
+ SIGNAL pulse_us_pp : STD_LOGIC; -- register to align with pulse_ms
+ SIGNAL pulse_us_p : STD_LOGIC; -- register to align with pulse_s
+ SIGNAL pulse_us_reg : STD_LOGIC; -- output register
+ SIGNAL i_pulse_us : STD_LOGIC;
+
+ SIGNAL pulse_ms_p : STD_LOGIC; -- register to align with pulse_s
+ SIGNAL pulse_ms_reg : STD_LOGIC; -- output register
+ SIGNAL i_pulse_ms : STD_LOGIC;
+
+ SIGNAL pulse_s_reg : STD_LOGIC; -- output register
+ SIGNAL i_pulse_s : STD_LOGIC;
+
+BEGIN
+
+ pulse_us <= i_pulse_us;
+ pulse_ms <= i_pulse_ms;
+ pulse_s <= i_pulse_s;
+
+ p_clk : PROCESS(clk)
+ BEGIN
+ IF rising_edge(clk) THEN
+ pulse_us_p <= pulse_us_pp;
+ pulse_us_reg <= pulse_us_p;
+ pulse_ms_reg <= pulse_ms_p;
+ i_pulse_us <= pulse_us_reg;
+ i_pulse_ms <= pulse_ms_reg;
+ i_pulse_s <= pulse_s_reg;
+ END IF;
+ END PROCESS;
+
+ u_common_pulser_us : ENTITY common_lib.common_pulser
+ GENERIC MAP (
+ g_pulse_period => g_pulse_us
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => '1',
+ pulse_clr => sync,
+ pulse_out => pulse_us_pp
+ );
+
+ u_common_pulser_ms : ENTITY common_lib.common_pulser
+ GENERIC MAP (
+ g_pulse_period => g_pulse_ms
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => pulse_us_pp,
+ pulse_clr => sync,
+ pulse_out => pulse_ms_p
+ );
+
+ u_common_pulser_s : ENTITY common_lib.common_pulser
+ GENERIC MAP (
+ g_pulse_period => g_pulse_s
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => pulse_ms_p,
+ pulse_clr => sync,
+ pulse_out => pulse_s_reg
+ );
+
+END str;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd b/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
new file mode 100644
index 0000000000..16e42db9ba
--- /dev/null
+++ b/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
@@ -0,0 +1,98 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for common_pulser_us_ms_s
+-- Description:
+-- The tb checks that the pulse_us occurs aligned when pulse_ms is active
+-- and when pulse_s is active.
+-- Usage:
+-- > as 3
+-- > run -a
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE work.common_pkg.ALL;
+
+ENTITY tb_common_pulser_us_ms_s IS
+END tb_common_pulser_us_ms_s;
+
+ARCHITECTURE tb OF tb_common_pulser_us_ms_s IS
+
+ CONSTANT c_pulse_us : NATURAL := 10;
+ CONSTANT c_1000 : NATURAL := 1000;
+
+ CONSTANT clk_period : TIME := 1000/c_pulse_us ns;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL rst : STD_LOGIC;
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL sync : STD_LOGIC := '0';
+
+ SIGNAL pulse_us : STD_LOGIC;
+ SIGNAL pulse_ms : STD_LOGIC;
+ SIGNAL pulse_s : STD_LOGIC;
+
+BEGIN
+
+ clk <= NOT clk OR tb_end AFTER clk_period/2;
+
+ p_sync : PROCESS
+ BEGIN
+ sync <= '0';
+ WAIT UNTIL pulse_s='1';
+ WAIT UNTIL pulse_s='1';
+ WAIT UNTIL pulse_s='1';
+ WAIT FOR c_1000/2 ms;
+ sync <= '1';
+ WAIT UNTIL pulse_s='1';
+ WAIT UNTIL pulse_s='1';
+ WAIT UNTIL pulse_s='1';
+ WAIT FOR c_1000/2 ms;
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ p_verify: PROCESS(clk)
+ BEGIN
+ IF rising_edge(clk) THEN
+ IF pulse_us='1' THEN ASSERT pulse_ms='1' AND pulse_s='1' REPORT "Error: pulse_us, ms, s misaligned" SEVERITY ERROR; END IF;
+ IF pulse_ms='1' THEN ASSERT pulse_s='1' REPORT "Error: pulse_ms, s misaligned" SEVERITY ERROR; END IF;
+ END IF;
+ END PROCESS;
+
+ u_common_pulser_us_ms_s : ENTITY work.common_pulser_us_ms_s
+ GENERIC MAP (
+ g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
+ g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ sync => sync,
+ pulse_us => pulse_us, -- pulses after every g_pulse_us clock cycles
+ pulse_ms => pulse_ms, -- pulses after every g_pulse_us*g_pulse_ms clock cycles
+ pulse_s => pulse_s -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
+ );
+
+END tb;
--
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