From 5165d381ad6b47756ce7ca9cca7db53f04c94cc0 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 4 Nov 2016 10:02:55 +0000
Subject: [PATCH] Use internal SCLK in aduh_quad_scope.
---
.../designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd | 3 ---
.../unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd | 4 +---
.../unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd | 1 -
.../unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd | 2 --
4 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
index 05b9b46690..6c1bc660a8 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
@@ -127,7 +127,6 @@ ENTITY node_unb1_bn_capture IS
-- >>> Node FPGA pins
--
-- ADC Interface
- SCLK : IN STD_LOGIC := '0'; -- sample clk, use only for simulation purposes
ADC_BI_A : IN STD_LOGIC_VECTOR(g_ai.port_w-1 DOWNTO 0);
ADC_BI_B : IN STD_LOGIC_VECTOR(g_ai.port_w-1 DOWNTO 0);
ADC_BI_A_CLK : IN STD_LOGIC := '0';
@@ -200,8 +199,6 @@ BEGIN
)
PORT MAP (
-- ADC Interface
- SCLK => SCLK,
-
-- . ADU_AB
ADC_BI_A => ADC_BI_A,
ADC_BI_B => ADC_BI_B,
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
index 6b712b57c8..be2f3249a5 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
@@ -49,8 +49,6 @@ ENTITY unb1_bn_capture_input IS
);
PORT (
-- ADC Interface
- SCLK : IN STD_LOGIC := '0'; -- sample clk, use only for simulation purposes
-
-- . ADU_AB
ADC_BI_A : IN STD_LOGIC_VECTOR(g_ai.port_w-1 DOWNTO 0);
ADC_BI_B : IN STD_LOGIC_VECTOR(g_ai.port_w-1 DOWNTO 0);
@@ -427,7 +425,7 @@ BEGIN
g_ai => g_ai
)
PORT MAP (
- SCLK => SCLK,
+ DCLK => dp_clk,
sp_sosi_arr => dp_shiftram_src_out_timestamped_arr
);
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
index 612e1153e8..a4737f6db8 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
@@ -503,7 +503,6 @@ BEGIN
reg_bsn_scheduler_sp_off_miso => reg_bsn_scheduler_sp_off_miso,
-- ADC Interface
- SCLK => SCLK, -- sample clk, use only for simulation purposes
ADC_BI_A => DIG_A,
ADC_BI_B => DIG_B,
ADC_BI_A_CLK => DCLK_AB,
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
index e8ed6212cd..22c8436d08 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
@@ -556,8 +556,6 @@ BEGIN
)
PORT MAP (
-- ADC Interface
- SCLK => SCLK,
-
-- . ADU_AB
ADC_BI_A => DIG_A,
ADC_BI_B => DIG_B,
--
GitLab