diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
index 05b9b46690a6f7226b9b19979b4a2f53c4b00e62..6c1bc660a836abe667b8ea210891fad2ca7d15bc 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
@@ -127,7 +127,6 @@ ENTITY node_unb1_bn_capture IS
     -- >>> Node FPGA pins
     --
     -- ADC Interface
-    SCLK                      : IN    STD_LOGIC := '0';  -- sample clk, use only for simulation purposes
     ADC_BI_A                  : IN    STD_LOGIC_VECTOR(g_ai.port_w-1 DOWNTO 0);
     ADC_BI_B                  : IN    STD_LOGIC_VECTOR(g_ai.port_w-1 DOWNTO 0);
     ADC_BI_A_CLK              : IN    STD_LOGIC := '0';
@@ -200,8 +199,6 @@ BEGIN
   )
   PORT MAP (
     -- ADC Interface
-    SCLK                      => SCLK,
-    
     -- . ADU_AB
     ADC_BI_A                  => ADC_BI_A,
     ADC_BI_B                  => ADC_BI_B,
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
index 6b712b57c84ffeb4420094bebab4fff5be7d0706..be2f3249a588408475e03a0586c881d888d6d6c5 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
@@ -49,8 +49,6 @@ ENTITY unb1_bn_capture_input IS
   );
   PORT (
     -- ADC Interface
-    SCLK                      : IN  STD_LOGIC := '0';  -- sample clk, use only for simulation purposes
-    
     -- . ADU_AB
     ADC_BI_A                  : IN  STD_LOGIC_VECTOR(g_ai.port_w-1 DOWNTO 0);
     ADC_BI_B                  : IN  STD_LOGIC_VECTOR(g_ai.port_w-1 DOWNTO 0);
@@ -427,7 +425,7 @@ BEGIN
     g_ai   => g_ai
   )
   PORT MAP (
-    SCLK        => SCLK,
+    DCLK        => dp_clk,
     sp_sosi_arr => dp_shiftram_src_out_timestamped_arr
   );
   
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
index 612e1153e83501f9e189d65be4efd815bae0ee2b..a4737f6db8961b560a363d841959d449ca912f8b 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
@@ -503,7 +503,6 @@ BEGIN
     reg_bsn_scheduler_sp_off_miso => reg_bsn_scheduler_sp_off_miso,
  
     -- ADC Interface
-    SCLK                   => SCLK,  -- sample clk, use only for simulation purposes
     ADC_BI_A               => DIG_A,
     ADC_BI_B               => DIG_B,
     ADC_BI_A_CLK           => DCLK_AB,
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
index e8ed6212cd66910e46a6a80025c25caa93e34871..22c8436d08d32ea5b13866b63503ef4377d9bff3 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
@@ -556,8 +556,6 @@ BEGIN
   )
   PORT MAP (
     -- ADC Interface
-    SCLK                   => SCLK,
-    
     -- . ADU_AB
     ADC_BI_A               => DIG_A,
     ADC_BI_B               => DIG_B,