diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold
index 80806efb43bcce15c07ffad7edb9687ba4f0cc64..ed1a182056b30b5066dfc16fff58922795a68c6e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold
@@ -162,7 +162,7 @@ number_of_columns = 13
- - - - sdp_reserved 0x0004a008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x0004a009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x0004a00a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0004a00b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x0004a00b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x0004a00c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x0004a00d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x0004a00e 1 RW uint32 b[11:11] - - -
@@ -258,7 +258,7 @@ number_of_columns = 13
- - - - sdp_reserved 0x00062008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00062009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x0006200a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0006200b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x0006200b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x0006200c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x0006200d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x0006200e 1 RW uint32 b[11:11] - - -
@@ -469,4 +469,4 @@ number_of_columns = 13
- - - - - 0x00065c3d - - - b[31:0] b[31:0] - -
REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00066000 1 RO uint32 b[0:0] - - -
- - - - xgmii_tx_ready 0x00066000 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x00066000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+ - - - - xgmii_link_status 0x00066000 1 RO uint32 b[3:2] - - -
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
index 0d8cb073a23c16f2aa4eb27afa96274b6bbb812d..9856e5ebb9b87c3e649c3399e159b2f01cfa11da 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
@@ -172,7 +172,7 @@ number_of_columns = 13
- - - - sdp_reserved 0x000e8008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x000e8009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x000e800a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x000e800b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x000e800b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x000e800c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x000e800d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x000e800e 1 RW uint32 b[11:11] - - -
@@ -250,7 +250,7 @@ number_of_columns = 13
- - - - sdp_reserved 0x00128008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00128009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x0012800a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0012800b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x0012800b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x0012800c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x0012800d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x0012800e 1 RW uint32 b[11:11] - - -
@@ -581,7 +581,7 @@ number_of_columns = 13
- - - - sdp_reserved 0x001c0008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x001c0009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x001c000a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x001c000b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x001c000b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x001c000c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x001c000d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x001c000e 1 RW uint32 b[11:11] - - -
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
index 6915bff22bd7ff53bb9e91672a4c37bc50e957d6..3253fb922b7c60e2cc0572d7dcef0af660900a99 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
@@ -36,12 +36,18 @@ number_of_columns = 13
- - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
+<<<<<<< HEAD
REG_FPGA_TEMP_SENS 1 1 REG temp 0x00043238 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00043200 6 RO uint32 b[31:0] - - -
+=======
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x00043210 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x000431e0 6 RO uint32 b[31:0] - - -
+>>>>>>> master
RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
AVS_ETH_0_REG 1 1 REG status 0x000431b0 12 RO uint32 b[31:0] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
+<<<<<<< HEAD
PIO_PPS 1 1 REG capture_cnt 0x00043264 1 RO uint32 b[29:0] - - -
- - - - stable 0x00043264 1 RO uint32 b[30:30] - - -
- - - - toggle 0x00043264 1 RO uint32 b[31:31] - - -
@@ -81,6 +87,47 @@ number_of_columns = 13
- - - - o_rn 0x00043253 1 RW uint32 b[7:0] - - -
PIO_JESD_CTRL 1 1 REG enable 0x0004326e 1 RW uint32 b[30:0] - - -
- - - - reset 0x0004326e 1 RW uint32 b[31:31] - - -
+=======
+ PIO_PPS 1 1 REG capture_cnt 0x0004323c 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x0004323c 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x0004323c 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x0004323d 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x0004323d 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x0004323e 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x00043218 1 WO uint32 b[31:0] - - -
+ - - - - rden 0x00043219 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x0004321a 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x0004321b 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x0004321c 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x0004321d 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x0004321e 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x00043256 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x00043254 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x00043252 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x00043253 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x00043250 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x00043220 1 WO uint32 b[31:0] - - -
+ - - - - param 0x00043221 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x00043222 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x00043223 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x00043224 1 RO uint32 b[31:0] - - -
+ - - - - data_in 0x00043225 1 WO uint32 b[31:0] - - -
+ - - - - busy 0x00043226 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG block_period 0x000431d0 1 RO uint32 b[15:0] - - -
+ - - - - beam_repositioning_flag 0x000431d1 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x000431d2 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x000431d3 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x000431d4 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x000431d5 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x000431d6 1 RW uint32 b[0:0] - - -
+ - - - - station_id 0x000431d7 1 RW uint32 b[15:0] - - -
+ REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x00043228 1 RW uint32 b[0:0] - - -
+ - - - - use_cable_to_next_rn 0x00043229 1 RW uint32 b[0:0] - - -
+ - - - - n_rn 0x0004322a 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x0004322b 1 RW uint32 b[7:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x00043246 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x00043246 1 RW uint32 b[31:31] - - -
+>>>>>>> master
JESD204B 1 12 REG rx_lane_ctrl_common 0x00042000 1 RW uint32 b[2:0] - - 256
- - - - rx_lane_ctrl_0 0x00042001 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_1 0x00042002 1 RW uint32 b[2:0] - - -
@@ -119,6 +166,7 @@ number_of_columns = 13
- - - - rx_status6 0x0004203e 1 RW uint32 b[23:0] - - -
- - - - rx_status7 0x0004203f 1 RO uint32 b[31:0] - - -
REG_DP_SHIFTRAM 1 12 REG shift 0x00043180 1 RW uint32 b[11:0] - - 2
+<<<<<<< HEAD
REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00043230 1 RW uint32 b[0:0] - - -
- - - - dp_on_pps 0x00043230 1 RW uint32 b[1:1] - - -
- - - - nof_clk_per_sync 0x00043231 1 RW uint32 b[31:0] - - -
@@ -127,6 +175,16 @@ number_of_columns = 13
- - - - bsn_time_offset 0x00043234 1 RW uint32 b[9:0] - - -
REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00043274 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00043275 - - - b[31:0] b[63:32] - -
+=======
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00043208 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00043208 1 RW uint32 b[1:1] - - -
+ - - - - nof_clk_per_sync 0x00043209 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x0004320a 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004320b - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x0004320c 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x0004324c 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004324d - - - b[31:0] b[63:32] - -
+>>>>>>> master
REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
@@ -152,6 +210,7 @@ number_of_columns = 13
REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000c20 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x00000c21 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[31:0] b[15:0] - 1024
+<<<<<<< HEAD
REG_SI 1 1 REG enable 0x00043276 1 RW uint32 b[0:0] - - -
RAM_FIL_COEFS 1 16 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024
RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
@@ -159,6 +218,15 @@ number_of_columns = 13
RAM_ST_SST 1 6 RAM data 0x0003c000 1024 RW uint64 b[31:0] b[31:0] - 2048
- - - - - 0x0003c001 - - - b[21:0] b[53:32] - -
REG_STAT_ENABLE_SST 1 1 REG enable 0x0004326c 1 RW uint32 b[0:0] - - -
+=======
+ REG_SI 1 1 REG enable 0x0004324e 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 1 16 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x0004324a 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 6 RAM data 0x0003c000 1024 RW uint64 b[31:0] b[31:0] - 2048
+ - - - - - 0x0003c001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x00043244 1 RW uint32 b[0:0] - - -
+>>>>>>> master
REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
- - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - -
@@ -172,7 +240,7 @@ number_of_columns = 13
- - - - sdp_reserved 0x00000c48 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00000c49 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x00000c4a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x00000c4b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x00000c4b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x00000c4c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x00000c4d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x00000c4e 1 RW uint32 b[11:11] - - -
@@ -205,6 +273,7 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
- - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
+<<<<<<< HEAD
REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x00000c08 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00000c08 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000c08 1 RO uint32 b[2:2] - - -
@@ -226,15 +295,37 @@ number_of_columns = 13
- - - - mon_output_sync_bsn 0x000431d9 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x000431da - - - b[31:0] b[63:32] - -
- - - - block_size 0x000431db 1 RO uint32 b[31:0] - - -
+=======
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x000431b0 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x000431b1 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x000431b2 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431b3 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x000431b4 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431b5 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x000431b6 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431b7 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x000431b8 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x000431b9 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431ba - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x000431bb 1 RO uint32 b[31:0] - - -
+>>>>>>> master
RAM_ST_XSQ 1 9 RAM data 0x00010000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
- - - - - 0x00010001 - - - b[31:0] b[63:32] - -
- - - - - 0x00010002 - - - b[31:0] b[95:64] - -
- - - - - 0x00010003 - - - b[31:0] b[127:96] - -
+<<<<<<< HEAD
REG_CROSSLETS_INFO 1 1 REG offset 0x000431e0 15 RW uint32 b[31:0] - - -
- - - - step 0x000431ef 1 RW uint32 b[31:0] - - -
REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x00043268 1 RW uint32 b[31:0] - - -
- - - - unused 0x00043269 1 RW uint32 b[31:0] - - -
REG_STAT_ENABLE_XST 1 1 REG enable 0x0004326a 1 RW uint32 b[0:0] - - -
+=======
+ REG_CROSSLETS_INFO 1 1 REG offset 0x000431c0 15 RW uint32 b[31:0] - - -
+ - - - - step 0x000431cf 1 RW uint32 b[31:0] - - -
+ REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x00043240 1 RW uint32 b[31:0] - - -
+ - - - - unused 0x00043241 1 RW uint32 b[31:0] - - -
+ REG_STAT_ENABLE_XST 1 1 REG enable 0x00043242 1 RW uint32 b[0:0] - - -
+>>>>>>> master
REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000041 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
@@ -250,7 +341,7 @@ number_of_columns = 13
- - - - sdp_reserved 0x00000048 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00000049 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x0000004a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0000004b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x0000004b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x0000004c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x0000004d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x0000004e 1 RW uint32 b[11:11] - - -
@@ -294,6 +385,7 @@ number_of_columns = 13
- - - - nof_valid 0x00000d04 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000d05 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000d08 1 RO uint32 b[31:0] - - -
+<<<<<<< HEAD
REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT 1 1 REG xon_stable 0x00043228 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00043228 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00043228 1 RO uint32 b[2:2] - - -
@@ -312,6 +404,26 @@ number_of_columns = 13
- - - - nof_valid 0x00043224 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00043225 1 RO uint32 b[31:0] - - -
- - - - latency 0x00043228 1 RO uint32 b[31:0] - - -
+=======
+ REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT 1 1 REG xon_stable 0x00043200 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00043200 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043200 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043201 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043202 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043203 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043204 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043205 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043208 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x000431f8 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x000431f8 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x000431f8 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x000431f9 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431fa - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x000431fb 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x000431fc 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x000431fd 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043200 1 RO uint32 b[31:0] - - -
+>>>>>>> master
REG_RING_LANE_INFO_XST 1 1 REG lane_direction 0x00000c02 1 RO uint32 b[0:0] - - -
- - - - transport_nof_hops 0x00000c03 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_RX_XST 1 16 REG xon_stable 0x00000c80 1 RO uint32 b[0:0] - - 8
@@ -332,6 +444,7 @@ number_of_columns = 13
- - - - nof_valid 0x00000084 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000085 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000088 1 RO uint32 b[31:0] - - -
+<<<<<<< HEAD
REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x000431c0 8 RO uint32 b[31:0] - - -
- - - - total_discarded_blocks 0x000431c8 1 RO uint32 b[31:0] - - -
- - - - total_block_count 0x000431c9 1 RO uint32 b[31:0] - - -
@@ -339,6 +452,15 @@ number_of_columns = 13
REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x00043254 1 RO uint32 b[31:0] - - -
- - - - nof_sync 0x00043255 1 RO uint32 b[31:0] - - -
- - - - clear 0x00043256 1 RW uint32 b[31:0] - - -
+=======
+ REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x000431a0 8 RO uint32 b[31:0] - - -
+ - - - - total_discarded_blocks 0x000431a8 1 RO uint32 b[31:0] - - -
+ - - - - total_block_count 0x000431a9 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x000431aa 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x0004322c 1 RO uint32 b[31:0] - - -
+ - - - - nof_sync 0x0004322d 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x0004322e 1 RW uint32 b[31:0] - - -
+>>>>>>> master
REG_TR_10GBE_MAC 1 3 REG rx_transfer_control 0x00020000 1 RW uint32 b[0:0] - - 1
- - - - rx_transfer_status 0x00020001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00020002 1 RW uint32 b[0:0] - - -
@@ -515,6 +637,7 @@ number_of_columns = 13
- - - - - 0x00021c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00021c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00021c3d - - - b[31:0] b[31:0] - -
+<<<<<<< HEAD
REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x00043218 1 RO uint32 b[0:0] - - 1
- - - - xgmii_tx_ready 0x00043218 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x00043218 1 RO uint32 b[3:2] - - -
@@ -522,6 +645,15 @@ number_of_columns = 13
RAM_BF_WEIGHTS 2 12 RAM data 0x00028000 976 RW cint16_ir b[31:0] - 16384 1024
REG_BF_SCALE 2 1 REG scale 0x00043260 1 RW uint32 b[15:0] - 2 2
- - - - unused 0x00043261 1 RW uint32 b[31:0] - - -
+=======
+ REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x000431f0 1 RO uint32 b[0:0] - - 1
+ - - - - xgmii_tx_ready 0x000431f0 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x000431f0 1 RO uint32 b[3:2] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x00030000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00028000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BF_SCALE 2 1 REG scale 0x00043238 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x00043239 1 RW uint32 b[31:0] - - -
+>>>>>>> master
REG_HDR_DAT 2 1 REG bsn 0x00043000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - 0x00043001 - - - b[31:0] b[63:32] - -
- - - - sdp_block_period 0x00043002 1 RW uint32 b[15:0] - - -
@@ -564,10 +696,17 @@ number_of_columns = 13
- - - - - 0x00043027 - - - b[15:0] b[47:32] - -
- - - - eth_destination_mac 0x00043028 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00043029 - - - b[15:0] b[47:32] - -
+<<<<<<< HEAD
REG_DP_XONOFF 2 1 REG enable_stream 0x0004325c 1 RW uint32 b[0:0] - 2 2
RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - 0x00001001 - - - b[21:0] b[53:32] - -
REG_STAT_ENABLE_BST 2 1 REG enable 0x00043258 1 RW uint32 b[0:0] - 2 2
+=======
+ REG_DP_XONOFF 2 1 REG enable_stream 0x00043234 1 RW uint32 b[0:0] - 2 2
+ RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
+ - - - - - 0x00001001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x00043230 1 RW uint32 b[0:0] - 2 2
+>>>>>>> master
REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000d80 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - 0x00000d81 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00000d82 1 RW uint32 b[15:0] - - -
@@ -581,7 +720,7 @@ number_of_columns = 13
- - - - sdp_reserved 0x00000d88 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00000d89 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x00000d8a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x00000d8b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x00000d8b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x00000d8c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x00000d8d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x00000d8e 1 RW uint32 b[11:11] - - -
@@ -614,6 +753,7 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000da9 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000daa - - - b[15:0] b[47:32] - -
- - - - word_align 0x00000dab 1 RW uint32 b[15:0] - - -
+<<<<<<< HEAD
REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x000431a0 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x000431a0 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x000431a0 1 RO uint32 b[2:2] - - -
@@ -632,6 +772,8 @@ number_of_columns = 13
- - - - nof_valid 0x00000c14 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000c15 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000c18 1 RO uint32 b[31:0] - - -
+=======
+>>>>>>> master
REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00006000 1 RW uint32 b[0:0] - - -
- - - - rx_transfer_status 0x00006001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00006002 1 RW uint32 b[0:0] - - -
@@ -808,6 +950,12 @@ number_of_columns = 13
- - - - - 0x00007c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00007c3d - - - b[31:0] b[31:0] - -
+<<<<<<< HEAD
REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00043270 1 RO uint32 b[0:0] - - -
- - - - xgmii_tx_ready 0x00043270 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x00043270 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+ - - - - xgmii_link_status 0x00043270 1 RO uint32 b[3:2] - - -
+=======
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00043248 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x00043248 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00043248 1 RO uint32 b[3:2] - - -
+>>>>>>> master
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold
index 5c7324b7afe6cace73257a58d726458b5f7f2f1f..bb5e1c60b07eb748f8bac3d413330558ce60ceb8 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold
@@ -172,7 +172,11 @@ number_of_columns = 13
- - - - sdp_reserved 0x000e8008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x000e8009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x000e800a 1 RW uint32 b[7:5] - - -
+<<<<<<< HEAD
- - - - sdp_source_info_subband_calibrated_flag 0x000e800b 1 RW uint32 b[8:8] - - -
+=======
+ - - - - sdp_source_info_weighted_subbands_flag 0x000e800b 1 RW uint32 b[8:8] - - -
+>>>>>>> master
- - - - sdp_source_info_beam_repositioning_flag 0x000e800c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x000e800d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x000e800e 1 RW uint32 b[11:11] - - -
@@ -205,6 +209,7 @@ number_of_columns = 13
- - - - eth_destination_mac 0x000e8029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x000e802a - - - b[15:0] b[47:32] - -
- - - - word_align 0x000e802b 1 RW uint32 b[15:0] - - -
+<<<<<<< HEAD
REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x000f0000 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x000f0000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x000f0000 1 RO uint32 b[2:2] - - -
@@ -226,6 +231,20 @@ number_of_columns = 13
- - - - mon_output_sync_bsn 0x000f8009 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x000f800a - - - b[31:0] b[63:32] - -
- - - - block_size 0x000f800b 1 RO uint32 b[31:0] - - -
+=======
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x000f0000 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x000f0001 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x000f0002 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000f0003 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x000f0004 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000f0005 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x000f0006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000f0007 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x000f0008 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x000f0009 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000f000a - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x000f000b 1 RO uint32 b[31:0] - - -
+>>>>>>> master
RAM_ST_XSQ 1 9 RAM data 0x00100000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
- - - - - 0x00100001 - - - b[31:0] b[63:32] - -
- - - - - 0x00100002 - - - b[31:0] b[95:64] - -
@@ -250,7 +269,11 @@ number_of_columns = 13
- - - - sdp_reserved 0x00128008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00128009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x0012800a 1 RW uint32 b[7:5] - - -
+<<<<<<< HEAD
- - - - sdp_source_info_subband_calibrated_flag 0x0012800b 1 RW uint32 b[8:8] - - -
+=======
+ - - - - sdp_source_info_weighted_subbands_flag 0x0012800b 1 RW uint32 b[8:8] - - -
+>>>>>>> master
- - - - sdp_source_info_beam_repositioning_flag 0x0012800c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x0012800d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x0012800e 1 RW uint32 b[11:11] - - -
@@ -581,7 +604,11 @@ number_of_columns = 13
- - - - sdp_reserved 0x001c0008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x001c0009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x001c000a 1 RW uint32 b[7:5] - - -
+<<<<<<< HEAD
- - - - sdp_source_info_subband_calibrated_flag 0x001c000b 1 RW uint32 b[8:8] - - -
+=======
+ - - - - sdp_source_info_weighted_subbands_flag 0x001c000b 1 RW uint32 b[8:8] - - -
+>>>>>>> master
- - - - sdp_source_info_beam_repositioning_flag 0x001c000c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x001c000d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x001c000e 1 RW uint32 b[11:11] - - -
@@ -614,6 +641,7 @@ number_of_columns = 13
- - - - eth_destination_mac 0x001c0029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x001c002a - - - b[15:0] b[47:32] - -
- - - - word_align 0x001c002b 1 RW uint32 b[15:0] - - -
+<<<<<<< HEAD
REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x001c8000 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x001c8000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001c8000 1 RO uint32 b[2:2] - - -
@@ -810,4 +838,185 @@ number_of_columns = 13
- - - - - 0x001d9c3d - - - b[31:0] b[31:0] - -
REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x001e0000 1 RO uint32 b[0:0] - - -
- - - - xgmii_tx_ready 0x001e0000 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x001e0000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+ - - - - xgmii_link_status 0x001e0000 1 RO uint32 b[3:2] - - -
+=======
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x001c8000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x001c8001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x001c8002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x001c8040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x001c8080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x001c80c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c80c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x001c80c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c80c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x001c8100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x001c8140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x001c8800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x001c8801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x001c8802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x001c8803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x001c8804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x001c8805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x001c8806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x001c8807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x001c8808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x001c8809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x001c880a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x001c880b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x001c8818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x001c8c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x001c8c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x001c8c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x001c8c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x001c8c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x001c8c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x001c8c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x001c8c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x001c8c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x001c8c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x001c8c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x001c8c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x001c8c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x001c8c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x001c8c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x001c8c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x001c8c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x001c8c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x001c8c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x001c8c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x001c8c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x001c8c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x001c8c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x001c8c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x001c8c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x001c8c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x001c8c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x001c8c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x001c8c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x001c8c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x001c8c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c8c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x001c9001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x001c9040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x001c9080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x001c90c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c90c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x001c9100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x001c9140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x001c9141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x001c9142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x001c9180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x001c9181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x001c9182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x001c9183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x001c9184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x001c9185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x001c9186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x001c9187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x001c9190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x001c9191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x001c9192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x001c9193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x001c9194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x001c9195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x001c9196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x001c9197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x001c91a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x001c9200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x001c9201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x001c9202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x001c9801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x001c9c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x001c9c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x001c9c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x001c9c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x001c9c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x001c9c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x001c9c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x001c9c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x001c9c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x001c9c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x001c9c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x001c9c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x001c9c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x001c9c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x001c9c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x001c9c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x001c9c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x001c9c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x001c9c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x001c9c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x001c9c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x001c9c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x001c9c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x001c9c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x001c9c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x001c9c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x001c9c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x001c9c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x001c9c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x001c9c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x001c9c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001c9c3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x001d0000 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x001d0000 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x001d0000 1 RO uint32 b[3:2] - - -
+>>>>>>> master
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold
index 1fb69eb3aef31244dc615f1a3f5e45a3a887e77e..478ac1046925de486a4bde05b8e2b44a1c46d303 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold
@@ -36,6 +36,7 @@ number_of_columns = 13
- - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
+<<<<<<< HEAD
REG_FPGA_TEMP_SENS 1 1 REG temp 0x000431b8 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00043180 6 RO uint32 b[31:0] - - -
RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
@@ -81,6 +82,53 @@ number_of_columns = 13
- - - - o_rn 0x000431d3 1 RW uint32 b[7:0] - - -
PIO_JESD_CTRL 1 1 REG enable 0x000431ee 1 RW uint32 b[30:0] - - -
- - - - reset 0x000431ee 1 RW uint32 b[31:31] - - -
+=======
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x00043190 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00043160 6 RO uint32 b[31:0] - - -
+ RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
+ AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x00000c10 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x000431bc 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x000431bc 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x000431bc 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x000431bd 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x000431bd 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x000431be 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x00043198 1 WO uint32 b[31:0] - - -
+ - - - - rden 0x00043199 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x0004319a 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x0004319b 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x0004319c 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x0004319d 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x0004319e 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x000431d6 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x000431d4 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x000431d2 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x000431d3 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x000431d0 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x000431a0 1 WO uint32 b[31:0] - - -
+ - - - - param 0x000431a1 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x000431a2 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x000431a3 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x000431a4 1 RO uint32 b[31:0] - - -
+ - - - - data_in 0x000431a5 1 WO uint32 b[31:0] - - -
+ - - - - busy 0x000431a6 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG block_period 0x00043150 1 RO uint32 b[15:0] - - -
+ - - - - beam_repositioning_flag 0x00043151 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x00043152 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x00043153 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x00043154 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x00043155 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x00043156 1 RW uint32 b[0:0] - - -
+ - - - - station_id 0x00043157 1 RW uint32 b[15:0] - - -
+ REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x000431a8 1 RW uint32 b[0:0] - - -
+ - - - - use_cable_to_next_rn 0x000431a9 1 RW uint32 b[0:0] - - -
+ - - - - n_rn 0x000431aa 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x000431ab 1 RW uint32 b[7:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x000431c6 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x000431c6 1 RW uint32 b[31:31] - - -
+>>>>>>> master
JESD204B 1 12 REG rx_lane_ctrl_common 0x00042000 1 RW uint32 b[2:0] - - 256
- - - - rx_lane_ctrl_0 0x00042001 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_1 0x00042002 1 RW uint32 b[2:0] - - -
@@ -119,6 +167,7 @@ number_of_columns = 13
- - - - rx_status6 0x0004203e 1 RW uint32 b[23:0] - - -
- - - - rx_status7 0x0004203f 1 RO uint32 b[31:0] - - -
REG_DP_SHIFTRAM 1 12 REG shift 0x00043100 1 RW uint32 b[11:0] - - 2
+<<<<<<< HEAD
REG_BSN_SOURCE_V2 1 1 REG dp_on 0x000431b0 1 RW uint32 b[0:0] - - -
- - - - dp_on_pps 0x000431b0 1 RW uint32 b[1:1] - - -
- - - - nof_clk_per_sync 0x000431b1 1 RW uint32 b[31:0] - - -
@@ -127,6 +176,16 @@ number_of_columns = 13
- - - - bsn_time_offset 0x000431b4 1 RW uint32 b[9:0] - - -
REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x000431f4 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x000431f5 - - - b[31:0] b[63:32] - -
+=======
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00043188 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00043188 1 RW uint32 b[1:1] - - -
+ - - - - nof_clk_per_sync 0x00043189 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x0004318a 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004318b - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x0004318c 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x000431cc 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431cd - - - b[31:0] b[63:32] - -
+>>>>>>> master
REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
@@ -152,6 +211,7 @@ number_of_columns = 13
REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000c20 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x00000c21 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[31:0] b[15:0] - 1024
+<<<<<<< HEAD
REG_SI 1 1 REG enable 0x000431f6 1 RW uint32 b[0:0] - - -
RAM_FIL_COEFS 1 16 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024
RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
@@ -159,6 +219,15 @@ number_of_columns = 13
RAM_ST_SST 1 6 RAM data 0x0003c000 1024 RW uint64 b[31:0] b[31:0] - 2048
- - - - - 0x0003c001 - - - b[21:0] b[53:32] - -
REG_STAT_ENABLE_SST 1 1 REG enable 0x000431ec 1 RW uint32 b[0:0] - - -
+=======
+ REG_SI 1 1 REG enable 0x000431ce 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 1 16 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x000431ca 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 6 RAM data 0x0003c000 1024 RW uint64 b[31:0] b[31:0] - 2048
+ - - - - - 0x0003c001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x000431c4 1 RW uint32 b[0:0] - - -
+>>>>>>> master
REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
- - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - -
@@ -172,7 +241,11 @@ number_of_columns = 13
- - - - sdp_reserved 0x00000c48 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00000c49 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x00000c4a 1 RW uint32 b[7:5] - - -
+<<<<<<< HEAD
- - - - sdp_source_info_subband_calibrated_flag 0x00000c4b 1 RW uint32 b[8:8] - - -
+=======
+ - - - - sdp_source_info_weighted_subbands_flag 0x00000c4b 1 RW uint32 b[8:8] - - -
+>>>>>>> master
- - - - sdp_source_info_beam_repositioning_flag 0x00000c4c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x00000c4d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x00000c4e 1 RW uint32 b[11:11] - - -
@@ -205,6 +278,7 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
- - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
+<<<<<<< HEAD
REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x00000c08 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00000c08 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000c08 1 RO uint32 b[2:2] - - -
@@ -226,15 +300,37 @@ number_of_columns = 13
- - - - mon_output_sync_bsn 0x00043159 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x0004315a - - - b[31:0] b[63:32] - -
- - - - block_size 0x0004315b 1 RO uint32 b[31:0] - - -
+=======
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x00043130 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x00043131 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x00043132 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043133 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x00043134 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043135 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x00043136 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043137 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x00043138 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x00043139 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004313a - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x0004313b 1 RO uint32 b[31:0] - - -
+>>>>>>> master
RAM_ST_XSQ 1 9 RAM data 0x00010000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
- - - - - 0x00010001 - - - b[31:0] b[63:32] - -
- - - - - 0x00010002 - - - b[31:0] b[95:64] - -
- - - - - 0x00010003 - - - b[31:0] b[127:96] - -
+<<<<<<< HEAD
REG_CROSSLETS_INFO 1 1 REG offset 0x00043160 15 RW uint32 b[31:0] - - -
- - - - step 0x0004316f 1 RW uint32 b[31:0] - - -
REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x000431e8 1 RW uint32 b[31:0] - - -
- - - - unused 0x000431e9 1 RW uint32 b[31:0] - - -
REG_STAT_ENABLE_XST 1 1 REG enable 0x000431ea 1 RW uint32 b[0:0] - - -
+=======
+ REG_CROSSLETS_INFO 1 1 REG offset 0x00043140 15 RW uint32 b[31:0] - - -
+ - - - - step 0x0004314f 1 RW uint32 b[31:0] - - -
+ REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x000431c0 1 RW uint32 b[31:0] - - -
+ - - - - unused 0x000431c1 1 RW uint32 b[31:0] - - -
+ REG_STAT_ENABLE_XST 1 1 REG enable 0x000431c2 1 RW uint32 b[0:0] - - -
+>>>>>>> master
REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000041 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
@@ -250,7 +346,11 @@ number_of_columns = 13
- - - - sdp_reserved 0x00000048 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00000049 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x0000004a 1 RW uint32 b[7:5] - - -
+<<<<<<< HEAD
- - - - sdp_source_info_subband_calibrated_flag 0x0000004b 1 RW uint32 b[8:8] - - -
+=======
+ - - - - sdp_source_info_weighted_subbands_flag 0x0000004b 1 RW uint32 b[8:8] - - -
+>>>>>>> master
- - - - sdp_source_info_beam_repositioning_flag 0x0000004c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x0000004d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x0000004e 1 RW uint32 b[11:11] - - -
@@ -294,6 +394,7 @@ number_of_columns = 13
- - - - nof_valid 0x00000084 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000085 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000088 1 RO uint32 b[31:0] - - -
+<<<<<<< HEAD
REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT 1 1 REG xon_stable 0x000431a8 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x000431a8 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x000431a8 1 RO uint32 b[2:2] - - -
@@ -312,6 +413,26 @@ number_of_columns = 13
- - - - nof_valid 0x000431a4 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x000431a5 1 RO uint32 b[31:0] - - -
- - - - latency 0x000431a8 1 RO uint32 b[31:0] - - -
+=======
+ REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT 1 1 REG xon_stable 0x00043180 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00043180 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043180 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043181 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043182 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043183 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043184 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043185 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043188 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x00043178 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00043178 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043178 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043179 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004317a - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x0004317b 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x0004317c 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x0004317d 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043180 1 RO uint32 b[31:0] - - -
+>>>>>>> master
REG_RING_LANE_INFO_XST 1 1 REG lane_direction 0x00000c02 1 RO uint32 b[0:0] - - -
- - - - transport_nof_hops 0x00000c03 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_RX_XST 1 16 REG xon_stable 0x00000d00 1 RO uint32 b[0:0] - - 8
@@ -332,6 +453,7 @@ number_of_columns = 13
- - - - nof_valid 0x00000c84 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000c85 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000c88 1 RO uint32 b[31:0] - - -
+<<<<<<< HEAD
REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x00043140 8 RO uint32 b[31:0] - - -
- - - - total_discarded_blocks 0x00043148 1 RO uint32 b[31:0] - - -
- - - - total_block_count 0x00043149 1 RO uint32 b[31:0] - - -
@@ -339,6 +461,15 @@ number_of_columns = 13
REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x000431d4 1 RO uint32 b[31:0] - - -
- - - - nof_sync 0x000431d5 1 RO uint32 b[31:0] - - -
- - - - clear 0x000431d6 1 RW uint32 b[31:0] - - -
+=======
+ REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x00043120 8 RO uint32 b[31:0] - - -
+ - - - - total_discarded_blocks 0x00043128 1 RO uint32 b[31:0] - - -
+ - - - - total_block_count 0x00043129 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x0004312a 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x000431ac 1 RO uint32 b[31:0] - - -
+ - - - - nof_sync 0x000431ad 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x000431ae 1 RW uint32 b[31:0] - - -
+>>>>>>> master
REG_TR_10GBE_MAC 1 3 REG rx_transfer_control 0x00020000 1 RW uint32 b[0:0] - - 1
- - - - rx_transfer_status 0x00020001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00020002 1 RW uint32 b[0:0] - - -
@@ -515,6 +646,7 @@ number_of_columns = 13
- - - - - 0x00021c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00021c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00021c3d - - - b[31:0] b[31:0] - -
+<<<<<<< HEAD
REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x00043198 1 RO uint32 b[0:0] - - 1
- - - - xgmii_tx_ready 0x00043198 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x00043198 1 RO uint32 b[3:2] - - -
@@ -522,6 +654,15 @@ number_of_columns = 13
RAM_BF_WEIGHTS 2 12 RAM data 0x00028000 976 RW cint16_ir b[31:0] - 16384 1024
REG_BF_SCALE 2 1 REG scale 0x000431e0 1 RW uint32 b[15:0] - 2 2
- - - - unused 0x000431e1 1 RW uint32 b[31:0] - - -
+=======
+ REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x00043170 1 RO uint32 b[0:0] - - 1
+ - - - - xgmii_tx_ready 0x00043170 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00043170 1 RO uint32 b[3:2] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x00030000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00028000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BF_SCALE 2 1 REG scale 0x000431b8 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x000431b9 1 RW uint32 b[31:0] - - -
+>>>>>>> master
REG_HDR_DAT 2 1 REG bsn 0x00043000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - 0x00043001 - - - b[31:0] b[63:32] - -
- - - - sdp_block_period 0x00043002 1 RW uint32 b[15:0] - - -
@@ -564,10 +705,17 @@ number_of_columns = 13
- - - - - 0x00043027 - - - b[15:0] b[47:32] - -
- - - - eth_destination_mac 0x00043028 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00043029 - - - b[15:0] b[47:32] - -
+<<<<<<< HEAD
REG_DP_XONOFF 2 1 REG enable_stream 0x000431dc 1 RW uint32 b[0:0] - 2 2
RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - 0x00001001 - - - b[21:0] b[53:32] - -
REG_STAT_ENABLE_BST 2 1 REG enable 0x000431d8 1 RW uint32 b[0:0] - 2 2
+=======
+ REG_DP_XONOFF 2 1 REG enable_stream 0x000431b4 1 RW uint32 b[0:0] - 2 2
+ RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
+ - - - - - 0x00001001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x000431b0 1 RW uint32 b[0:0] - 2 2
+>>>>>>> master
REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000d80 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - 0x00000d81 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00000d82 1 RW uint32 b[15:0] - - -
@@ -581,7 +729,11 @@ number_of_columns = 13
- - - - sdp_reserved 0x00000d88 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00000d89 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x00000d8a 1 RW uint32 b[7:5] - - -
+<<<<<<< HEAD
- - - - sdp_source_info_subband_calibrated_flag 0x00000d8b 1 RW uint32 b[8:8] - - -
+=======
+ - - - - sdp_source_info_weighted_subbands_flag 0x00000d8b 1 RW uint32 b[8:8] - - -
+>>>>>>> master
- - - - sdp_source_info_beam_repositioning_flag 0x00000d8c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x00000d8d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x00000d8e 1 RW uint32 b[11:11] - - -
@@ -614,6 +766,7 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000da9 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000daa - - - b[15:0] b[47:32] - -
- - - - word_align 0x00000dab 1 RW uint32 b[15:0] - - -
+<<<<<<< HEAD
REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x00043120 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x00043120 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00043120 1 RO uint32 b[2:2] - - -
@@ -632,6 +785,8 @@ number_of_columns = 13
- - - - nof_valid 0x00000c14 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000c15 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000c18 1 RO uint32 b[31:0] - - -
+=======
+>>>>>>> master
REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00006000 1 RW uint32 b[0:0] - - -
- - - - rx_transfer_status 0x00006001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00006002 1 RW uint32 b[0:0] - - -
@@ -808,6 +963,12 @@ number_of_columns = 13
- - - - - 0x00007c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00007c3d - - - b[31:0] b[31:0] - -
+<<<<<<< HEAD
REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x000431f0 1 RO uint32 b[0:0] - - -
- - - - xgmii_tx_ready 0x000431f0 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x000431f0 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+ - - - - xgmii_link_status 0x000431f0 1 RO uint32 b[3:2] - - -
+=======
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x000431c8 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x000431c8 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x000431c8 1 RO uint32 b[3:2] - - -
+>>>>>>> master
diff --git a/applications/lofar2/images/images.txt b/applications/lofar2/images/images.txt
index f7f918986067a2bf413c825c81765dbde587689c..3bb32ccaf12e27a9c58f000aa8de24560bd3312d 100644
--- a/applications/lofar2/images/images.txt
+++ b/applications/lofar2/images/images.txt
@@ -10,4 +10,4 @@ lofar2_unb2b_sdp_station_bf-r087d98be6 | 2021-06-14 | R vd Walle
lofar2_unb2b_sdp_station_xsub_one-r087d98be6 | 2021-06-14 | R vd Walle |
unb2b_minimal-rce6b96eed | 2021-08-26 | P. Donker | unb2b_minimal with new mmap, rbf maid with option --unb2_factory
lofar2_unb2b_sdp_station_full-r9ff51058a | 2022-01-12 | R vd Walle | Lofar2 SDP station full design for UniBoard2b.
-lofar2_unb2c_sdp_station_full-rfc9844d8e | 2021-12-16 | R vd Walle | Lofar2 SDP station full design for UniBoard2c.
+lofar2_unb2c_sdp_station_full-r802d1d5ea | 2022-02-25 | R vd Walle | Lofar2 SDP station full design for UniBoard2c.
diff --git a/applications/lofar2/images/lofar2_unb2c_sdp_station_full-rfc9844d8e.tar.gz b/applications/lofar2/images/lofar2_unb2c_sdp_station_full-r802d1d5ea.tar.gz
similarity index 53%
rename from applications/lofar2/images/lofar2_unb2c_sdp_station_full-rfc9844d8e.tar.gz
rename to applications/lofar2/images/lofar2_unb2c_sdp_station_full-r802d1d5ea.tar.gz
index f57442d780cbf0b76b04a15594fa222704b02c19..58864b419c6b622772248c562c9f6a7144a345a3 100644
Binary files a/applications/lofar2/images/lofar2_unb2c_sdp_station_full-rfc9844d8e.tar.gz and b/applications/lofar2/images/lofar2_unb2c_sdp_station_full-r802d1d5ea.tar.gz differ
diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
index e45e1d737a5f1ea3b1f1cdff74bdc333e9a3e6b9..94c9ce8b457e0347216606a067062f7a58981f36 100644
--- a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -303,7 +303,7 @@ peripherals:
- - { field_name: sdp_source_info_fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x38 }
- - { field_name: sdp_source_info_payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x34 }
- - { field_name: sdp_source_info_beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x30 }
- - - { field_name: sdp_source_info_subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: sdp_source_info_weighted_subbands_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
- - { field_name: sdp_source_info_reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x28 }
- - { field_name: sdp_source_info_gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
- - { field_name: sdp_reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
@@ -372,7 +372,7 @@ peripherals:
- - { field_name: sdp_source_info_fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x38 }
- - { field_name: sdp_source_info_payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x34 }
- - { field_name: sdp_source_info_beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x30 }
- - - { field_name: sdp_source_info_subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: sdp_source_info_weighted_subbands_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
- - { field_name: sdp_source_info_reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x28 }
- - { field_name: sdp_source_info_gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
- - { field_name: sdp_reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
@@ -442,7 +442,7 @@ peripherals:
- - { field_name: sdp_source_info_fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x38 }
- - { field_name: sdp_source_info_payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x34 }
- - { field_name: sdp_source_info_beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x30 }
- - - { field_name: sdp_source_info_subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: sdp_source_info_weighted_subbands_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
- - { field_name: sdp_source_info_reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x28 }
- - { field_name: sdp_source_info_gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
- - { field_name: sdp_reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
index f2655a56359a21d22b89c112ecc9ac8a44cc0447..ebe6a0d76da72e26fc87d3ca54549cac67ba3189 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
@@ -344,8 +344,9 @@ BEGIN
udp_src_port => stat_udp_src_port,
ip_src_addr => stat_ip_src_addr,
+ gn_index => TO_UINT(gn_id),
sdp_info => sdp_info,
- gn_index => TO_UINT(gn_id)
+ weighted_subbands_flag => '1' -- because BF uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
);
---------------------------------------------------------------
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index 4a0ad75b512b560e095066e0f5b7cf3df80c230a..ec8180f396e3c3a6837878b26792c6f01f29274b 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -471,6 +471,7 @@ BEGIN
gn_index => TO_UINT(gn_id),
ring_info => ring_info,
sdp_info => sdp_info,
+ weighted_subbands_flag => '1', -- because XSub uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
nof_crosslets => nof_crosslets,
crosslets_info => crosslets_info
);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index dddef0eb92b56a52d0b045b5c42c685d70d8b172..149139e4ff79a3462f14bd6dca06c117677577dc 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -126,7 +126,7 @@ ARCHITECTURE str OF node_sdp_filterbank IS
SIGNAL scope_sosi_arr : t_dp_sosi_integer_arr(c_sdp_S_pn-1 DOWNTO 0);
SIGNAL selector_en : STD_LOGIC;
- SIGNAL subband_calibrated_flag : STD_LOGIC;
+ SIGNAL weighted_subbands_flag : STD_LOGIC;
SIGNAL dp_bsn_source_restart_pipe : STD_LOGIC;
BEGIN
---------------------------------------------------------------
@@ -333,7 +333,7 @@ BEGIN
---------------------------------------------------------------
-- STATISTICS OFFLOAD
---------------------------------------------------------------
- subband_calibrated_flag <= NOT selector_en;
+ weighted_subbands_flag <= NOT selector_en;
u_sdp_sst_udp_offload: ENTITY work.sdp_statistics_offload
GENERIC MAP (
@@ -369,7 +369,7 @@ BEGIN
gn_index => TO_UINT(gn_id),
sdp_info => sdp_info,
- subband_calibrated_flag => subband_calibrated_flag
+ weighted_subbands_flag => weighted_subbands_flag
);
END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
index 1b4d1753f9c49ad38b28390d1df7906969393848..94347aaca1aeccb0c0ed9efed5a10b24fbc668e3 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
@@ -61,7 +61,6 @@ ENTITY sdp_crosslets_subband_select IS
reg_bsn_sync_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
out_crosslets_info : OUT STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0)
-
);
END sdp_crosslets_subband_select;
@@ -105,6 +104,7 @@ ARCHITECTURE str OF sdp_crosslets_subband_select IS
SIGNAL crosslets_info_reg : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL crosslets_info_reg_in : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL active_crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL i_out_crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------------------------------------------------
@@ -152,9 +152,11 @@ BEGIN
in_reg => crosslets_info_reg_in,
out_reg => crosslets_info_reg
);
- p_set_unused_crosslets : PROCESS(crosslets_info_reg)
+
+ p_set_unused_crosslets : PROCESS(i_out_crosslets_info)
BEGIN
- crosslets_info_reg_in <= crosslets_info_reg; -- Always use crosslets info 6:0 + step(@ index 15)
+ -- MM readback the currently active crosslets info, instead of the initial MM written crosslets_info_reg
+ crosslets_info_reg_in <= i_out_crosslets_info; -- Always use crosslets info 6:0 + step(@ index 15)
-- Set crosslets 14:7 to -1
FOR I IN g_N_crosslets TO c_sdp_mm_reg_crosslets_info.nof_dat - 2 LOOP
crosslets_info_reg_in((I+1) * c_sdp_crosslets_index_w - 1 DOWNTO I * c_sdp_crosslets_index_w ) <= TO_SVEC(-1, c_sdp_crosslets_index_w);
@@ -309,6 +311,7 @@ BEGIN
gen_crosslets_info : FOR I IN 0 TO g_N_crosslets-1 GENERATE
active_crosslets_info((I+1)*c_sdp_crosslets_index_w-1 DOWNTO I*c_sdp_crosslets_index_w) <= TO_UVEC(r.offsets(I), c_sdp_crosslets_index_w);
END GENERATE;
+
-- pipeline for alignment with sync
u_common_pipeline : ENTITY common_lib.common_pipeline
GENERIC MAP(
@@ -321,9 +324,11 @@ BEGIN
clk => dp_clk,
in_en => row_sosi.sync,
in_dat => active_crosslets_info,
- out_dat => out_crosslets_info
+ out_dat => i_out_crosslets_info
);
+ out_crosslets_info <= i_out_crosslets_info;
+
---------------------------------------------------------------
-- Out sosi pipeline
---------------------------------------------------------------
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 509a77e8feb7a0bd96a5cb469637e1cf1398a3ba..4c874ce5c9eea26ef903b5a1caff0d9c71acda3c 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -77,7 +77,7 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_N_sub : NATURAL := 512;
CONSTANT c_sdp_N_sync_rcu : NATURAL := 1;
CONSTANT c_sdp_N_taps : NATURAL := 16;
- CONSTANT c_sdp_P_sq : NATURAL := 9;
+ CONSTANT c_sdp_P_sq : NATURAL := 9; -- = N_pn / 2 + 1
CONSTANT c_sdp_Q_fft : NATURAL := 2;
CONSTANT c_sdp_S_pn : NATURAL := 12;
CONSTANT c_sdp_S_rcu : NATURAL := 3;
@@ -115,10 +115,10 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_N_sync_jesd : NATURAL := c_sdp_S_pn * c_sdp_N_sync_rcu / c_sdp_S_rcu; -- = 4, nof JESD IP sync outputs per PN
CONSTANT c_sdp_A_pn : NATURAL := c_sdp_S_pn / c_sdp_N_pol; -- = 6 dual pol antenna per PN, is 6 signal input pairs
CONSTANT c_sdp_P_pfb : NATURAL := c_sdp_S_pn / c_sdp_Q_fft; -- = 6 PFB units, for 6 signal input pairs
- CONSTANT c_sdp_T_adc : TIME := (10**6 / c_sdp_f_adc_MHz) * 1 ps;
- CONSTANT c_sdp_T_sub : TIME := c_sdp_N_fft * c_sdp_T_adc;
+ CONSTANT c_sdp_T_adc : TIME := (10**6 / c_sdp_f_adc_MHz) * 1 ps; -- = 5 ns @ 200MHz
+ CONSTANT c_sdp_T_sub : TIME := c_sdp_N_fft * c_sdp_T_adc; -- = 5.12 us @ 200MHz
CONSTANT c_sdp_W_bf_product : NATURAL := c_sdp_W_subband + c_sdp_W_bf_weight -1;
- CONSTANT c_sdp_X_sq : NATURAL := c_sdp_S_pn * c_sdp_S_pn;
+ CONSTANT c_sdp_X_sq : NATURAL := c_sdp_S_pn * c_sdp_S_pn; -- = 144
CONSTANT c_sdp_block_period : NATURAL := c_sdp_N_fft * 1000 / c_sdp_f_adc_MHz; -- = 5120 [ns]
CONSTANT c_sdp_N_beamlets_sdp : NATURAL := c_sdp_N_beamsets * c_sdp_S_sub_bf; -- = 976
CONSTANT c_sdp_unit_sub_weight : NATURAL := 2**c_sdp_W_sub_weight_fraction; -- 2**13, so range +-4.0 for 16 bit signed weight
@@ -224,7 +224,7 @@ PACKAGE sdp_pkg is
( field_name_pad("sdp_source_info_fsub_type" ), "RW", 1, field_default(0) ),
( field_name_pad("sdp_source_info_payload_error" ), "RW", 1, field_default(0) ),
( field_name_pad("sdp_source_info_beam_repositioning_flag" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_subband_calibrated_flag" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_weighted_subbands_flag" ), "RW", 1, field_default(0) ),
( field_name_pad("sdp_source_info_reserved" ), "RW", 3, field_default(0) ),
( field_name_pad("sdp_source_info_gn_id" ), "RW", 5, field_default(0) ),
@@ -252,7 +252,7 @@ PACKAGE sdp_pkg is
sdp_source_info_fsub_type : STD_LOGIC_VECTOR( 0 DOWNTO 0);
sdp_source_info_payload_error : STD_LOGIC_VECTOR( 0 DOWNTO 0);
sdp_source_info_beam_repositioning_flag : STD_LOGIC_VECTOR( 0 DOWNTO 0);
- sdp_source_info_subband_calibrated_flag : STD_LOGIC_VECTOR( 0 DOWNTO 0);
+ sdp_source_info_weighted_subbands_flag : STD_LOGIC_VECTOR( 0 DOWNTO 0);
sdp_source_info_reserved : STD_LOGIC_VECTOR( 2 DOWNTO 0);
sdp_source_info_gn_id : STD_LOGIC_VECTOR( 4 DOWNTO 0);
@@ -724,7 +724,7 @@ PACKAGE BODY sdp_pkg IS
v.app.sdp_source_info_fsub_type := hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_fsub_type") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_fsub_type"));
v.app.sdp_source_info_payload_error := hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_payload_error") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_payload_error"));
v.app.sdp_source_info_beam_repositioning_flag := hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_beam_repositioning_flag") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_beam_repositioning_flag"));
- v.app.sdp_source_info_subband_calibrated_flag := hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_subband_calibrated_flag") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_subband_calibrated_flag"));
+ v.app.sdp_source_info_weighted_subbands_flag := hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_weighted_subbands_flag") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_weighted_subbands_flag"));
v.app.sdp_source_info_reserved := hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_reserved") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_reserved"));
v.app.sdp_source_info_gn_id := hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_gn_id") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_gn_id"));
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 7e1e3a084fafafc614433f48d0b91f5f1db78e5b..528ce3d5d74364c88bb0062061a910d2e6355643 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -422,8 +422,8 @@ ARCHITECTURE str OF sdp_station IS
----------------------------------------------
SIGNAL ait_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
- SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
- SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0); -- raw subbands
+ SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0); -- weighted subbands
SIGNAL bs_sosi : t_dp_sosi;
SIGNAL xst_from_ri_sosi : t_dp_sosi;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index 04dcc4b8401c080de3884b67fdf50ae2f34a8398..afe6fb047c260a99537a89133bf8f1ed2af4056e 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -82,6 +82,17 @@
-- BST (Xh, Xl), (Yh, Yl), 2 keep X, Y parts order
-- XST (Rh, Rl), (Ih, Il), 2 keep Re, Im parts order
--
+-- . g_P_sq and nof_used_P_sq
+-- The g_P_sq defines the number of correlator cells that is available in
+-- the SDPFW. Use generic to support P_sq = 1 for one node and P_sq =
+-- c_sdp_P_sq for multiple nodes (with ring).
+-- The nof_used_P_sq is the number of correlator cells that is actually
+-- used and that will output XST packets. Unused correlator cells yield
+-- zero data that should not be output. The nof_used_P_sq is the smallest
+-- of g_P_sq and ring_info.N_rn/2 + 1. In this way the XST offload can work
+-- with g_P_sq = 1 when N_rn > 1 and also in a ring with N_rn < N_pn when
+-- g_P_sq = 9.
+--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, mm_lib, dp_lib, ring_lib;
@@ -99,8 +110,8 @@ ENTITY sdp_statistics_offload IS
g_statistics_type : STRING := "SST";
g_offload_time : NATURAL := c_sdp_offload_time;
g_beamset_id : NATURAL := 0;
- g_P_sq : NATURAL := c_sdp_P_sq; -- use generic to support P_sq = 1 for one node and P_sq = c_sdp_P_sq for multiple nodes (with ring)
- g_crosslets_direction : NATURAL := 1; -- > 0 for crosslet transport in positive direction (incrementing RN), else 0 for negative direction
+ g_P_sq : NATURAL := c_sdp_P_sq; -- number of available correlator cells,
+ g_crosslets_direction : NATURAL := 1; -- > 0 for crosslet transport in positive direction (incrementing RN), else 0 for negative direction
g_reverse_word_order : BOOLEAN := TRUE -- default word order is MSB after LSB, we need to stream LSB after MSB.
);
PORT (
@@ -141,7 +152,7 @@ ENTITY sdp_statistics_offload IS
gn_index : IN NATURAL;
ring_info : IN t_ring_info := c_ring_info_rst; -- only needed for XST
sdp_info : IN t_sdp_info;
- subband_calibrated_flag : IN STD_LOGIC := '0';
+ weighted_subbands_flag : IN STD_LOGIC := '0';
nof_crosslets : IN STD_LOGIC_VECTOR(c_sdp_nof_crosslets_reg_w-1 DOWNTO 0) := (OTHERS => '0');
crosslets_info : IN STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0')
);
@@ -202,7 +213,10 @@ ARCHITECTURE str OF sdp_statistics_offload IS
SIGNAL remote_pn : NATURAL; -- index of remote node in antenna band
SIGNAL remote_si_offset : NATURAL; -- index of first signal input on remote node
SIGNAL nof_cycles_dly : NATURAL; -- trigger_offload delay for this node
- SIGNAL nof_packets : NATURAL; -- nof packets per integration interval
+ SIGNAL offset_rn : NATURAL; -- = ring_info.O_rn, GN index of first ring node
+ SIGNAL nof_rn : NATURAL; -- = ring_info.N_rn, number of GN in the ring
+ SIGNAL nof_used_P_sq : NATURAL; -- number of used correlator cells <= g_P_sq (is number of available correlator cells)
+ SIGNAL nof_packets : NATURAL; -- nof XST offload packets per integration interval
SIGNAL data_id_rec : t_sdp_stat_data_id;
SIGNAL data_id_slv : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
@@ -258,7 +272,7 @@ BEGIN
-- sdp_source_info_fsub_type,
-- sdp_source_info_payload_error,
-- sdp_source_info_beam_repositioning_flag,
- -- sdp_source_info_subband_calibrated_flag,
+ -- sdp_source_info_weighted_subbands_flag,
-- sdp_source_info_gn_id,
-- - sdp_integration_interval, sdp_data_id, sdp_nof_signal_inputs,
-- sdp_nof_bytes_per_statistic,
@@ -279,7 +293,7 @@ BEGIN
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_fsub_type" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_fsub_type" )) <= SLV(sdp_info.fsub_type);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_payload_error" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_payload_error" )) <= SLV(r.payload_err);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_beam_repositioning_flag" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_beam_repositioning_flag" )) <= SLV(sdp_info.beam_repositioning_flag);
- dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_subband_calibrated_flag" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_subband_calibrated_flag" )) <= SLV(subband_calibrated_flag);
+ dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_weighted_subbands_flag" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_weighted_subbands_flag" )) <= SLV(weighted_subbands_flag);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_gn_id" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_gn_id" )) <= TO_UVEC(gn_index, 5);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_integration_interval" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_integration_interval" )) <= TO_UVEC(r.integration_interval, 24);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_data_id" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_data_id" )) <= data_id_slv;
@@ -299,17 +313,24 @@ BEGIN
END PROCESS;
-- Derive and pipeline dynamic parameters
- gn_index_reg <= gn_index WHEN rising_edge(dp_clk);
- pn_index <= func_sdp_gn_index_to_pn_index(gn_index) WHEN rising_edge(dp_clk);
- rn_index <= gn_index - TO_UINT(ring_info.O_rn) WHEN rising_edge(dp_clk);
- local_si_offset <= pn_index * c_sdp_S_pn WHEN rising_edge(dp_clk);
- nof_cycles_dly <= gn_index * g_offload_time WHEN rising_edge(dp_clk);
- nof_packets <= func_sdp_get_stat_nof_packets(g_statistics_type, c_sdp_S_pn, g_P_sq, r.nof_crosslets) WHEN rising_edge(dp_clk);
-
- remote_rn <= func_ring_nof_hops_to_source_rn(r.instance_count, rn_index, TO_UINT(ring_info.N_rn), g_crosslets_direction);
- remote_gn <= TO_UINT(ring_info.O_rn) + remote_rn;
- remote_pn <= func_sdp_gn_index_to_pn_index(remote_gn) WHEN rising_edge(dp_clk);
- remote_si_offset <= remote_pn * c_sdp_S_pn WHEN rising_edge(dp_clk);
+ p_parameters : PROCESS(dp_clk)
+ BEGIN
+ IF rising_edge(dp_clk) THEN
+ gn_index_reg <= gn_index;
+ pn_index <= func_sdp_gn_index_to_pn_index(gn_index_reg);
+ offset_rn <= TO_UINT(ring_info.O_rn);
+ rn_index <= gn_index_reg - offset_rn;
+ local_si_offset <= pn_index * c_sdp_S_pn;
+ nof_cycles_dly <= gn_index_reg * g_offload_time;
+ nof_rn <= TO_UINT(ring_info.N_rn);
+ nof_used_P_sq <= smallest(nof_rn / 2 + 1, g_P_sq);
+ nof_packets <= func_sdp_get_stat_nof_packets(g_statistics_type, c_sdp_S_pn, nof_used_P_sq, r.nof_crosslets);
+ remote_rn <= func_ring_nof_hops_to_source_rn(r.instance_count, rn_index, nof_rn, g_crosslets_direction);
+ remote_gn <= offset_rn + remote_rn;
+ remote_pn <= func_sdp_gn_index_to_pn_index(remote_gn);
+ remote_si_offset <= remote_pn * c_sdp_S_pn;
+ END IF;
+ END PROCESS;
-- Assign application header data_id for different statistic types, use
-- GENERATE to keep unused fields at 0.
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
index 2b6912dc420207a7adb5bd133be40546074c798c..d58cd1b58e1de6fbc64612736e5f3bad2ce48e72 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
@@ -55,28 +55,31 @@ ARCHITECTURE tb OF tb_sdp_crosslets_subband_select IS
CONSTANT c_rl : NATURAL := 1;
CONSTANT c_nof_sync : NATURAL := 5;
CONSTANT c_nof_block_per_sync : NATURAL := 4;
- CONSTANT c_nof_ch_in : NATURAL := 1024; -- nof input words per block, identical for all input streams.
CONSTANT c_dsp_data_w : NATURAL := c_sdp_W_subband;
- CONSTANT c_nof_ch_sel_row : NATURAL := c_sdp_P_pfb;
CONSTANT c_N_crosslets : NATURAL := 2;
- CONSTANT c_ch_sel_offsets : t_natural_arr(0 TO c_N_crosslets-1) := (0, 15);
- CONSTANT c_nof_ch_sel_col : NATURAL := c_sdp_Q_fft; -- nof of sequential collums to select per row.
- CONSTANT c_ch_sel_step : NATURAL := 3; -- offset step size to increase per sync interval
+ CONSTANT c_crosslet_offsets : t_natural_arr(0 TO c_N_crosslets-1) := (0, 15);
+ CONSTANT c_crosslet_step : NATURAL := 3; -- offset step size to increase per sync interval
+ CONSTANT c_nof_ch_in : NATURAL := 1024; -- nof input words per block, identical for all input streams.
+ CONSTANT c_nof_ch_sel_row : NATURAL := c_sdp_P_pfb;
+ CONSTANT c_nof_ch_sel_col : NATURAL := c_sdp_Q_fft; -- nof of sequential columns to select per row.
CONSTANT c_nof_ch_sel : NATURAL := c_N_crosslets*c_nof_ch_sel_col*c_nof_ch_sel_row;
+
CONSTANT c_ctrl_interval_size : NATURAL := c_nof_block_per_sync * c_nof_ch_in;
CONSTANT c_scheduled_bsn : NATURAL := 11;
CONSTANT c_nof_block_dly : NATURAL := c_nof_block_per_sync;
+ SIGNAL tb_end : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
SIGNAL mm_clk : STD_LOGIC := '1';
- SIGNAL tb_end : STD_LOGIC;
-
- SIGNAL mm_mosi : t_mem_mosi;
- SIGNAL mm_miso : t_mem_miso;
-
+
+ SIGNAL mm_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL mm_miso : t_mem_miso;
+ SIGNAL rd_crosslet_offsets : t_natural_arr(0 TO c_N_crosslets-1) := (0, 15);
+ SIGNAL rd_crosslet_step : NATURAL;
+
SIGNAL mm_trigger_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL mm_trigger_miso : t_mem_miso;
@@ -91,32 +94,74 @@ ARCHITECTURE tb OF tb_sdp_crosslets_subband_select IS
SIGNAL out_sosi : t_dp_sosi;
- SIGNAL exp_crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
- SIGNAL out_crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL exp_crosslets_info_slv : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL out_crosslets_info_slv : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL exp_crosslets_info_rec : t_sdp_crosslets_info;
+ SIGNAL out_crosslets_info_rec : t_sdp_crosslets_info;
+
BEGIN
clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
mm_clk <= (NOT mm_clk) OR tb_end AFTER c_mm_clk_period/2;
rst <= '1', '0' AFTER c_clk_period*7;
- p_select_stimuli : PROCESS
+ p_mm_stimuli : PROCESS
VARIABLE k : NATURAL;
BEGIN
-
proc_common_wait_until_low(mm_clk, rst);
proc_common_wait_some_cycles(mm_clk, 50); -- Give dut some time to start
- -- BSN Scheduler
+
+ -- Set BSN sync scheduler
proc_mem_mm_bus_wr(1, c_ctrl_interval_size, mm_clk, mm_trigger_miso, mm_trigger_mosi);
proc_mem_mm_bus_wr(2, c_scheduled_bsn, mm_clk, mm_trigger_miso, mm_trigger_mosi);
proc_mem_mm_bus_wr(3, 0, mm_clk, mm_trigger_miso, mm_trigger_mosi);
proc_mem_mm_bus_wr(0, 1, mm_clk, mm_trigger_miso, mm_trigger_mosi); --enable
+ -- Set crosslet info
+ FOR I IN 0 TO c_N_crosslets-1 LOOP
+ proc_mem_mm_bus_wr(I, c_crosslet_offsets(I), mm_clk, mm_miso, mm_mosi); --offsets
+ END LOOP;
+ proc_mem_mm_bus_wr(15, c_crosslet_step, mm_clk, mm_miso, mm_mosi); --step
+ proc_common_wait_cross_clock_domain_latency(c_clk_period, c_mm_clk_period);
- -- crosslet info
+ -- Verify that MM reads the active crosslets_info
+ -- a) Readback crosslet info after rst release
+ FOR I IN 0 TO c_N_crosslets-1 LOOP
+ proc_mem_mm_bus_rd(I, mm_clk, mm_miso, mm_mosi); --offsets
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rd_crosslet_offsets(I) <= TO_UINT(mm_miso.rddata(c_word_w-1 DOWNTO 0));
+ END LOOP;
+ proc_mem_mm_bus_rd(15, mm_clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rd_crosslet_step <= TO_UINT(mm_miso.rddata(c_word_w-1 DOWNTO 0));
+ proc_common_wait_some_cycles(mm_clk, 1);
+ -- Verify that readback crosslet info is active crosslets_info
FOR I IN 0 TO c_N_crosslets-1 LOOP
- proc_mem_mm_bus_wr(I, c_ch_sel_offsets(I), mm_clk, mm_miso, mm_mosi); --offsets
+ ASSERT rd_crosslet_offsets(I) = 0 REPORT "Wrong crosslet offset after rst." SEVERITY ERROR;
END LOOP;
- proc_mem_mm_bus_wr(15, c_ch_sel_step, mm_clk, mm_miso, mm_mosi); --step
+ ASSERT rd_crosslet_step = 0 REPORT "Wrong crosslet step after rst." SEVERITY ERROR;
+
+ -- b) Read crosslet_info in every sync interval
+ WHILE TRUE LOOP
+ proc_common_wait_until_hi_lo(clk, out_sosi.sync);
+ proc_common_wait_cross_clock_domain_latency(c_clk_period, c_mm_clk_period);
+ -- Readback crosslet info
+ FOR I IN 0 TO c_N_crosslets-1 LOOP
+ proc_mem_mm_bus_rd(I, mm_clk, mm_miso, mm_mosi); --offsets
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rd_crosslet_offsets(I) <= TO_UINT(mm_miso.rddata(c_word_w-1 DOWNTO 0));
+ END LOOP;
+ proc_mem_mm_bus_rd(15, mm_clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rd_crosslet_step <= TO_UINT(mm_miso.rddata(c_word_w-1 DOWNTO 0));
+ proc_common_wait_some_cycles(mm_clk, 1);
+ -- Verify that readback crosslet info is active crosslets_info
+ FOR I IN 0 TO c_N_crosslets-1 LOOP
+ ASSERT rd_crosslet_offsets(I) = exp_crosslets_info_rec.offset_arr(I) REPORT "Wrong active crosslet offset in output sync interval." SEVERITY ERROR;
+ END LOOP;
+ ASSERT rd_crosslet_step = exp_crosslets_info_rec.step REPORT "Wrong active crosslet step in output sync interval." SEVERITY ERROR;
+ END LOOP;
+
WAIT;
END PROCESS;
@@ -179,16 +224,16 @@ BEGIN
exp_sosi <= c_dp_sosi_rst;
WAIT UNTIL rising_edge(out_sosi.sop);
- exp_crosslets_info(c_sdp_crosslets_info_reg_w-1 DOWNTO c_sdp_crosslets_info_reg_w - c_sdp_crosslets_index_w) <= TO_UVEC(c_ch_sel_step, c_sdp_crosslets_index_w);
+ exp_crosslets_info_slv(c_sdp_crosslets_info_reg_w-1 DOWNTO c_sdp_crosslets_info_reg_w - c_sdp_crosslets_index_w) <= TO_UVEC(c_crosslet_step, c_sdp_crosslets_index_w);
FOR C IN 0 TO c_nof_ch_sel_col-1 LOOP
- exp_crosslets_info((C+1)*c_sdp_crosslets_index_w-1 DOWNTO C*c_sdp_crosslets_index_w) <= TO_UVEC(c_ch_sel_offsets(C) + v_sync_ix * c_ch_sel_step, c_sdp_crosslets_index_w);
+ exp_crosslets_info_slv((C+1)*c_sdp_crosslets_index_w-1 DOWNTO C*c_sdp_crosslets_index_w) <= TO_UVEC(c_crosslet_offsets(C) + v_sync_ix * c_crosslet_step, c_sdp_crosslets_index_w);
END LOOP;
FOR J IN 0 TO c_nof_ch_sel-1 LOOP
v_offset := J / (c_nof_ch_sel_col*c_nof_ch_sel_row);
v_col := J MOD c_nof_ch_sel_col;
v_row := (J/c_nof_ch_sel_col) MOD c_nof_ch_sel_row;
- v_k := c_nof_ch_sel_col * v_sync_ix * c_ch_sel_step;
+ v_k := c_nof_ch_sel_col * v_sync_ix * c_crosslet_step;
exp_sosi <= c_dp_sosi_rst;
exp_sosi.valid <= '1';
@@ -202,8 +247,8 @@ BEGIN
exp_sosi.eop <= '1';
END IF;
- exp_sosi.re <= RESIZE_DP_DSP_DATA(TO_DP_DSP_DATA( (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5)(c_sdp_W_crosslet-1 DOWNTO 0));
- exp_sosi.im <= RESIZE_DP_DSP_DATA(TO_DP_DSP_DATA(1+ (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5)(c_sdp_W_crosslet-1 DOWNTO 0));
+ exp_sosi.re <= RESIZE_DP_DSP_DATA(TO_DP_DSP_DATA( (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_crosslet_offsets(v_offset) + v_col + v_row*2**5)(c_sdp_W_crosslet-1 DOWNTO 0));
+ exp_sosi.im <= RESIZE_DP_DSP_DATA(TO_DP_DSP_DATA(1+ (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_crosslet_offsets(v_offset) + v_col + v_row*2**5)(c_sdp_W_crosslet-1 DOWNTO 0));
proc_common_wait_some_cycles(clk, 1);
END LOOP;
@@ -219,7 +264,7 @@ BEGIN
ASSERT out_sosi.sop = exp_sosi.sop REPORT "Wrong out_sosi.sop" SEVERITY ERROR;
ASSERT out_sosi.eop = exp_sosi.eop REPORT "Wrong out_sosi.eop" SEVERITY ERROR;
ASSERT out_sosi.sync = exp_sosi.sync REPORT "Wrong out_sosi.sync" SEVERITY ERROR;
- ASSERT out_crosslets_info = exp_crosslets_info REPORT "Wrong out_crosslets_info" SEVERITY ERROR;
+ ASSERT out_crosslets_info_slv = exp_crosslets_info_slv REPORT "Wrong out_crosslets_info_slv" SEVERITY ERROR;
IF exp_sosi.valid = '1' THEN
ASSERT out_sosi.re = exp_sosi.re REPORT "Wrong out_sosi.re" SEVERITY ERROR;
ASSERT out_sosi.im = exp_sosi.im REPORT "Wrong out_sosi.im" SEVERITY ERROR;
@@ -249,7 +294,11 @@ BEGIN
in_sosi_arr => in_sosi_arr,
out_sosi => out_sosi,
- out_crosslets_info => out_crosslets_info
+ out_crosslets_info => out_crosslets_info_slv
);
+ -- Map crosslets_info slv to record for easier view in Wave window
+ exp_crosslets_info_rec <= func_sdp_map_crosslets_info(exp_crosslets_info_slv);
+ out_crosslets_info_rec <= func_sdp_map_crosslets_info(out_crosslets_info_slv);
+
END tb;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
index d905af1d81408584d7240267628053baee46f4a5..7c2e39c5f1af617d757ee4fe815428bedac881ce 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
@@ -85,7 +85,7 @@ PACKAGE BODY tb_sdp_pkg IS
ASSERT in_hdr.app.sdp_source_info_fsub_type = exp_hdr.app.sdp_source_info_fsub_type REPORT "Wrong " & g_statistics_type & " app.sdp_source_info_fsub_type" SEVERITY ERROR;
ASSERT in_hdr.app.sdp_source_info_payload_error = exp_hdr.app.sdp_source_info_payload_error REPORT "Wrong " & g_statistics_type & " app.sdp_source_info_payload_error" SEVERITY ERROR;
ASSERT in_hdr.app.sdp_source_info_beam_repositioning_flag = exp_hdr.app.sdp_source_info_beam_repositioning_flag REPORT "Wrong " & g_statistics_type & " app.sdp_source_info_beam_repositioning_flag" SEVERITY ERROR;
- ASSERT in_hdr.app.sdp_source_info_subband_calibrated_flag = exp_hdr.app.sdp_source_info_subband_calibrated_flag REPORT "Wrong " & g_statistics_type & " app.sdp_source_info_subband_calibrated_flag" SEVERITY ERROR;
+ ASSERT in_hdr.app.sdp_source_info_weighted_subbands_flag = exp_hdr.app.sdp_source_info_weighted_subbands_flag REPORT "Wrong " & g_statistics_type & " app.sdp_source_info_weighted_subbands_flag" SEVERITY ERROR;
ASSERT in_hdr.app.sdp_source_info_reserved = exp_hdr.app.sdp_source_info_reserved REPORT "Wrong " & g_statistics_type & " app.sdp_source_info_reserved" SEVERITY ERROR;
ASSERT in_hdr.app.sdp_source_info_gn_id = exp_hdr.app.sdp_source_info_gn_id REPORT "Wrong " & g_statistics_type & " app.sdp_source_info_gn_id" SEVERITY ERROR;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
index 0c30fa8fb3a9d587e752b79d106fd4715073fec6..d3e8ea79f510f428d3550ecc8ccefe21028da6e8 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
@@ -54,17 +54,17 @@ USE work.tb_sdp_pkg.ALL;
ENTITY tb_sdp_statistics_offload IS
GENERIC (
-- All
- g_statistics_type : STRING := "SST";
+ g_statistics_type : STRING := "XST";
g_offload_time : NATURAL := 50;
g_reverse_word_order : BOOLEAN := TRUE; -- when TRUE then stream LSB word after MSB word.
- g_gn_index : NATURAL := 5; -- global node (GN) index, must be in range(O_rn, O_rn + N_rn), use > 0 to see effect of g_offload_time
+ g_gn_index : NATURAL := 0; -- global node (GN) index, must be in range(O_rn, O_rn + N_rn), use > 0 to see effect of g_offload_time
-- BST
- g_beamset_id : NATURAL := 1; -- < c_sdp_N_beamsets
+ g_beamset_id : NATURAL := 0; -- < c_sdp_N_beamsets
-- XST
- g_O_rn : NATURAL := 4; -- GN index of first ring node (RN)
+ g_O_rn : NATURAL := 0; -- GN index of first ring node (RN)
g_N_rn : NATURAL := 8; -- <= c_sdp_N_rn_max = 16, number of nodes in ring
- g_P_sq : NATURAL := 4; -- <= c_sdp_P_sq
- g_nof_crosslets : NATURAL := 3; -- <= c_sdp_N_crosslets_max
+ g_P_sq : NATURAL := 9; -- <= c_sdp_P_sq, nof available correlator cells
+ g_nof_crosslets : NATURAL := 7; -- <= c_sdp_N_crosslets_max
g_crosslets_direction : NATURAL := 1 -- > 0 for crosslet transport in positive direction (incrementing RN), else 0 for negative direction
);
END tb_sdp_statistics_offload;
@@ -117,7 +117,8 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS
-- Crosslets settings
CONSTANT c_mm_nof_crosslets : STD_LOGIC_VECTOR(c_sdp_nof_crosslets_reg_w-1 DOWNTO 0) := TO_UVEC(g_nof_crosslets, c_sdp_nof_crosslets_reg_w);
- CONSTANT c_mm_nof_packets : NATURAL := func_sdp_get_stat_nof_packets(g_statistics_type, c_sdp_S_pn, g_P_sq, g_nof_crosslets);
+ CONSTANT c_nof_used_P_sq : NATURAL := smallest(g_N_rn / 2 + 1, g_P_sq); -- number of used correlator cells <= g_P_sq
+ CONSTANT c_rx_nof_packets : NATURAL := func_sdp_get_stat_nof_packets(g_statistics_type, c_sdp_S_pn, c_nof_used_P_sq, g_nof_crosslets);
-- payload data
CONSTANT c_packet_size : NATURAL := c_nof_statistics_per_packet * c_sdp_W_statistic_sz;
@@ -204,7 +205,7 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS
SIGNAL source_rn : NATURAL; -- source node RN
SIGNAL source_gn : NATURAL; -- source node GN
- SIGNAL subband_calibrated_flag : STD_LOGIC := '0';
+ SIGNAL weighted_subbands_flag : STD_LOGIC := '0';
-- Signals used for starting processes.
SIGNAL ram_wr_data : STD_LOGIC_VECTOR(c_ram_buf.dat_w-1 DOWNTO 0);
@@ -225,6 +226,7 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS
SIGNAL dbg_c_marker : NATURAL := c_marker;
SIGNAL dbg_c_nof_signal_inputs : NATURAL := c_nof_signal_inputs;
SIGNAL dbg_c_nof_packets_max : NATURAL := c_nof_packets_max;
+ SIGNAL dbg_c_rx_nof_packets : NATURAL := c_rx_nof_packets;
SIGNAL dbg_c_beamlet_index : NATURAL := c_beamlet_index;
SIGNAL dbg_c_packet_size : NATURAL := c_packet_size;
SIGNAL dbg_c_mm_user_size : NATURAL := c_mm_user_size;
@@ -337,7 +339,7 @@ BEGIN
test_sync_cnt <= in_sync_cnt - 1; -- optionally adjust to fit test_offload_sosi
-- derive current X_sq correlator cell index
- cur_X_sq_cell <= (test_offload_eop_cnt / g_nof_crosslets) MOD g_P_sq;
+ cur_X_sq_cell <= (test_offload_eop_cnt / g_nof_crosslets) MOD c_nof_used_P_sq;
-- derive current N_crosslets index index
cur_crosslet <= test_offload_eop_cnt MOD g_nof_crosslets;
@@ -364,7 +366,7 @@ BEGIN
-- . prepare expected XST signal_input_B index, assume crosslet transport in positive direction
exp_xst_signal_input_B <= (source_gn MOD c_sdp_N_pn_max) * c_sdp_S_pn;
- p_exp_sdp_stat_header : PROCESS(subband_calibrated_flag, gn_index, exp_dp_bsn, exp_sst_signal_input, exp_subband_index, exp_xst_signal_input_A, exp_xst_signal_input_B)
+ p_exp_sdp_stat_header : PROCESS(weighted_subbands_flag, gn_index, exp_dp_bsn, exp_sst_signal_input, exp_subband_index, exp_xst_signal_input_A, exp_xst_signal_input_B)
BEGIN
-- eth header
exp_sdp_stat_header.eth.dst_mac <= c_sdp_stat_eth_dst_mac;
@@ -403,7 +405,7 @@ BEGIN
exp_sdp_stat_header.app.sdp_source_info_fsub_type <= slv(c_exp_sdp_info.fsub_type);
exp_sdp_stat_header.app.sdp_source_info_payload_error <= TO_UVEC(0, 1);
exp_sdp_stat_header.app.sdp_source_info_beam_repositioning_flag <= slv(c_exp_sdp_info.beam_repositioning_flag);
- exp_sdp_stat_header.app.sdp_source_info_subband_calibrated_flag <= slv(subband_calibrated_flag);
+ exp_sdp_stat_header.app.sdp_source_info_weighted_subbands_flag <= slv(weighted_subbands_flag);
exp_sdp_stat_header.app.sdp_source_info_reserved <= TO_UVEC(0, 3);
exp_sdp_stat_header.app.sdp_source_info_gn_id <= TO_UVEC(gn_index, 5);
@@ -460,7 +462,7 @@ BEGIN
BEGIN
IF rising_edge(dp_clk) THEN
IF in_sosi.sync = '1' AND in_sync_cnt > 1 THEN
- ASSERT rx_packet_cnt = c_mm_nof_packets REPORT "Wrong number of packets per sync interval" SEVERITY ERROR;
+ ASSERT rx_packet_cnt = c_rx_nof_packets REPORT "Wrong number of packets per sync interval" SEVERITY ERROR;
END IF;
END IF;
END PROCESS;
@@ -557,7 +559,7 @@ BEGIN
ASSERT v_exp_data = v_rx_data REPORT "Wrong BST payload data Rx" SEVERITY ERROR;
ELSIF g_statistics_type = "XST" THEN
- -- . g_P_sq = 4
+ -- . c_nof_used_P_sq = 4
-- . g_nof_crosslets = 3
-- . c_sdp_N_crosslets_max = 7 --> c_mm_Xsq_span = 2**ceil_log2(7 * 576) = 4096
--
@@ -587,9 +589,9 @@ BEGIN
-- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_nof_complex
X := D; -- range c_sdp_X_sq = 144 complex XST values
I := W MOD c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
- P := rx_packet_cnt; -- range c_mm_nof_packets
+ P := rx_packet_cnt; -- range c_rx_nof_packets
J := P MOD g_nof_crosslets; -- range g_nof_crosslets
- K := P / g_nof_crosslets; -- range g_P_sq
+ K := P / g_nof_crosslets; -- range c_nof_used_P_sq
v_exp_data := S * c_mm_user_size; -- c_mm_user_size = 2
IF g_reverse_word_order = FALSE THEN
@@ -706,7 +708,7 @@ BEGIN
gn_index => gn_index,
ring_info => c_exp_ring_info,
sdp_info => c_exp_sdp_info,
- subband_calibrated_flag => subband_calibrated_flag,
+ weighted_subbands_flag => weighted_subbands_flag,
nof_crosslets => c_mm_nof_crosslets,
crosslets_info => in_crosslets_info_slv
);
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
index a688d26acd7d88aba8f60ca51f3409710bf0c36e..0d3f42ce3fd8ebfd344e86d101ddc1a301d05b49 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
@@ -63,5 +63,7 @@ BEGIN
u_xst_P9_N3_no_reverse : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("XST", 50, FALSE, 1, 0, 0, 16, 9, 3, 1);
u_xst_P9_N3_neg : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("XST", 50, TRUE, 1, 0, 0, 16, 9, 3, 0);
u_xst_P8_N7_RN1_15 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("XST", 50, TRUE, 1, 0, 1, 15, 8, 7, 0);
+ u_xst_P1_N7_RN0_7 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("XST", 50, TRUE, 3, 0, 0, 8, 1, 7, 1); -- P_sq = 1 < N_rn/2+1 = 5
+ u_xst_P9_N7_RN0_7 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("XST", 50, TRUE, 3, 0, 0, 8, 9, 7, 1); -- P_sq = 9 > N_rn/2+1 = 5
END tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index ec61c554e1d9224213f550744994132598d0feea..11f71912060c66fd2d324bd4a0530a103d6b1738 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -258,7 +258,7 @@ END ctrl_unb2b_board;
ARCHITECTURE str OF ctrl_unb2b_board IS
- CONSTANT c_rom_version : NATURAL := 2; -- Only increment when something changes to the register map of rom_system_info.
+ CONSTANT c_rom_version : NATURAL := 3; -- Only increment when something changes to the register map of rom_system_info.
CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg
CONSTANT c_mm_clk_freq : NATURAL := sel_a_b(g_sim=FALSE,g_mm_clk_freq,c_unb2b_board_mm_clk_freq_10M);
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index 105a8f3b95a2d81afb8253ca857262316c2b60ab..20c4278e6951dfa1f2b727784a5ee751ebf87523 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -241,7 +241,7 @@ END ctrl_unb2c_board;
ARCHITECTURE str OF ctrl_unb2c_board IS
- CONSTANT c_rom_version : NATURAL := 2; -- Only increment when something changes to the register map of rom_system_info.
+ CONSTANT c_rom_version : NATURAL := 3; -- Only increment when something changes to the register map of rom_system_info.
CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg
CONSTANT c_mm_clk_freq : NATURAL := sel_a_b(g_sim=FALSE,g_mm_clk_freq,c_unb2c_board_mm_clk_freq_10M);
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index 331c88ad51e35af98694cc004c3bb75a84cc4a16..4146bec45c38f9d6b98fb7bbdf4bb8d3183ffb00 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -835,6 +835,8 @@ Works from home in VPN:
* LTS --> http://test-lcu2.astron.nl:8888/notebooks/ # = dop81
* DTS --> http://dts-lcu.astron.nl:8888/notebooks/
+Check of SDPTR op dop369 actief is met:
+> uals -u 10.87.2.36:4840 -p "0:Objects"
*******************************************************************************
* Zenodo DOI
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 6153caf04a8c55f7cfdb2b77674b7407161229a4..13d8042484abd05f906b0b30d243174e12139cb2 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -473,7 +473,9 @@ PACKAGE common_pkg IS
FUNCTION SHIFT_UVEC(vec : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR; -- < 0 shift left, > 0 shift right
FUNCTION SHIFT_SVEC(vec : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR; -- < 0 shift left, > 0 shift right
-
+
+ FUNCTION ROTATE_UVEC(vec : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR; -- < 0 rotate left, > 0 rotate right
+
FUNCTION offset_binary(a : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION truncate( vec : STD_LOGIC_VECTOR; n : NATURAL) RETURN STD_LOGIC_VECTOR; -- remove n LSBits from vec, so result has width vec'LENGTH-n
@@ -2271,6 +2273,17 @@ PACKAGE BODY common_pkg IS
END IF;
END;
+ FUNCTION ROTATE_UVEC(vec : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ IF shift < 0 THEN
+ RETURN STD_LOGIC_VECTOR(ROTATE_LEFT(UNSIGNED(vec), -shift)); -- /<-- vec <--\
+ -- \---------->/
+ ELSE
+ RETURN STD_LOGIC_VECTOR(ROTATE_RIGHT(UNSIGNED(vec), shift)); -- /--> vec -->\
+ -- \<----------/
+ END IF;
+ END;
+
--
-- offset_binary() : maps offset binary to or from two-complement binary.
--
diff --git a/libraries/base/diag/src/vhdl/diag_wg.vhd b/libraries/base/diag/src/vhdl/diag_wg.vhd
index 53ab3a2a5daf43706991a4e810991280920e5dc8..a30ec8a8608aa3fce0021d2829869ddaf3116558 100644
--- a/libraries/base/diag/src/vhdl/diag_wg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg.vhd
@@ -21,7 +21,12 @@
-- Purpose: Sine waveform generator
-- Description:
--- . Based on diag_waveproc from LOFAR.
+-- . Based on diag_waveproc from LOFAR1.
+-- . Monitor the active WG ctrl:
+-- - WG ctrl.mode = off takes effect immediately
+-- - WG ctrl.ampl takes effect immediately
+-- - Changing WG ctrl.phase and ctrl.freq require a restart to take effect,
+-- to have synchronous phase relation between different WG.
-- Remarks:
-- . For WG sine periods that integer fit in the WG buffer size the carrier
-- wWave (CW) frequency is exact. For fractional WG frequencies, for which
@@ -73,6 +78,7 @@ ENTITY diag_wg IS
buf_rdval : IN STD_LOGIC;
ctrl : IN t_diag_wg;
+ mon_ctrl : OUT t_diag_wg;
out_ovr : OUT STD_LOGIC;
out_dat : OUT STD_LOGIC_VECTOR(g_buf_dat_w-1 DOWNTO 0);
@@ -117,8 +123,11 @@ ARCHITECTURE rtl OF diag_wg IS
SIGNAL state : state_enum;
SIGNAL nxt_state : state_enum;
+ SIGNAL prev_state : state_enum;
SIGNAL idle : STD_LOGIC;
+ SIGNAL i_mon_ctrl : t_diag_wg;
+ SIGNAL nxt_mon_ctrl : t_diag_wg;
SIGNAL nof_samples : STD_LOGIC_VECTOR(g_buf_addr_w DOWNTO 0); -- only use effective range of nof_samples+1
SIGNAL nxt_nof_samples : STD_LOGIC_VECTOR(g_buf_addr_w DOWNTO 0);
SIGNAL sample_cnt : NATURAL RANGE 0 TO 2**g_buf_addr_w-1;
@@ -126,7 +135,7 @@ ARCHITECTURE rtl OF diag_wg IS
SIGNAL sample_step : NATURAL RANGE 0 TO g_rate_factor;
SIGNAL nxt_sample_step : NATURAL;
SIGNAL init_repeat_done : STD_LOGIC;
-
+
SIGNAL phase : STD_LOGIC_VECTOR(ctrl.freq'LENGTH-1 DOWNTO 0);
SIGNAL nxt_phase : STD_LOGIC_VECTOR(phase'RANGE);
SIGNAL phase_step : STD_LOGIC_VECTOR(phase'RANGE);
@@ -159,12 +168,15 @@ ARCHITECTURE rtl OF diag_wg IS
BEGIN
+ mon_ctrl <= i_mon_ctrl;
+
registers : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
-- Internal registers.
nof_samples <= (OTHERS => '0');
state <= s_off;
+ prev_state <= s_off;
sample_cnt <= 0;
sample_step <= 0;
phase <= (OTHERS => '0');
@@ -172,6 +184,7 @@ BEGIN
init_phase_cnt <= 0;
init_sync <= '0';
-- Output registers.
+ i_mon_ctrl <= c_diag_wg_rst;
buf_addr <= (OTHERS => '0');
buf_rden <= '0';
out_ovr <= '0';
@@ -182,6 +195,7 @@ BEGIN
-- Internal registers.
nof_samples <= nxt_nof_samples;
state <= nxt_state;
+ prev_state <= state;
sample_cnt <= nxt_sample_cnt;
sample_step <= nxt_sample_step;
phase <= nxt_phase;
@@ -189,6 +203,7 @@ BEGIN
init_phase_cnt <= nxt_init_phase_cnt;
init_sync <= nxt_init_sync;
-- Output registers.
+ i_mon_ctrl <= nxt_mon_ctrl;
buf_addr <= nxt_buf_addr;
buf_rden <= nxt_buf_rden;
out_ovr <= nxt_out_ovr;
@@ -317,9 +332,23 @@ BEGIN
END IF;
END PROCESS;
-
ctrl_ampl <= '0' & ctrl.ampl;
+ p_mon_ctrl : PROCESS(i_mon_ctrl, ctrl, prev_state, state)
+ BEGIN
+ nxt_mon_ctrl <= i_mon_ctrl;
+ IF TO_UINT(ctrl.mode) = c_diag_wg_mode_off THEN
+ -- WG immediately goes into off state
+ nxt_mon_ctrl <= ctrl;
+ ELSIF prev_state = s_init AND prev_state /= state THEN
+ -- WG holds ctrl, when it goes into active state (s_single, s_repeat, or s_calc)
+ nxt_mon_ctrl <= ctrl;
+ END IF;
+ -- These MM ctrl fields always take effect immediately in all WG states
+ nxt_mon_ctrl.ampl <= ctrl.ampl;
+ nxt_mon_ctrl.nof_samples <= ctrl.nof_samples;
+ END PROCESS;
+
mult : ENTITY common_mult_lib.common_mult
GENERIC MAP (
g_technology => g_technology,
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
index 63d02e992cb7517fae7ddb83bbaf8649f71e3e3d..0f4384df6182b31988bb8090ab3bcd95b4835b9b 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
@@ -66,6 +66,7 @@ ENTITY diag_wg_wideband IS
st_restart : IN STD_LOGIC;
st_ctrl : IN t_diag_wg;
+ st_mon_ctrl : OUT t_diag_wg;
out_ovr : OUT STD_LOGIC_VECTOR(g_wideband_factor -1 DOWNTO 0); -- big endian, so first output sample in MSBit, MSData
out_dat : OUT STD_LOGIC_VECTOR(g_wideband_factor*g_buf_dat_w-1 DOWNTO 0);
@@ -88,7 +89,9 @@ ARCHITECTURE str OF diag_wg_wideband IS
TYPE t_buf_dat_arr IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(g_buf_dat_w-1 DOWNTO 0);
TYPE t_buf_adr_arr IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(g_buf_addr_w-1 DOWNTO 0);
-
+
+ SIGNAL st_mon_ctrl_arr : t_diag_wg_arr(0 TO g_wideband_factor-1);
+
-- Use same address and data widths for both MM side and ST side memory ports
SIGNAL buf_rdval : STD_LOGIC_VECTOR(0 TO g_wideband_factor-1);
SIGNAL buf_rddata : t_buf_dat_arr(0 TO g_wideband_factor-1);
@@ -107,6 +110,8 @@ BEGIN
mm_rdval <= buf_rdval(0);
mm_rddata <= buf_rddata(0);
+ st_mon_ctrl <= st_mon_ctrl_arr(0); -- same for all g_wideband_factor waveform generators
+
gen_wg : FOR I IN 0 TO g_wideband_factor-1 GENERATE
-- Waveform buffer
u_buf : ENTITY common_lib.common_ram_crw_crw
@@ -157,7 +162,8 @@ BEGIN
buf_rden => st_rd(I),
ctrl => st_ctrl,
-
+ mon_ctrl => st_mon_ctrl_arr(I),
+
out_ovr => out_ovr( g_wideband_factor-I-1),
out_dat => out_dat((g_wideband_factor-I)*g_buf_dat_w-1 DOWNTO (g_wideband_factor-I-1)*g_buf_dat_w),
out_val => out_val( g_wideband_factor-I-1),
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
index 4043c51e1efa6bb2bcbf672b4f52ae97dba203a3..c6db7329b6ea11c94d3918d8b6f728518c06230e 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
@@ -62,7 +62,8 @@ ENTITY diag_wg_wideband_reg IS
sla_out : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
-- MM registers in st_clk domain
- st_wg_ctrl : OUT t_diag_wg -- WG control port
+ st_wg_ctrl : OUT t_diag_wg; -- WG control write port
+ st_mon_ctrl : IN t_diag_wg -- WG control read port, for currently active control
);
END diag_wg_wideband_reg;
@@ -80,6 +81,8 @@ ARCHITECTURE rtl OF diag_wg_wideband_reg IS
SIGNAL mm_wg_ctrl : t_diag_wg;
SIGNAL mm_wg_ctrl_mode_wr : STD_LOGIC;
+ SIGNAL mm_mon_ctrl : t_diag_wg;
+
-- Registers in st_clk domain
BEGIN
@@ -129,14 +132,14 @@ BEGIN
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
CASE TO_UINT(sla_in.address(c_mm_reg.adr_w-1 DOWNTO 0)) IS
WHEN 0 =>
- sla_out.rddata( 7 DOWNTO 0) <= mm_wg_ctrl.mode; -- = 8 = c_diag_wg_mode_w
- sla_out.rddata(31 DOWNTO 16) <= mm_wg_ctrl.nof_samples; -- = 16 = c_diag_wg_nof_samples_w
+ sla_out.rddata( 7 DOWNTO 0) <= mm_mon_ctrl.mode; -- = 8 = c_diag_wg_mode_w
+ sla_out.rddata(31 DOWNTO 16) <= mm_mon_ctrl.nof_samples; -- = 16 = c_diag_wg_nof_samples_w
WHEN 1 =>
- sla_out.rddata(15 DOWNTO 0) <= mm_wg_ctrl.phase; -- = 16 = c_diag_wg_phase_w
+ sla_out.rddata(15 DOWNTO 0) <= mm_mon_ctrl.phase; -- = 16 = c_diag_wg_phase_w
WHEN 2 =>
- sla_out.rddata(30 DOWNTO 0) <= mm_wg_ctrl.freq; -- = 31 = c_diag_wg_freq_w
+ sla_out.rddata(30 DOWNTO 0) <= mm_mon_ctrl.freq; -- = 31 = c_diag_wg_freq_w
WHEN 3 =>
- sla_out.rddata(16 DOWNTO 0) <= mm_wg_ctrl.ampl; -- = 17 = c_diag_wg_ampl_w
+ sla_out.rddata(16 DOWNTO 0) <= mm_mon_ctrl.ampl; -- = 17 = c_diag_wg_ampl_w
WHEN OTHERS => NULL; -- not used MM addresses
END CASE;
END IF;
@@ -161,6 +164,7 @@ BEGIN
------------------------------------------------------------------------------
no_cross : IF g_cross_clock_domain = FALSE GENERATE -- so mm_clk = st_clk
+ -- Write: MM to ST clock domain
p_st_clk : PROCESS(st_rst, st_clk)
BEGIN
IF st_rst='1' THEN
@@ -171,9 +175,13 @@ BEGIN
END IF;
END IF;
END PROCESS;
- END GENERATE; -- no_cross
- gen_cross : IF g_cross_clock_domain = TRUE GENERATE
+ -- Read: ST to MM clock domain
+ mm_mon_ctrl <= st_mon_ctrl;
+ END GENERATE;
+
+ -- Write: MM to ST clock domain
+ gen_cross_wr : IF g_cross_clock_domain = TRUE GENERATE
-- Assume diag WG mode gets written last, so when diag WG mode is transfered properly to the st_clk domain, then
-- the other diag WG control fields are stable as well
u_mode : ENTITY common_lib.common_reg_cross_domain
@@ -188,7 +196,7 @@ BEGIN
out_dat => st_wg_ctrl.mode,
out_new => OPEN -- when '1' then the out_dat was updated with in_dat due to in_new
);
- END GENERATE; -- gen_cross
+ END GENERATE;
-- The other wg_ctrl only take effect in diag_wg after the mode has been set
st_wg_ctrl.nof_samples <= mm_wg_ctrl.nof_samples;
@@ -196,4 +204,57 @@ BEGIN
st_wg_ctrl.phase <= mm_wg_ctrl.phase;
st_wg_ctrl.ampl <= mm_wg_ctrl.ampl;
+ -- Read: ST to MM clock domain
+ gen_cross_rd : IF g_cross_clock_domain = TRUE GENERATE
+ u_mode : ENTITY common_lib.common_reg_cross_domain
+ PORT MAP (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.mode,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.mode
+ );
+
+ u_nof_samples : ENTITY common_lib.common_reg_cross_domain
+ PORT MAP (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.nof_samples,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.nof_samples
+ );
+
+ u_freq : ENTITY common_lib.common_reg_cross_domain
+ PORT MAP (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.freq,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.freq
+ );
+
+ u_phase : ENTITY common_lib.common_reg_cross_domain
+ PORT MAP (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.phase,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.phase
+ );
+
+ u_ampl : ENTITY common_lib.common_reg_cross_domain
+ PORT MAP (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.ampl,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.ampl
+ );
+ END GENERATE;
+
END rtl;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
index 6c6b912bde048cc3c7897963943bbc0c694ae430..e2f291106471290e27750fb6485d82002f149158 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
@@ -80,7 +80,8 @@ END mms_diag_wg_wideband;
ARCHITECTURE str OF mms_diag_wg_wideband IS
- SIGNAL st_wg_ctrl : t_diag_wg;
+ SIGNAL st_wg_ctrl : t_diag_wg; -- write
+ SIGNAL st_mon_ctrl : t_diag_wg; -- read
BEGIN
@@ -100,7 +101,8 @@ BEGIN
sla_out => reg_miso,
-- MM registers in st_clk domain
- st_wg_ctrl => st_wg_ctrl
+ st_wg_ctrl => st_wg_ctrl,
+ st_mon_ctrl => st_mon_ctrl
);
u_wg_wideband : ENTITY work.diag_wg_wideband
@@ -137,6 +139,7 @@ BEGIN
st_restart => st_restart,
st_ctrl => st_wg_ctrl,
+ st_mon_ctrl => st_mon_ctrl,
out_ovr => out_ovr,
out_dat => out_dat,
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
index ca3ba5ef9857a8cd8b962bf3fb7aa4f4a450445f..520bf017d12372c674ac709130a7c0fc01bde844 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
@@ -19,7 +19,7 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
-
+
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
@@ -49,7 +49,7 @@ ARCHITECTURE tb OF tb_diag_wg IS
CONSTANT c_clk_freq : NATURAL := 200*10**6; -- Hz
CONSTANT c_clk_period : TIME := (10**9 / c_clk_freq) * 1 ns;
-
+
-- Default settings
CONSTANT c_buf : t_c_mem := (latency => 1,
adr_w => g_buf_adr_w,
@@ -59,86 +59,86 @@ ARCHITECTURE tb OF tb_diag_wg IS
CONSTANT c_buf_file : STRING := sel_a_b(c_buf.adr_w=11 AND c_buf.dat_w=18, "data/diag_sin_2048x18.hex",
sel_a_b(c_buf.adr_w=10 AND c_buf.dat_w=18, "data/diag_sin_1024x18.hex",
sel_a_b(c_buf.adr_w=10 AND c_buf.dat_w= 8, "data/diag_sin_1024x8.hex", "UNUSED")));
-
-
+
+
CONSTANT c_wg_nof_samples : NATURAL := c_buf.nof_dat; -- must be <= c_buf.nof_dat
CONSTANT c_wg_gain_w : NATURAL := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
-- . use gain 2**0 = 1 to have fulle scale without clipping
-- . use gain 2**g_calc_gain_w > 1 to cause clipping
-
+
CONSTANT c_buf_full_scale : NATURAL := 2**(g_buf_dat_w-1)-1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
CONSTANT c_wg_full_scale : NATURAL := 2**(g_wg_dat_w-1)-1;
CONSTANT c_ampl_norm : REAL := sel_a_b(g_wg_dat_w < g_buf_dat_w, REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1), 1.0);
--CONSTANT c_ampl_norm : REAL := REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1); -- Use this if g_wg_dat_w < g_buf_dat_w, to avoid clipping
--CONSTANT c_ampl_norm : REAL := 1.0; -- Use this if g_wg_dat_w = g_buf_dat_w, because the stored waveform range is already -+c_buf_full_scale
--CONSTANT c_ampl_norm : REAL := REAL(c_buf_full_scale)/REAL(c_buf_full_scale+1); -- No need to use this, because the stored waveform range is already -+c_buf_full_scale
-
+
CONSTANT c_freq_unit : REAL := c_diag_wg_freq_unit; -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
CONSTANT c_ampl_unit : REAL := c_diag_wg_ampl_unit*c_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
CONSTANT c_phase_unit : REAL := c_diag_wg_phase_unit; -- ^= 1 degree
-
+
SIGNAL tb_end : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
SIGNAL restart : STD_LOGIC;
-
+
SIGNAL buf_rddat : STD_LOGIC_VECTOR(c_buf.dat_w-1 DOWNTO 0);
SIGNAL buf_rdval : STD_LOGIC;
SIGNAL buf_addr : STD_LOGIC_VECTOR(c_buf.adr_w-1 DOWNTO 0);
SIGNAL buf_rden : STD_LOGIC;
-
+
SIGNAL wg_ctrl : t_diag_wg;
-
+
SIGNAL wg_mode : NATURAL;
SIGNAL wg_freq : NATURAL;
SIGNAL wg_ampl : NATURAL;
SIGNAL wg_nof_samples : NATURAL;
SIGNAL wg_phase : NATURAL;
-
+
SIGNAL wg_ovr : STD_LOGIC;
SIGNAL wg_dat : STD_LOGIC_VECTOR(c_buf.dat_w-1 DOWNTO 0);
SIGNAL wg_val : STD_LOGIC;
SIGNAL wg_sync : STD_LOGIC;
-
+
BEGIN
rst <= '1', '0' AFTER c_clk_period/10;
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
-
+
wg_ctrl.mode <= TO_UVEC(wg_mode, c_diag_wg_mode_w);
wg_ctrl.freq <= TO_UVEC(wg_freq, c_diag_wg_freq_w);
wg_ctrl.ampl <= TO_UVEC(wg_ampl, c_diag_wg_ampl_w);
wg_ctrl.nof_samples <= TO_UVEC(wg_nof_samples, c_diag_wg_nofsamples_w);
wg_ctrl.phase <= TO_UVEC(wg_phase, c_diag_wg_phase_w);
-
+
p_mm : PROCESS
BEGIN
tb_end <= '0';
restart <= '0';
wg_mode <= c_diag_wg_mode_off;
-
+
---------------------------------------------------------------------------
-- >>> Single, repeat mode
wg_nof_samples <= c_wg_nof_samples;
-
+
-- >>> CALC mode
-- Cosinus with frequency Fs/2 (note sinus Fs/2 yields DC = 0)
-- wg_freq <= INTEGER(0.5 * c_freq_unit);
-- wg_phase <= INTEGER(90.0 * c_phase_unit);
-
+
-- Choosing 1.0*Fs to select Fs which is equivalent to DC, hence the DC value is then determined by phase
- -- this also applies to 2.0, 3.0, 4.0 etc
+ -- this also applies to 2.0, 3.0, 4.0 etc
-- wg_freq <= INTEGER(1.0 * c_freq_unit);
-- wg_phase <= INTEGER(45.0 * c_phase_unit);
-
+
-- Sinus Fs/16
wg_freq <= INTEGER(0.0625 * c_freq_unit);
--wg_freq <= INTEGER(511.0/512.0 * c_freq_unit);
--wg_freq <= INTEGER(1.0/512.0 * c_freq_unit);
--wg_freq <= INTEGER(1.0); -- minimum value, yields Fs/c_freq_unit Hz sinus
wg_phase <= INTEGER(0.0 * c_phase_unit);
-
+
-- Sinus Fs/17
-- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
-- wg_phase <= INTEGER(0.0 * c_phase_unit);
@@ -146,13 +146,13 @@ BEGIN
wg_ampl <= INTEGER(1.0 * c_ampl_unit); -- yields amplitude of c_wg_full_scale
-- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
-- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
-
+
WAIT UNTIL rising_edge(clk); -- align to rising edge
WAIT FOR c_clk_period*200;
-
+
---------------------------------------------------------------------------
-- >>> Select the different modes
-
+
-- CALC mode
wg_mode <= c_diag_wg_mode_calc;
restart <= '1';
@@ -164,14 +164,14 @@ BEGIN
restart <= '0';
WAIT FOR c_clk_period*3000;
--WAIT FOR 1 sec;
-
+
-- OFF mode
wg_mode <= c_diag_wg_mode_off;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
WAIT FOR c_clk_period*200;
-
+
-- SINGLE mode
wg_mode <= c_diag_wg_mode_single;
FOR I IN 0 TO 1 LOOP
@@ -181,7 +181,7 @@ BEGIN
WAIT FOR c_clk_period*c_buf.nof_dat;
WAIT FOR c_clk_period*300;
END LOOP;
-
+
-- REPEAT mode
wg_mode <= c_diag_wg_mode_repeat;
restart <= '1';
@@ -194,19 +194,19 @@ BEGIN
restart <= '0';
WAIT FOR c_clk_period*c_buf.nof_dat*5;
WAIT FOR c_clk_period*200;
-
+
-- OFF mode
wg_mode <= c_diag_wg_mode_off;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
WAIT FOR c_clk_period*200;
-
+
WAIT FOR c_clk_period*100;
tb_end <= '1';
WAIT;
END PROCESS;
-
+
-- Waveform buffer
u_buf : ENTITY common_lib.common_ram_crw_crw
GENERIC MAP (
@@ -231,7 +231,7 @@ BEGIN
rd_val_a => OPEN,
rd_val_b => buf_rdval
);
-
+
-- Waveform generator
u_wg : ENTITY work.diag_wg
GENERIC MAP (
@@ -258,6 +258,6 @@ BEGIN
out_val => wg_val,
out_sync => wg_sync
);
-
+
END tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
index 5fe5307223af3b54807bffcd691fe80b30ea4130..3727020eac42f779201e4a94f5d043d0b93ec80d 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
@@ -19,7 +19,15 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
-
+-- Purpose: Tb for WG
+-- Description: Verifies all WG modes.
+-- Usage:
+-- > as 10
+-- > run -all
+-- . Use select rigth mouse in Wave window on wg_dat and choose radix -->
+-- decimal and format --> analogue (automatic)
+-- . Observe state in diag_wg(0).
+
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
@@ -27,15 +35,6 @@ USE IEEE.MATH_REAL.ALL;
USE common_lib.common_pkg.ALL;
USE work.diag_pkg.ALL;
--- Usage:
--- > do wave_diag_wg_wideband.do
--- > run -all
---
--- . Use select rigth mouse in wave window on wg_dat and choose 'format --> analogue (automatic)'
--- . run 10 us to see CALC mode waveform output at proper automatic scale
--- . run 100 us to see SINGLE and REPEAT mode waveform output at proper automatic scale
-
-
ENTITY tb_diag_wg_wideband IS
GENERIC (
-- Wideband parameters
@@ -52,49 +51,51 @@ ARCHITECTURE tb OF tb_diag_wg_wideband IS
CONSTANT c_clk_freq : NATURAL := 200; -- MHz
CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps;
-
+
-- Default WG settings
CONSTANT c_buf_nof_dat : NATURAL := 2**g_buf_addr_w;
-
+
CONSTANT c_wg_gain_w : NATURAL := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
-- . use gain 2**0 = 1 to have fulle scale without clipping
-- . use gain 2**g_calc_gain_w > 1 to cause clipping
-
+
CONSTANT c_buf_full_scale : NATURAL := 2**(g_buf_dat_w-1)-1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
CONSTANT c_wg_full_scale : NATURAL := 2**(g_wg_dat_w-1)-1;
CONSTANT c_ampl_norm : REAL := sel_a_b(g_wg_dat_w < g_buf_dat_w, REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1), 1.0);
--CONSTANT c_ampl_norm : REAL := REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1); -- Use this if g_wg_dat_w < g_buf_dat_w, to avoid clipping
--CONSTANT c_ampl_norm : REAL := 1.0; -- Use this if g_wg_dat_w = g_buf_dat_w, because the stored waveform range is already -+c_buf_full_scale
--CONSTANT c_ampl_norm : REAL := REAL(c_buf_full_scale)/REAL(c_buf_full_scale+1); -- No need to use this, because the stored waveform range is already -+c_buf_full_scale
-
+
CONSTANT c_freq_unit : REAL := c_diag_wg_freq_unit; -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
CONSTANT c_ampl_unit : REAL := c_diag_wg_ampl_unit*c_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
CONSTANT c_phase_unit : REAL := c_diag_wg_phase_unit; -- ^= 1 degree
-
+
-- Wideband WG settings
CONSTANT c_sample_period : TIME := (10**6 / (c_clk_freq*g_wideband_factor)) * 1 ps;
-
+
TYPE t_buf_dat_arr IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(g_buf_dat_w-1 DOWNTO 0);
-
+
SIGNAL tb_end : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
SIGNAL restart : STD_LOGIC;
-
+
SIGNAL wg_ctrl : t_diag_wg;
-
+ SIGNAL cur_ctrl : t_diag_wg;
+ SIGNAL mon_ctrl : t_diag_wg;
+
SIGNAL wg_mode : NATURAL;
SIGNAL wg_freq : NATURAL;
SIGNAL wg_ampl : NATURAL;
SIGNAL wg_nof_samples : NATURAL;
SIGNAL wg_phase : NATURAL;
-
+
-- Wideband WG output is big endian, so first output sample in MSBit, MSData
SIGNAL out_ovr : STD_LOGIC_VECTOR(g_wideband_factor -1 DOWNTO 0);
SIGNAL out_dat : STD_LOGIC_VECTOR(g_wideband_factor*g_buf_dat_w-1 DOWNTO 0);
SIGNAL out_val : STD_LOGIC_VECTOR(g_wideband_factor -1 DOWNTO 0);
SIGNAL out_sync : STD_LOGIC_VECTOR(g_wideband_factor -1 DOWNTO 0);
-
+
SIGNAL wg_ovr : STD_LOGIC_VECTOR(0 TO g_wideband_factor-1);
SIGNAL wg_dat : t_buf_dat_arr(0 TO g_wideband_factor-1);
SIGNAL wg_val : STD_LOGIC_VECTOR(0 TO g_wideband_factor-1);
@@ -106,47 +107,47 @@ ARCHITECTURE tb OF tb_diag_wg_wideband IS
SIGNAL sample_dat : STD_LOGIC_VECTOR(g_buf_dat_w-1 DOWNTO 0);
SIGNAL sample_val : STD_LOGIC;
SIGNAL sample_sync : STD_LOGIC;
-
+
BEGIN
rst <= '1', '0' AFTER c_clk_period/10;
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
-
+
sample_clk <= NOT sample_clk OR tb_end AFTER c_sample_period/2;
-
+
wg_ctrl.mode <= TO_UVEC(wg_mode, c_diag_wg_mode_w);
wg_ctrl.freq <= TO_UVEC(wg_freq, c_diag_wg_freq_w);
wg_ctrl.ampl <= TO_UVEC(wg_ampl, c_diag_wg_ampl_w);
wg_ctrl.nof_samples <= TO_UVEC(wg_nof_samples, c_diag_wg_nofsamples_w);
wg_ctrl.phase <= TO_UVEC(wg_phase, c_diag_wg_phase_w);
-
+
p_mm : PROCESS
BEGIN
tb_end <= '0';
restart <= '0';
wg_mode <= c_diag_wg_mode_off;
-
+
---------------------------------------------------------------------------
-- >>> Single, repeat mode
wg_nof_samples <= c_buf_nof_dat; -- must be <= c_buf_nof_dat
-
+
-- >>> CALC mode
-- Cosinus with frequency Fs/2 (note sinus Fs/2 yields DC = 0)
-- wg_freq <= INTEGER(0.5 * c_freq_unit);
-- wg_phase <= INTEGER(90.0 * c_phase_unit);
-
+
-- Choosing 1.0*Fs to select Fs which is equivalent to DC, hence the DC value is then determined by phase
- -- this also applies to 2.0, 3.0, 4.0 etc
+ -- this also applies to 2.0, 3.0, 4.0 etc
-- wg_freq <= INTEGER(1.0 * c_freq_unit);
-- wg_phase <= INTEGER(45.0 * c_phase_unit);
-
+
-- Sinus Fs/16
wg_freq <= INTEGER(0.0625 * c_freq_unit);
--wg_freq <= INTEGER(511.0/512.0 * c_freq_unit);
wg_freq <= INTEGER(1.0/512.0 * c_freq_unit);
--wg_freq <= INTEGER(1.0); -- minimum value, yields Fs/c_freq_unit Hz sinus
wg_phase <= INTEGER(0.0 * c_phase_unit);
-
+
-- Sinus Fs/17
-- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
-- wg_phase <= INTEGER(0.0 * c_phase_unit);
@@ -154,68 +155,115 @@ BEGIN
wg_ampl <= INTEGER(1.0 * c_ampl_unit); -- yields amplitude of c_wg_full_scale
-- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
-- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
-
+
WAIT UNTIL rising_edge(clk); -- align to rising edge
+ cur_ctrl <= wg_ctrl;
WAIT FOR c_clk_period*200;
-
+
---------------------------------------------------------------------------
-- >>> Select the different modes
-
+
-- CALC mode
wg_mode <= c_diag_wg_mode_calc;
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected hold OFF)" SEVERITY ERROR;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
+ cur_ctrl <= wg_ctrl;
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected new CALC)" SEVERITY ERROR;
+
WAIT FOR c_clk_period*3000;
+
+ wg_ampl <= INTEGER(0.5 * c_ampl_unit); -- change ampl immediately
+ WAIT FOR c_clk_period*1;
+ cur_ctrl <= wg_ctrl;
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected new CALC ampl)" SEVERITY ERROR;
+
+ WAIT FOR c_clk_period*3000;
+
+ wg_phase <= INTEGER(90.0 * c_phase_unit); -- no change phase without restart
+ wg_freq <= INTEGER(0.5/512.0 * c_freq_unit); -- no change freq without restart
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected hold CALC phase and freq)" SEVERITY ERROR;
+
+ WAIT FOR c_clk_period*3000;
+
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
+ cur_ctrl <= wg_ctrl;
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected new CALC phase and freq)" SEVERITY ERROR;
+
WAIT FOR c_clk_period*3000;
- --WAIT FOR 1 sec;
-
+
-- OFF mode
wg_mode <= c_diag_wg_mode_off;
+ WAIT FOR c_clk_period*1;
+ cur_ctrl <= wg_ctrl; -- OFF mode takes effect immediately
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected immediately OFF)" SEVERITY ERROR;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected still OFF)" SEVERITY ERROR;
+
WAIT FOR c_clk_period*200;
-
+
-- SINGLE mode
wg_mode <= c_diag_wg_mode_single;
- FOR I IN 0 TO 1 LOOP
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected hold OFF)" SEVERITY ERROR;
+ FOR I IN 0 TO 3 LOOP
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
+ cur_ctrl <= wg_ctrl;
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected new SINGLE)" SEVERITY ERROR;
WAIT FOR c_clk_period*c_buf_nof_dat;
WAIT FOR c_clk_period*300;
END LOOP;
-
+
-- REPEAT mode
wg_mode <= c_diag_wg_mode_repeat;
- restart <= '1';
- WAIT FOR c_clk_period*1;
- restart <= '0';
- WAIT FOR c_clk_period*c_buf_nof_dat*5;
- WAIT FOR c_clk_period*200;
- restart <= '1';
- WAIT FOR c_clk_period*1;
- restart <= '0';
- WAIT FOR c_clk_period*c_buf_nof_dat*5;
- WAIT FOR c_clk_period*200;
-
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected hold SINGLE)" SEVERITY ERROR;
+ FOR I IN 0 TO 1 LOOP
+ restart <= '1';
+ WAIT FOR c_clk_period*1;
+ restart <= '0';
+ cur_ctrl <= wg_ctrl;
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected new REPEAT)" SEVERITY ERROR;
+ WAIT FOR c_clk_period*c_buf_nof_dat*5;
+ WAIT FOR c_clk_period*200;
+ END LOOP;
+
-- OFF mode
wg_mode <= c_diag_wg_mode_off;
+ WAIT FOR c_clk_period*1;
+ cur_ctrl <= wg_ctrl; -- OFF mode takes effect immediately, no need for restart
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected immediately OFF)" SEVERITY ERROR;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected still OFF)" SEVERITY ERROR;
+
WAIT FOR c_clk_period*200;
-
+
WAIT FOR c_clk_period*100;
tb_end <= '1';
WAIT;
END PROCESS;
-
-
+
+
u_wideband_wg : ENTITY work.diag_wg_wideband
GENERIC MAP (
-- Wideband parameters
@@ -231,7 +279,7 @@ BEGIN
-- Memory-mapped clock domain
mm_rst => '0',
mm_clk => '0',
-
+
mm_wrdata => (OTHERS=>'0'),
mm_address => (OTHERS=>'0'),
mm_wr => '0',
@@ -243,15 +291,16 @@ BEGIN
st_rst => rst,
st_clk => clk,
st_restart => restart,
-
+
st_ctrl => wg_ctrl,
+ st_mon_ctrl => mon_ctrl,
out_ovr => out_ovr,
out_dat => out_dat,
out_val => out_val,
out_sync => out_sync
);
-
+
-- Map wideband WG out_* slv to wg_* arrays to ease interpretation in wave window
gen_wires : FOR I IN 0 TO g_wideband_factor-1 GENERATE
wg_ovr(I) <= out_ovr( g_wideband_factor-I-1);
@@ -259,8 +308,8 @@ BEGIN
wg_val(I) <= out_val( g_wideband_factor-I-1);
wg_sync(I) <= out_sync( g_wideband_factor-I-1);
END GENERATE;
-
- -- View WG output at the sample rate
+
+ -- View WG output at the sample rate
p_sample : PROCESS(sample_clk)
BEGIN
IF rising_edge(sample_clk) THEN
@@ -275,6 +324,6 @@ BEGIN
sample_sync <= wg_sync(sample_cnt);
END IF;
END PROCESS;
-
+
END tb;
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index 64e18fe4e39c713ae535859a07f67f936db76315..9cca7c30d99b6efd5ea8c17f1b7c3d549c246ff1 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -129,7 +129,6 @@ peripherals:
address_offset: 1 * MM_BUS_SIZE
access_mode: RO
-
- peripheral_name: dp_bsn_source # pi_dp_bsn_source.py
peripheral_description: "Block Sequence Number (BSN) source for timestamping blocks of data samples."
parameters:
diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 34a2c49f89a64e30918443ee012c44e85d40f1d5..fdead4ddbcbdaa5a5e5274ef6dbb2a49e688a1da 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -300,6 +300,7 @@ test_bench_files =
tb/vhdl/tb_tb_dp_block_validate_channel.vhd
tb/vhdl/tb_tb_dp_bsn_align.vhd
tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
+ tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
tb/vhdl/tb_tb_dp_concat.vhd
@@ -357,7 +358,6 @@ regression_test_vhdl =
tb/vhdl/tb_dp_latency_adapter.vhd
tb/vhdl/tb_dp_shiftreg.vhd
tb/vhdl/tb_dp_bsn_source.vhd
- tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
tb/vhdl/tb_mms_dp_bsn_source.vhd
tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
@@ -372,6 +372,7 @@ regression_test_vhdl =
tb/vhdl/tb_tb_dp_block_from_mm.vhd
tb/vhdl/tb_tb_dp_block_validate_channel.vhd
tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
+ tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
tb/vhdl/tb_tb_dp_concat.vhd
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
index 0d5b21ea615ec19a28357937cc811b4c43b23ddc..22099bf168a065ce4064308f9e30c4a84b12f1e0 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
@@ -111,29 +111,31 @@ USE work.dp_stream_pkg.ALL;
ENTITY dp_bsn_sync_scheduler IS
GENERIC (
- g_bsn_w : NATURAL := c_dp_stream_bsn_w;
- g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
- g_pipeline : NATURAL := 1 -- use '1' on HW, use '0' for easier debugging in Wave window
+ g_bsn_w : NATURAL := c_dp_stream_bsn_w;
+ g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
+ g_ctrl_interval_size_min : NATURAL := 1; -- Minimum interval size to use if MM write interval size is set too small.
+ g_pipeline : NATURAL := 1 -- use '1' on HW, use '0' for easier debugging in Wave window
);
PORT (
- rst : IN STD_LOGIC;
- clk : IN STD_LOGIC;
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
-- M&C
- ctrl_enable : IN STD_LOGIC;
- ctrl_enable_evt : IN STD_LOGIC;
- ctrl_interval_size : IN NATURAL;
- ctrl_start_bsn : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
- mon_current_input_bsn : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
- mon_input_bsn_at_sync : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
- mon_output_enable : OUT STD_LOGIC;
- mon_output_sync_bsn : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ ctrl_enable : IN STD_LOGIC;
+ ctrl_enable_evt : IN STD_LOGIC;
+ ctrl_interval_size : IN NATURAL;
+ ctrl_start_bsn : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+ mon_current_input_bsn : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ mon_input_bsn_at_sync : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ mon_output_enable : OUT STD_LOGIC;
+ mon_output_interval_size : OUT NATURAL;
+ mon_output_sync_bsn : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
-- Streaming
- in_sosi : IN t_dp_sosi;
- out_sosi : OUT t_dp_sosi;
- out_start : OUT STD_LOGIC; -- pulse at out_sosi.sync at ctrl_start_bsn
- out_enable : OUT STD_LOGIC -- for tb verification purposes
+ in_sosi : IN t_dp_sosi;
+ out_sosi : OUT t_dp_sosi;
+ out_start : OUT STD_LOGIC; -- pulse at out_sosi.sync at ctrl_start_bsn
+ out_enable : OUT STD_LOGIC -- for tb verification purposes
);
END dp_bsn_sync_scheduler;
@@ -158,7 +160,7 @@ ARCHITECTURE rtl OF dp_bsn_sync_scheduler IS
output_sync_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
END RECORD;
- CONSTANT c_reg_rst : t_reg := ('0', '0', 0, 0, (OTHERS=>'0'), (OTHERS=>'0'), 0, 0, 0, 0, 0, '1', '0', '0', (OTHERS=>'0'));
+ CONSTANT c_reg_rst : t_reg := ('0', '0', 0, g_ctrl_interval_size_min, (OTHERS=>'0'), (OTHERS=>'0'), 0, 0, 0, 0, 0, '1', '0', '0', (OTHERS=>'0'));
-- Local registers
SIGNAL r : t_reg;
@@ -173,10 +175,11 @@ BEGIN
ASSERT g_block_size >= 2 REPORT "g_block_size must be >= 2." SEVERITY FAILURE;
-- Capture monitoring info
- mon_current_input_bsn <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sop = '1';
- mon_input_bsn_at_sync <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sync = '1';
- mon_output_enable <= r.output_enable;
- mon_output_sync_bsn <= r.output_sync_bsn;
+ mon_current_input_bsn <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sop = '1';
+ mon_input_bsn_at_sync <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sync = '1';
+ mon_output_enable <= r.output_enable;
+ mon_output_interval_size <= g_ctrl_interval_size_min WHEN rst='1' ELSE r.interval_size WHEN rising_edge(clk) AND output_start = '1';
+ mon_output_sync_bsn <= r.output_sync_bsn;
p_clk : PROCESS(rst, clk)
BEGIN
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
index 75b42316d077b32591da03f6a12aff7ee6da26d9..9cfe48f8dba79806999f160015e2e625b4753190 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
@@ -22,7 +22,8 @@
--
-- wi Bits Access Type Name
-- 0 [0] RW boolean ctrl_enable, '1' is on, '0' is FALSE is off
--- 1 [31:0] RW uint32 ctrl_interval_size
+-- 1 [31:0] RW uint32 W: ctrl_interval_size
+-- R: mon_output_interval_size
-- 2 [31:0] RW uint64 ctrl_start_bsn[31:0]
-- 3 [31:0] RW ctrl_start_bsn[63:32]
-- 4 [31:0] RO uint64 mon_current_input_bsn[31:0]
@@ -63,7 +64,7 @@ USE work.dp_stream_pkg.ALL;
ENTITY mmp_dp_bsn_sync_scheduler IS
GENERIC (
g_bsn_w : NATURAL := c_dp_stream_bsn_w;
- g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
+ g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
g_ctrl_interval_size_min : NATURAL := 1 -- Minimum interval size to use if MM write interval size is set too small.
);
PORT (
@@ -95,20 +96,21 @@ ARCHITECTURE str OF mmp_dp_bsn_sync_scheduler IS
-- init_sl : STD_LOGIC; -- optional, init all dat words to std_logic '0', '1' or 'X'
CONSTANT c_mm_reg : t_c_mem := (1, 4, c_word_w, 12, '0');
- SIGNAL reg_wr_arr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat -1 DOWNTO 0);
- SIGNAL reg_wr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0);
- SIGNAL reg_rd : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
-
- SIGNAL wr_ctrl_enable : STD_LOGIC;
- SIGNAL wr_ctrl_enable_evt : STD_LOGIC;
- SIGNAL ctrl_enable : STD_LOGIC := '0';
- SIGNAL ctrl_enable_evt : STD_LOGIC := '0';
- SIGNAL ctrl_interval_size : NATURAL;
- SIGNAL ctrl_start_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL mon_current_input_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
- SIGNAL mon_input_bsn_at_sync : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
- SIGNAL mon_output_enable : STD_LOGIC;
- SIGNAL mon_output_sync_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ SIGNAL reg_wr_arr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat -1 DOWNTO 0);
+ SIGNAL reg_wr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0);
+ SIGNAL reg_rd : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL wr_ctrl_enable : STD_LOGIC;
+ SIGNAL wr_ctrl_enable_evt : STD_LOGIC;
+ SIGNAL ctrl_enable : STD_LOGIC := '0';
+ SIGNAL ctrl_enable_evt : STD_LOGIC := '0';
+ SIGNAL ctrl_interval_size : NATURAL;
+ SIGNAL ctrl_start_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL mon_current_input_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ SIGNAL mon_input_bsn_at_sync : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ SIGNAL mon_output_enable : STD_LOGIC;
+ SIGNAL mon_output_interval_size : NATURAL;
+ SIGNAL mon_output_sync_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
-- Resize BSN values to 64 bit
SIGNAL wr_start_bsn_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
@@ -151,7 +153,7 @@ BEGIN
-- . Read
reg_rd( 0) <= ctrl_enable; -- read back internal ctrl_enable
- reg_rd( 2*c_word_w-1 DOWNTO 1*c_word_w) <= TO_UVEC(ctrl_interval_size, c_word_w);
+ reg_rd( 2*c_word_w-1 DOWNTO 1*c_word_w) <= TO_UVEC(mon_output_interval_size, c_word_w);
reg_rd( 3*c_word_w-1 DOWNTO 2*c_word_w) <= wr_start_bsn_64( c_word_w-1 DOWNTO 0); -- low word
reg_rd( 4*c_word_w-1 DOWNTO 3*c_word_w) <= wr_start_bsn_64( 2*c_word_w-1 DOWNTO c_word_w); -- high word
reg_rd( 5*c_word_w-1 DOWNTO 4*c_word_w) <= rd_current_input_bsn_64( c_word_w-1 DOWNTO 0); -- low word
@@ -189,29 +191,31 @@ BEGIN
u_dp_bsn_sync_scheduler : ENTITY work.dp_bsn_sync_scheduler
GENERIC MAP (
- g_bsn_w => g_bsn_w,
- g_block_size => g_block_size,
- g_pipeline => 1
+ g_bsn_w => g_bsn_w,
+ g_block_size => g_block_size,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min,
+ g_pipeline => 1
)
PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
+ rst => dp_rst,
+ clk => dp_clk,
-- M&C
- ctrl_enable => ctrl_enable,
- ctrl_enable_evt => ctrl_enable_evt,
- ctrl_interval_size => ctrl_interval_size,
- ctrl_start_bsn => ctrl_start_bsn,
- mon_current_input_bsn => mon_current_input_bsn,
- mon_input_bsn_at_sync => mon_input_bsn_at_sync,
- mon_output_enable => mon_output_enable,
- mon_output_sync_bsn => mon_output_sync_bsn,
+ ctrl_enable => ctrl_enable,
+ ctrl_enable_evt => ctrl_enable_evt,
+ ctrl_interval_size => ctrl_interval_size,
+ ctrl_start_bsn => ctrl_start_bsn,
+ mon_current_input_bsn => mon_current_input_bsn,
+ mon_input_bsn_at_sync => mon_input_bsn_at_sync,
+ mon_output_enable => mon_output_enable,
+ mon_output_interval_size => mon_output_interval_size,
+ mon_output_sync_bsn => mon_output_sync_bsn,
-- Streaming
- in_sosi => in_sosi,
- out_sosi => out_sosi,
- out_start => out_start,
- out_enable => out_enable
+ in_sosi => in_sosi,
+ out_sosi => out_sosi,
+ out_start => out_start,
+ out_enable => out_enable
);
END str;
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
index a7b2234a79a41c7fb71c5250e2a999c8d3cbb43e..d9fd975a4eb30877fd101260a963134aab754ba7 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
@@ -45,6 +45,9 @@ USE work.dp_stream_pkg.ALL;
USE work.tb_dp_pkg.ALL;
ENTITY tb_mmp_dp_bsn_align_v2 IS
+ GENERIC (
+ g_lost_input : BOOLEAN := TRUE -- when TRUE use c_nof_streams-1 as lost input
+ );
END tb_mmp_dp_bsn_align_v2;
@@ -60,11 +63,12 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
-- Fixed dut generics
-- . for dp_bsn_align_v2
- CONSTANT c_nof_streams : NATURAL := 3;
+ CONSTANT c_nof_streams : NATURAL := 5;
CONSTANT c_bsn_latency_max : NATURAL := 1;
CONSTANT c_nof_aligners_max : POSITIVE := 1; -- fixed in this tb
CONSTANT c_block_size : NATURAL := 11;
CONSTANT c_block_period : NATURAL := 11;
+ CONSTANT c_block_per_sync : NATURAL := 7;
CONSTANT c_bsn_w : NATURAL := c_dp_stream_bsn_w;
CONSTANT c_data_w : NATURAL := 16;
CONSTANT c_data_replacement_value : INTEGER := 17;
@@ -73,7 +77,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
CONSTANT c_pipeline_output : NATURAL := 1;
CONSTANT c_rd_latency : NATURAL := 2;
-- . for mms_dp_bsn_monitor_v2
- CONSTANT c_nof_clk_per_sync : NATURAL := 200*10**6;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_block_per_sync * c_block_period;
CONSTANT c_nof_input_bsn_monitors : NATURAL := c_nof_streams;
CONSTANT c_use_bsn_output_monitor : BOOLEAN := TRUE;
@@ -96,8 +100,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
CONSTANT c_bsn_init : NATURAL := 3;
CONSTANT c_channel_init : INTEGER := 0;
CONSTANT c_err_init : NATURAL := 247;
- CONSTANT c_sync_period : NATURAL := 7;
- CONSTANT c_sync_offset : NATURAL := 2;
+ CONSTANT c_sync_bsn_offset : NATURAL := 2;
CONSTANT c_gap_size : NATURAL := c_block_period - c_block_size;
-- DUT latency
@@ -138,8 +141,8 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
SIGNAL reg_output_monitor_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL reg_output_monitor_cipo : t_mem_cipo;
- SIGNAL mon_latency_input_arr : t_nat_natural_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL mon_latency_output : NATURAL;
+ SIGNAL mon_latency_input_arr : t_integer_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL mon_latency_output : INTEGER;
-- DP clock domain
SIGNAL dp_clk : STD_LOGIC := '1';
@@ -173,7 +176,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
SIGNAL out_err_arr : t_err_arr;
SIGNAL verify_done_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0) := (OTHERS => '0');
- SIGNAL verify_done : STD_LOGIC;
+ SIGNAL verify_done : STD_LOGIC := '0';
SIGNAL hold_out_sop_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL expected_out_bsn_arr : t_bsn_arr;
@@ -257,15 +260,19 @@ BEGIN
FOR I IN 0 TO c_nof_streams-1 LOOP
proc_mem_mm_bus_rd(6 + I*c_reg_bsn_monitor_span, mm_clk, reg_input_monitor_cipo, reg_input_monitor_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
- mon_latency_input_arr(I) <= TO_UINT(reg_input_monitor_cipo.rddata);
+ mon_latency_input_arr(I) <= TO_SINT(reg_input_monitor_cipo.rddata(31 DOWNTO 0));
proc_common_wait_some_cycles(mm_clk, 1);
- ASSERT mon_latency_input_arr(I) = func_input_delay(I) REPORT "Wrong input BSN monitor latency for input " & int_to_str(I) SEVERITY ERROR;
+ IF g_lost_input = TRUE AND I = c_nof_streams-1 THEN
+ ASSERT mon_latency_input_arr(I) = -1 REPORT "Wrong input BSN monitor latency timeout for input " & int_to_str(I) SEVERITY ERROR;
+ ELSE
+ ASSERT mon_latency_input_arr(I) = func_input_delay(I) REPORT "Wrong input BSN monitor latency for input " & int_to_str(I) SEVERITY ERROR;
+ END IF;
END LOOP;
-- Read output BSN monitor
proc_mem_mm_bus_rd(6, mm_clk, reg_output_monitor_cipo, reg_output_monitor_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
- mon_latency_output <= TO_UINT(reg_output_monitor_cipo.rddata);
+ mon_latency_output <= TO_SINT(reg_output_monitor_cipo.rddata(31 DOWNTO 0));
proc_common_wait_some_cycles(mm_clk, 1);
ASSERT mon_latency_output = c_total_latency REPORT "Wrong output BSN monitor latency" SEVERITY ERROR;
@@ -299,14 +306,14 @@ BEGIN
FOR S IN 0 TO c_tb_nof_restart-1 LOOP
v_bsn := c_bsn_init;
FOR R IN 0 TO c_tb_nof_blocks-1 LOOP
- v_sync := sel_a_b(v_bsn MOD c_sync_period = c_sync_offset, '1', '0');
+ v_sync := sel_a_b(v_bsn MOD c_block_per_sync = c_sync_bsn_offset, '1', '0');
proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_data_w, v_data, 0, 0, c_block_size, v_channel, v_err, v_sync, TO_UVEC(v_bsn, c_bsn_w), dp_clk, sl1, ref_siso_arr(I), ref_sosi_arr(I));
v_bsn := v_bsn + 1;
v_data := v_data + c_block_size;
proc_common_wait_some_cycles(dp_clk, c_gap_size); -- create gap between frames
END LOOP;
-- Create gap between restarts
- proc_common_wait_some_cycles(dp_clk, 100);
+ proc_common_wait_some_cycles(dp_clk, 10);
restart_cnt_arr(I) <= restart_cnt_arr(I) + 1;
END LOOP;
@@ -314,10 +321,15 @@ BEGIN
-- . default c_bsn_latency_max blocks remain in DUT buffer
expected_out_bsn_arr(I) <= TO_UVEC(v_bsn-1 - c_align_latency_nof_blocks, c_bsn_w);
expected_out_data_arr(I) <= TO_UVEC(v_data-1 - c_align_latency_nof_valid, c_data_w);
- -- . default no data is lost, so all channel(0) lost data flags are 0
+ -- . default no data is lost, so all channel(bit 0) lost data flags are 0
expected_out_channel_arr(I) <= TO_DP_CHANNEL(0);
-
- proc_common_wait_some_cycles(dp_clk, 100);
+ IF g_lost_input = TRUE THEN
+ IF I = c_nof_streams-1 THEN
+ expected_out_data_arr(I) <= TO_UVEC(c_data_replacement_value, c_data_w);
+ expected_out_channel_arr(I) <= TO_DP_CHANNEL(1);
+ END IF;
+ END IF;
+ proc_common_wait_some_cycles(dp_clk, 10);
verify_done_arr(I) <= '1';
proc_common_wait_some_cycles(dp_clk, 1);
verify_done_arr(I) <= '0';
@@ -329,15 +341,25 @@ BEGIN
END PROCESS;
END GENERATE;
- verify_done <= verify_done_arr(0);
+ verify_done <= '1' WHEN verify_done_arr(0) = '1';
restart_cnt <= restart_cnt_arr(0);
dp_end <= vector_and(dp_end_arr);
-- Model misalignment latency between the input streams to have different
-- input BSN monitor latencies
- gen_rx_sosi_arr : FOR I IN c_nof_streams-1 DOWNTO 0 GENERATE
- in_sosi_arr(I) <= TRANSPORT ref_sosi_arr(I) AFTER func_input_delay(I) * c_dp_clk_period;
+ no_lost_input : IF g_lost_input = FALSE GENERATE
+ gen_in_sosi_arr : FOR I IN c_nof_streams-1 DOWNTO 0 GENERATE
+ in_sosi_arr(I) <= TRANSPORT ref_sosi_arr(I) AFTER func_input_delay(I) * c_dp_clk_period;
+ END GENERATE;
+ END GENERATE;
+
+ one_lost_input : IF g_lost_input = TRUE GENERATE
+ -- Model missing enabled input stream at index c_lost_input = c_nof_streams-1
+ in_sosi_arr(c_nof_streams-1) <= c_dp_sosi_rst;
+ gen_in_sosi_arr : FOR I IN c_nof_streams-2 DOWNTO 0 GENERATE
+ in_sosi_arr(I) <= TRANSPORT ref_sosi_arr(I) AFTER func_input_delay(I) * c_dp_clk_period;
+ END GENERATE;
END GENERATE;
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
index ce4e5f605e7efbba13cb3ec7a972a5d9b9548805..43162d9c6df7dd1b3e4b768e0353f9f65d51e791 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
@@ -52,6 +52,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_sync_scheduler IS
CONSTANT c_nof_block_per_input_sync : NATURAL := 17;
CONSTANT c_nof_block_per_output_sync : NATURAL := 5;
CONSTANT c_block_size : NATURAL := 10;
+ CONSTANT c_ctrl_interval_size_min : NATURAL := 19; -- Minimum interval size to use if MM write interval size is set too small.
CONSTANT c_input_gap_size : NATURAL := 3;
CONSTANT c_sim_nof_blocks : NATURAL := c_nof_block_per_input_sync * c_nof_input_sync;
@@ -75,6 +76,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_sync_scheduler IS
SIGNAL ctrl_start_bsn_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
SIGNAL mon_output_enable : STD_LOGIC;
+ SIGNAL mon_output_interval_size : NATURAL;
SIGNAL mon_current_input_bsn_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
SIGNAL mon_input_bsn_at_sync_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
SIGNAL mon_output_sync_bsn_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
@@ -118,6 +120,13 @@ BEGIN
proc_common_wait_some_cycles(mm_clk, 1);
ASSERT mon_block_size = c_block_size REPORT "Wrong block_size." SEVERITY ERROR;
+ -- . Read mon_output_interval_size
+ proc_mem_mm_bus_rd(1, mm_clk, reg_miso, reg_mosi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ mon_output_interval_size <= TO_UINT(reg_miso.rddata(c_word_w-1 DOWNTO 0));
+ proc_common_wait_some_cycles(mm_clk, 1);
+ ASSERT mon_output_interval_size = c_ctrl_interval_size_min REPORT "Wrong minimum output interval_size." SEVERITY ERROR;
+
-- . Read mon_output_enable
proc_mem_mm_bus_rd(8, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
@@ -214,10 +223,16 @@ BEGIN
proc_mem_mm_bus_rd_latency(1, mm_clk);
mon_output_enable <= reg_miso.rddata(0);
+ -- . Read mon_output_interval_size
+ proc_mem_mm_bus_rd(1, mm_clk, reg_miso, reg_mosi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ mon_output_interval_size <= TO_UINT(reg_miso.rddata(c_word_w-1 DOWNTO 0));
+
-- Verify output is on and running
proc_common_wait_some_cycles(mm_clk, 1);
ASSERT mon_output_enable = '1' REPORT "mon_output_enable is not enabled." SEVERITY ERROR;
ASSERT out_enable = '1' REPORT "output_enable is not enabled." SEVERITY ERROR;
+ ASSERT mon_output_interval_size = c_ctrl_interval_size REPORT "mon_output_interval_size is not ctrl_interval_size." SEVERITY ERROR;
---------------------------------------------------------------------------
-- Check that monitor BSN are incrementing
@@ -381,8 +396,9 @@ BEGIN
u_mmp_dp_bsn_sync_scheduler : ENTITY work.mmp_dp_bsn_sync_scheduler
GENERIC MAP (
- g_bsn_w => c_bsn_w,
- g_block_size => c_block_size
+ g_bsn_w => c_bsn_w,
+ g_block_size => c_block_size,
+ g_ctrl_interval_size_min => c_ctrl_interval_size_min
)
PORT MAP (
-- Clocks and reset
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7eea68cc3bdd53a99d18a3334f5df6d2a1fa3f16
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
@@ -0,0 +1,46 @@
+-- --------------------------------------------------------------------------
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+--
+-- Author: E. Kooistra, 2 march 2022
+-- Purpose: Regression multi tb for mmp_dp_bsn_align_v2
+-- Description:
+-- Usage:
+-- > as 3
+-- > run -all
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE work.tb_dp_pkg.ALL;
+
+
+ENTITY tb_tb_mmp_dp_bsn_align_v2 IS
+END tb_tb_mmp_dp_bsn_align_v2;
+
+
+ARCHITECTURE tb OF tb_tb_mmp_dp_bsn_align_v2 IS
+
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+
+BEGIN
+
+ -- g_lost_input : BOOLEAN := FALSE
+
+ u_no_lost_input : ENTITY work.tb_mmp_dp_bsn_align_v2 GENERIC MAP (FALSE);
+ u_one_lost_input : ENTITY work.tb_mmp_dp_bsn_align_v2 GENERIC MAP (TRUE);
+
+END tb;
diff --git a/libraries/dsp/fft/hdllib.cfg b/libraries/dsp/fft/hdllib.cfg
index a75778467bbdea6b49354de1f431115a5b5dd9d8..aee1489da150feebf22084542d8ebd71b86484e8 100644
--- a/libraries/dsp/fft/hdllib.cfg
+++ b/libraries/dsp/fft/hdllib.cfg
@@ -21,7 +21,8 @@ synth_files =
test_bench_files =
tb/vhdl/tb_fft_pkg.vhd
- tb/vhdl/tb_fft_functions.vhd
+ tb/vhdl/tb_fft_functions.vhd
+ tb/vhdl/tb_fft_lfsr.vhd
tb/vhdl/tb_fft_switch.vhd
tb/vhdl/tb_fft_sepa.vhd
tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
@@ -32,11 +33,12 @@ test_bench_files =
tb/vhdl/tb_fft_wide_unit.vhd
tb/vhdl/tb_mmf_fft_r2.vhd
tb/vhdl/tb_mmf_fft_wide_unit.vhd
- tb/vhdl/tb_tb_fft_r2_pipe.vhd
+ tb/vhdl/tb_tb_fft_r2_pipe.vhd
tb/vhdl/tb_tb_fft_r2_par.vhd
tb/vhdl/tb_tb_fft_r2_wide.vhd
regression_test_vhdl =
+ tb/vhdl/tb_fft_lfsr.vhd
tb/vhdl/tb_fft_switch.vhd
tb/vhdl/tb_tb_fft_r2_pipe.vhd
tb/vhdl/tb_tb_fft_r2_par.vhd
diff --git a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
index 56f5b5e453f9a2e009a05c2418f6890ee6aa22e3..7f53b0a398f8dddef39cc056eb7225767d53362b 100644
--- a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
@@ -21,12 +21,20 @@
-- Author: ported by E. Kooistra, original 2004 by W. Lubberhuizen / W. Poeisz
-- Purpose: Scramble quantization noise crosstalk between two real inputs
-- Description: Ported from LOFAR1, see readme_lofar1.txt
--- Remark: Copy from applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
+-- Remark:
+-- . Copy from applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
+-- . The g_seed must be > 0 for LFSR period is 2**c_fft_lfsr_len - 1. Value
+-- g_seed = 0 causes the LFSR to remain stuck at 0.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
+USE work.fft_pkg.ALL;
ENTITY fft_lfsr IS
+ GENERIC (
+ g_seed1 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := c_fft_switch_seed1;
+ g_seed2 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := c_fft_switch_seed2
+ );
PORT (
in_en : IN STD_LOGIC;
out_bit1 : OUT STD_LOGIC;
@@ -43,23 +51,23 @@ ARCHITECTURE rtl OF fft_lfsr IS
-- x^41 + x^20 + 1 and x^41 + x^3 + 1
-- see XAPP217
- CONSTANT c_max : NATURAL := 41;
+ CONSTANT c_len : NATURAL := c_fft_lfsr_len; -- = 41, same for both trinomials
CONSTANT c1 : NATURAL := 20;
CONSTANT c2 : NATURAL := 3;
- SIGNAL s1 : STD_LOGIC_VECTOR(c_max-1 DOWNTO 0);
- SIGNAL nxt_s1 : STD_LOGIC_VECTOR(c_max-1 DOWNTO 0);
-
- SIGNAL s2 : STD_LOGIC_VECTOR(c_max-1 DOWNTO 0);
- SIGNAL nxt_s2 : STD_LOGIC_VECTOR(c_max-1 DOWNTO 0);
-
+ SIGNAL s1 : STD_LOGIC_VECTOR(c_len-1 DOWNTO 0);
+ SIGNAL nxt_s1 : STD_LOGIC_VECTOR(c_len-1 DOWNTO 0);
+ SIGNAL s2 : STD_LOGIC_VECTOR(c_len-1 DOWNTO 0);
+ SIGNAL nxt_s2 : STD_LOGIC_VECTOR(c_len-1 DOWNTO 0);
+
BEGIN
+
p_reg : PROCESS(rst,clk)
BEGIN
IF rst='1' THEN
- s1 <= "01000101011101110101001011111000101100001";
- s2 <= "11011001000101001011011001110101100101100";
+ s1 <= g_seed1;
+ s2 <= g_seed2;
ELSIF rising_edge(clk) THEN
s1 <= nxt_s1;
s2 <= nxt_s2;
@@ -69,22 +77,22 @@ BEGIN
out_bit1 <= s1(s1'HIGH);
out_bit2 <= s2(s2'HIGH);
- p_seed : PROCESS(in_en,s1,s2)
+ p_seed : PROCESS(in_en, s1, s2)
BEGIN
nxt_s1 <= s1;
nxt_s2 <= s2;
- IF in_en='1' THEN
+ IF in_en = '1' THEN
-- shift
- nxt_s1(c_max-1 DOWNTO 1) <= s1(c_max-2 DOWNTO 0);
- nxt_s2(c_max-1 DOWNTO 1) <= s2(c_max-2 DOWNTO 0);
+ nxt_s1(c_len-1 DOWNTO 1) <= s1(c_len-2 DOWNTO 0);
+ nxt_s2(c_len-1 DOWNTO 1) <= s2(c_len-2 DOWNTO 0);
-- feedback 1
- nxt_s1(0) <= s1(c_max-1);
- nxt_s2(0) <= s2(c_max-1);
+ nxt_s1(0) <= s1(c_len-1);
+ nxt_s2(0) <= s2(c_len-1);
-- feedback 2
- nxt_s1(c1) <= s1(c_max-1) xor s1(c1-1);
- nxt_s2(c2) <= s2(c_max-1) xor s2(c2-1);
+ nxt_s1(c1) <= s1(c_len-1) xor s1(c1-1);
+ nxt_s2(c2) <= s2(c_len-1) xor s2(c2-1);
END IF;
END PROCESS;
diff --git a/libraries/dsp/fft/src/vhdl/fft_pkg.vhd b/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
index 4b4a00f80ba00c619efabaf1b8c5be9995588636..05eaa1ffb226920d9127c5d69ea56bdd2ecacefe 100644
--- a/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
@@ -25,6 +25,13 @@ use common_lib.common_pkg.all;
package fft_pkg is
+ -- Default FFT switch and unswitch seeds from LOFAR1
+ constant c_fft_lfsr_len : natural := 41;
+ constant c_fft_switch_seed1 : std_logic_vector(c_fft_lfsr_len-1 DOWNTO 0) := "01000101011101110101001011111000101100001";
+ constant c_fft_switch_seed2 : std_logic_vector(c_fft_lfsr_len-1 DOWNTO 0) := "11011001000101001011011001110101100101100";
+
+ function fft_switch_new_seed(seed : std_logic_vector; offset : natural) return std_logic_vector;
+
-- FFT parameters for pipelined FFT (fft_pipe), parallel FFT (fft_par) and wideband FFT (fft_wide)
type t_fft is record
use_reorder : boolean; -- = false for bit-reversed output, true for normal output
@@ -68,6 +75,11 @@ end package fft_pkg;
package body fft_pkg is
+ function fft_switch_new_seed(seed : std_logic_vector; offset : natural) return std_logic_vector is
+ begin
+ return INCR_UVEC(seed, offset); -- make new unique seed
+ end;
+
function fft_r2_parameter_asserts(g_fft : t_fft) return boolean is
begin
-- nof_points
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
index c9ed7f72c558ac588935c3670265363a810f4b5f..00c2007bd8a4bb7bafb6ca126bf1a11b5f602755 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
@@ -66,6 +66,7 @@ use work.fft_pkg.all;
entity fft_r2_pipe is
generic (
+ g_instance_index : natural := 0; -- used for FFT switch seed
g_fft : t_fft := c_fft; -- generics for the FFT
g_pipeline : t_fft_pipeline := c_fft_pipeline; -- generics for pipelining in each stage, defined in rTwoSDF_lib.rTwoSDFPkg
g_dont_flip_channels : boolean := false; -- generic to prevent re-ordering of the channels
@@ -92,6 +93,8 @@ architecture str of fft_r2_pipe is
constant c_switch_sz_w : natural := ceil_log2(g_fft.nof_points) + g_fft.nof_chan;
constant c_switch_dat_w : natural := g_fft.in_dat_w + 1; -- add 1 extra bit to fit negation of most negative value per real input switch function
constant c_unswitch_dat_w : natural := g_fft.out_dat_w; -- no need for extra bit, because most negative value cannot occur in output
+ constant c_switch_seed1 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := fft_switch_new_seed(c_fft_switch_seed1, g_instance_index);
+ constant c_switch_seed2 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := fft_switch_new_seed(c_fft_switch_seed2, g_instance_index);
constant c_nof_stages : natural := ceil_log2(g_fft.nof_points);
constant c_stage_offset : natural := true_log2(g_fft.wb_factor); -- Stage offset is required for twiddle generation in wideband fft
constant c_in_scale_w : natural := g_fft.stage_dat_w - g_fft.in_dat_w - sel_a_b(g_fft.guard_enable, g_fft.guard_w, 0);
@@ -143,6 +146,8 @@ begin
u_switch : ENTITY work.fft_switch
GENERIC MAP (
g_switch_en => c_switch_en,
+ g_seed1 => c_switch_seed1,
+ g_seed2 => c_switch_seed2,
g_fft_sz_w => c_switch_sz_w,
g_dat_w => c_switch_dat_w
)
@@ -303,6 +308,8 @@ begin
u_unswitch : ENTITY work.fft_unswitch
GENERIC MAP (
g_switch_en => c_switch_en,
+ g_seed1 => c_switch_seed1,
+ g_seed2 => c_switch_seed2,
g_fft_sz_w => c_switch_sz_w,
g_dat_w => c_unswitch_dat_w
)
diff --git a/libraries/dsp/fft/src/vhdl/fft_switch.vhd b/libraries/dsp/fft/src/vhdl/fft_switch.vhd
index cad57405ab3b2c03ed84834171fab082b2ed6b51..9da13b566ede8834d55739437b8515417fac3bf5 100644
--- a/libraries/dsp/fft/src/vhdl/fft_switch.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_switch.vhd
@@ -46,10 +46,13 @@
LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
+USE work.fft_pkg.ALL;
ENTITY fft_switch IS
GENERIC (
g_switch_en : BOOLEAN := FALSE;
+ g_seed1 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := c_fft_switch_seed1;
+ g_seed2 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := c_fft_switch_seed2;
g_fft_sz_w : NATURAL;
g_dat_w : NATURAL
);
@@ -156,6 +159,10 @@ BEGIN
END PROCESS;
u_fft_lfsr: ENTITY work.fft_lfsr
+ GENERIC MAP (
+ g_seed1 => g_seed1,
+ g_seed2 => g_seed2
+ )
PORT MAP (
clk => clk,
rst => rst,
diff --git a/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd b/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
index 6d9f561a15e7ca184f70c418810bd85f9b1ac6d6..f94f12e7f0954a3b6af011504a33052e471bef90 100644
--- a/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
@@ -31,10 +31,13 @@
LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
+USE work.fft_pkg.ALL;
ENTITY fft_unswitch IS
GENERIC (
g_switch_en : BOOLEAN := FALSE;
+ g_seed1 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := c_fft_switch_seed1;
+ g_seed2 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := c_fft_switch_seed2;
g_fft_sz_w : NATURAL;
g_dat_w : NATURAL
);
@@ -147,6 +150,10 @@ BEGIN
END PROCESS;
u_fft_lfsr: ENTITY work.fft_lfsr
+ GENERIC MAP (
+ g_seed1 => g_seed1,
+ g_seed2 => g_seed2
+ )
PORT MAP (
clk => clk,
rst => rst,
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..23791ba61bcdf56d68adae81c6b3d1672fb22166
--- /dev/null
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd
@@ -0,0 +1,92 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Verify fft_lsfr for different seeds
+-- Description:
+-- Check that after c_fft_lfsr_len = 41 blocks the LFSR1 and LFSR2 bits of
+-- the two instances u0 and u1 indeed start to differ.
+--
+-- Usage:
+-- > as 4
+-- > run -all
+-- # Not self checking, manually compare that u0_lfsr_bit1 and u1_lfsr_bit1
+-- start to differ after about c_fft_lfsr_len blocks. Similar for
+-- u0_lfsr_bit1 and u1_lfsr_bit1.
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE work.fft_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_fft_lfsr IS
+END tb_fft_lfsr;
+
+ARCHITECTURE tb OF tb_fft_lfsr IS
+
+ CONSTANT clk_period : TIME := 10 ns;
+
+ CONSTANT c_block_period : NATURAL := 10;
+ CONSTANT c_nof_block : NATURAL := 1000;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL rst : STD_LOGIC := '1';
+ SIGNAL clk : STD_LOGIC := '0';
+
+ SIGNAL in_en : STD_LOGIC := '0';
+ SIGNAL u0_lfsr_bit1 : STD_LOGIC;
+ SIGNAL u1_lfsr_bit1 : STD_LOGIC;
+ SIGNAL u0_lfsr_bit2 : STD_LOGIC;
+ SIGNAL u1_lfsr_bit2 : STD_LOGIC;
+
+BEGIN
+
+ clk <= NOT clk OR tb_end AFTER clk_period/2;
+ rst <= '1', '0' AFTER 10 * clk_period;
+ tb_end <= '0', '1' AFTER c_nof_block * c_block_period * clk_period;
+
+ proc_common_gen_pulse(1, c_block_period, '1', rst, clk, in_en);
+
+ u0 : ENTITY work.fft_lfsr
+ GENERIC MAP (
+ g_seed1 => fft_switch_new_seed(c_fft_switch_seed1, 0),
+ g_seed2 => fft_switch_new_seed(c_fft_switch_seed2, 0)
+ )
+ PORT MAP (
+ in_en => in_en,
+ out_bit1 => u0_lfsr_bit1,
+ out_bit2 => u0_lfsr_bit2,
+ clk => clk,
+ rst => rst
+ );
+
+ u1 : ENTITY work.fft_lfsr
+ GENERIC MAP (
+ g_seed1 => fft_switch_new_seed(c_fft_switch_seed1, 1),
+ g_seed2 => fft_switch_new_seed(c_fft_switch_seed2, 1)
+ )
+ PORT MAP (
+ in_en => in_en,
+ out_bit1 => u1_lfsr_bit1,
+ out_bit2 => u1_lfsr_bit2,
+ clk => clk,
+ rst => rst
+ );
+
+END tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
index 08d04ee3e9bae1ffaea762e535be0d38d97395f6..981f017da2af2a9125e6155283168f6e17d83542 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
@@ -52,9 +52,11 @@ LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
+USE work.fft_pkg.ALL;
ENTITY tb_fft_switch IS
GENERIC (
+ g_instance_index : NATURAL := 0;
g_switch_en : BOOLEAN := TRUE;
g_in_val_gaps : BOOLEAN := TRUE;
g_increment_at_val : BOOLEAN := TRUE;
@@ -66,9 +68,9 @@ END tb_fft_switch;
ARCHITECTURE tb OF tb_fft_switch IS
- CONSTANT clk_period : TIME := 10 ns;
+ CONSTANT clk_period : TIME := 10 ns;
- CONSTANT c_dat_w : NATURAL := 16;
+ CONSTANT c_dat_w : NATURAL := 16;
CONSTANT c_nof_clk_per_block : NATURAL := 2**g_fft_size_w;
CONSTANT c_nof_block_per_sync_max : NATURAL := ceil_div(g_nof_clk_per_sync, c_nof_clk_per_block);
@@ -76,6 +78,9 @@ ARCHITECTURE tb OF tb_fft_switch IS
CONSTANT c_dly : NATURAL := 4; -- pipeling in fft_switch, mux, fft_unswitch and demux
+ constant c_switch_seed1 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := fft_switch_new_seed(c_fft_switch_seed1, g_instance_index);
+ constant c_switch_seed2 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := fft_switch_new_seed(c_fft_switch_seed2, g_instance_index);
+
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL rst : STD_LOGIC := '1';
SIGNAL clk : STD_LOGIC := '0';
@@ -185,6 +190,8 @@ BEGIN
u_fft_switch : ENTITY work.fft_switch
GENERIC MAP (
g_switch_en => g_switch_en,
+ g_seed1 => c_switch_seed1,
+ g_seed2 => c_switch_seed2,
g_fft_sz_w => g_fft_size_w,
g_dat_w => c_dat_w
)
@@ -227,6 +234,8 @@ BEGIN
u_fft_unswitch : ENTITY work.fft_unswitch
GENERIC MAP (
g_switch_en => g_switch_en,
+ g_seed1 => c_switch_seed1,
+ g_seed2 => c_switch_seed2,
g_fft_sz_w => g_fft_size_w,
g_dat_w => c_dat_w
)
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
index 158f3cb747fb60b86fb13e8ba917f330920df0d1..c12d89665762e8451ba9e6e337e367d3bb72f11f 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
@@ -597,6 +597,7 @@ begin
gen_fft_r2_pipe_streams: for S in 0 to g_wpfb.nof_wb_streams-1 generate
u_fft_r2_pipe : entity fft_lib.fft_r2_pipe
generic map(
+ g_instance_index => S,
g_fft => c_fft,
g_pipeline => g_wpfb.fft_pipeline,
g_dont_flip_channels => g_dont_flip_channels,
diff --git a/libraries/io/eth/src/vhdl/eth_control.vhd b/libraries/io/eth/src/vhdl/eth_control.vhd
index c9f05abf52f6ac95e75079241ce81108207231b5..7efb2fa35a64090f2c818feb9785306d92d3b35d 100644
--- a/libraries/io/eth/src/vhdl/eth_control.vhd
+++ b/libraries/io/eth/src/vhdl/eth_control.vhd
@@ -187,6 +187,8 @@ BEGIN
nxt_hdr_response_arr <= func_network_total_header_response_arp( rcv_hdr_words_arr, reg_config.mac_address, reg_config.ip_address);
ELSIF rcv_hdr_status.is_icmp='1' THEN
nxt_hdr_response_arr <= func_network_total_header_response_icmp(rcv_hdr_words_arr, reg_config.mac_address);
+ -- Calculate icmp checksum = original checksum + 0x0800.
+ nxt_hdr_response_arr(9)(c_halfword_w-1 DOWNTO 0) <= TO_UVEC( 2048 + TO_UINT(rcv_hdr_words_arr(9)(c_halfword_w-1 DOWNTO 0)), c_halfword_w);
ELSIF rcv_hdr_status.is_udp='1' THEN
nxt_hdr_response_arr <= func_network_total_header_response_udp( rcv_hdr_words_arr, reg_config.mac_address);
ELSIF rcv_hdr_status.is_ip='1' THEN
diff --git a/libraries/io/eth/tb/vhdl/tb_eth.vhd b/libraries/io/eth/tb/vhdl/tb_eth.vhd
index 22387c22d9d90beb359e0e2513ef85bd8ef065a2..8274212a952de0465c56fedb596507b4b2148018 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth.vhd
@@ -181,9 +181,13 @@ ARCHITECTURE tb OF tb_eth IS
checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
+
+ -- checksum is 0x0800 + original checksum
+ CONSTANT c_exp_icmp_checksum : STD_LOGIC_VECTOR(c_network_icmp_checksum_w-1 DOWNTO 0) := TO_UVEC( 2048 + TO_UINT(c_tx_icmp_header.checksum), c_network_icmp_checksum_w);
+
CONSTANT c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
code => c_tx_icmp_header.code,
- checksum => c_tx_icmp_header.checksum, -- init value
+ checksum => c_exp_icmp_checksum,
id => c_tx_icmp_header.id,
sequence => c_tx_icmp_header.sequence);
diff --git a/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd b/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
index 956e61a07e4262b35df42a61d4f4eda7dc69a995..ad31f6993c05a73b70d8178512ce05d7e6468c2d 100644
--- a/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
+++ b/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
@@ -181,9 +181,13 @@ ARCHITECTURE tb OF tb_eth1g IS
checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
+
+ -- checksum is 0x0800 + original checksum
+ CONSTANT c_exp_icmp_checksum : STD_LOGIC_VECTOR(c_network_icmp_checksum_w-1 DOWNTO 0) := TO_UVEC( 2048 + TO_UINT(c_tx_icmp_header.checksum), c_network_icmp_checksum_w);
+
CONSTANT c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
code => c_tx_icmp_header.code,
- checksum => c_tx_icmp_header.checksum, -- init value
+ checksum => c_exp_icmp_checksum,
id => c_tx_icmp_header.id,
sequence => c_tx_icmp_header.sequence);