From 508c138ab901faac447e1d1f59990f1bb0cff060 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Sun, 18 Oct 2015 12:24:59 +0000
Subject: [PATCH] Added and pass on g_technology.
---
.../base/common/src/vhdl/common_blockreg.vhd | 13 ++++++++-----
.../src/vhdl/common_paged_ram_crw_crw.vhd | 19 ++++++++++++-------
.../common/src/vhdl/common_paged_ram_r_w.vhd | 15 +++++++++------
.../src/vhdl/common_paged_ram_rw_rw.vhd | 15 +++++++++------
.../common/src/vhdl/common_paged_ram_w_rr.vhd | 11 +++++++----
.../src/vhdl/common_paged_ram_ww_rr.vhd | 15 +++++++++------
.../base/common/src/vhdl/common_shiftram.vhd | 9 ++++++---
libraries/base/dp/src/vhdl/dp_distribute.vhd | 16 +++++++++-------
libraries/base/dp/src/vhdl/dp_fifo_core.vhd | 16 ++++++++++------
libraries/base/dp/src/vhdl/dp_fifo_dc.vhd | 5 ++++-
.../dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd | 18 +++++++++++-------
libraries/base/dp/src/vhdl/dp_fifo_fill.vhd | 16 +++++++++-------
.../base/dp/src/vhdl/dp_fifo_fill_core.vhd | 6 +++++-
.../base/dp/src/vhdl/dp_fifo_fill_dc.vhd | 5 ++++-
.../base/dp/src/vhdl/dp_fifo_fill_sc.vhd | 5 ++++-
libraries/base/dp/src/vhdl/dp_fifo_info.vhd | 16 ++++++++++------
libraries/base/dp/src/vhdl/dp_fifo_sc.vhd | 5 ++++-
.../base/dp/src/vhdl/dp_frame_scheduler.vhd | 16 +++++++++-------
libraries/base/dp/src/vhdl/dp_mux.vhd | 16 +++++++++-------
libraries/base/dp/src/vhdl/dp_offload_tx.vhd | 5 ++++-
libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd | 5 ++++-
libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd | 5 ++++-
libraries/base/dp/src/vhdl/dp_shiftram.vhd | 5 ++++-
23 files changed, 164 insertions(+), 93 deletions(-)
diff --git a/libraries/base/common/src/vhdl/common_blockreg.vhd b/libraries/base/common/src/vhdl/common_blockreg.vhd
index 919b24a16b..234a418e83 100755
--- a/libraries/base/common/src/vhdl/common_blockreg.vhd
+++ b/libraries/base/common/src/vhdl/common_blockreg.vhd
@@ -19,11 +19,6 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE work.common_pkg.ALL;
-
-- Purpose:
-- . 'Shift register' that shifts on block boundary instead of single
-- word boundary: If the register is full, it shifts out an entire
@@ -41,8 +36,15 @@ USE work.common_pkg.ALL;
-- . the '+1' is caused by 'nxt_' register latency; always there (not
-- valid-dependent like the rest).
+LIBRARY IEEE, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE work.common_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY common_blockreg IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_block_size : NATURAL;
g_dat_w : NATURAL
);
@@ -83,6 +85,7 @@ BEGIN
u_fifo : ENTITY work.common_fifo_sc
GENERIC MAP (
+ g_technology => g_technology,
g_note_is_ful => FALSE,
g_dat_w => g_dat_w,
g_nof_words => g_block_size+1
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
index 7f6d6e5220..6139a16582 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
@@ -19,13 +19,6 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-LIBRARY common_lib;
-USE work.common_pkg.ALL;
-USE work.common_mem_pkg.ALL;
-
-- Purpose: Multi page memory
-- Description:
-- When next_page_* pulses then the next access will occur in the next page.
@@ -41,8 +34,17 @@ USE work.common_mem_pkg.ALL;
-- pages are then mapped at subsequent addresses in the buf RAM.
-- . The "use_adr" variant is optimal for speed, so that is set as default.
+LIBRARY IEEE, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+LIBRARY common_lib;
+USE work.common_pkg.ALL;
+USE work.common_mem_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY common_paged_ram_crw_crw IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_str : STRING := "use_adr";
g_data_w : NATURAL;
g_nof_pages : NATURAL := 2; -- >= 2
@@ -226,6 +228,7 @@ BEGIN
gen_pages : FOR I IN 0 TO g_nof_pages-1 GENERATE
u_ram : ENTITY work.common_ram_crw_crw
GENERIC MAP (
+ g_technology => g_technology,
g_ram => c_page_ram,
g_init_file => "UNUSED",
g_true_dual_port => g_true_dual_port
@@ -276,6 +279,7 @@ BEGIN
gen_adr : IF g_str = "use_adr" GENERATE
u_mem : ENTITY work.common_ram_crw_crw
GENERIC MAP (
+ g_technology => g_technology,
g_ram => c_mem_ram,
g_init_file => "UNUSED",
g_true_dual_port => g_true_dual_port
@@ -309,6 +313,7 @@ BEGIN
gen_ofs : IF g_str = "use_ofs" GENERATE
u_buf : ENTITY work.common_ram_crw_crw
GENERIC MAP (
+ g_technology => g_technology,
g_ram => c_buf_ram,
g_init_file => "UNUSED",
g_true_dual_port => g_true_dual_port
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd b/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
index aee99711d4..a5dcdec09d 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
@@ -19,20 +19,22 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-LIBRARY common_lib;
-USE work.common_pkg.ALL;
-
-- Purpose: Multi page memory
-- Description:
-- When next_page_* pulses then the next access will occur in the next page.
-- Remarks:
-- . See common_paged_ram_crw_crw for details.
+LIBRARY IEEE, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+LIBRARY common_lib;
+USE work.common_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY common_paged_ram_r_w IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_str : STRING := "use_adr";
g_data_w : NATURAL;
g_nof_pages : NATURAL := 2; -- >= 2
@@ -64,6 +66,7 @@ BEGIN
u_rw_rw : ENTITY work.common_paged_ram_rw_rw
GENERIC MAP (
+ g_technology => g_technology,
g_str => g_str,
g_data_w => g_data_w,
g_nof_pages => g_nof_pages,
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
index f9dc9b233c..d7a41264d8 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
@@ -19,20 +19,22 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-LIBRARY common_lib;
-USE work.common_pkg.ALL;
-
-- Purpose: Multi page memory
-- Description:
-- When next_page_* pulses then the next access will occur in the next page.
-- Remarks:
-- . See common_paged_ram_crw_crw for details.
+LIBRARY IEEE, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+LIBRARY common_lib;
+USE work.common_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY common_paged_ram_rw_rw IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_str : STRING := "use_adr";
g_data_w : NATURAL;
g_nof_pages : NATURAL := 2; -- >= 2
@@ -70,6 +72,7 @@ BEGIN
u_crw_crw : ENTITY work.common_paged_ram_crw_crw
GENERIC MAP (
+ g_technology => g_technology,
g_str => g_str,
g_data_w => g_data_w,
g_nof_pages => g_nof_pages,
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd b/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
index fb27ac5e45..15c1250322 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
@@ -19,18 +19,20 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE work.common_pkg.ALL;
-
-- Purpose: Dual page memory with single wr in one page and dual rd in other page
-- Description:
-- When next_page pulses then the next access will occur in the other page.
-- Remarks:
-- Each page uses one or more RAM blocks.
+LIBRARY IEEE, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE work.common_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY common_paged_ram_w_rr IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_pipeline_in : NATURAL := 0; -- >= 0
g_pipeline_out : NATURAL := 0; -- >= 0
g_data_w : NATURAL;
@@ -67,6 +69,7 @@ BEGIN
u_ww_rr : ENTITY work.common_paged_ram_ww_rr
GENERIC MAP (
+ g_technology => g_technology,
g_pipeline_in => g_pipeline_in,
g_pipeline_out => g_pipeline_out,
g_data_w => g_data_w,
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd b/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
index 85bcaf4810..3256afa9d1 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
@@ -19,20 +19,22 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE work.common_pkg.ALL;
-USE work.common_mem_pkg.ALL;
-USE work.common_components_pkg.ALL;
-
-- Purpose: Dual page memory with dual wr in one page and dual rd in other page
-- Description:
-- When next_page pulses then the next access will occur in the other page.
-- Remarks:
-- Each page uses one or more RAM blocks.
+LIBRARY IEEE, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE work.common_pkg.ALL;
+USE work.common_mem_pkg.ALL;
+USE work.common_components_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY common_paged_ram_ww_rr IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_pipeline_in : NATURAL := 0; -- >= 0
g_pipeline_out : NATURAL := 0; -- >= 0
g_data_w : NATURAL;
@@ -180,6 +182,7 @@ BEGIN
u_page : ENTITY work.common_ram_rw_rw
GENERIC MAP (
+ g_technology => g_technology,
g_ram => c_page_ram,
g_init_file => "UNUSED"
)
diff --git a/libraries/base/common/src/vhdl/common_shiftram.vhd b/libraries/base/common/src/vhdl/common_shiftram.vhd
index 7b01723b7b..fba9bf09c8 100644
--- a/libraries/base/common/src/vhdl/common_shiftram.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftram.vhd
@@ -49,16 +49,18 @@
-- R = RAM I/O
-- r0..r2 = register stages.
-LIBRARY IEEE,common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY common_shiftram IS
GENERIC (
- g_data_w : NATURAL;
- g_nof_words : NATURAL; -- Depth of RAM. Must be a power of two.
+ g_technology : NATURAL := c_tech_select_default;
+ g_data_w : NATURAL;
+ g_nof_words : NATURAL; -- Depth of RAM. Must be a power of two.
g_output_invalid_during_shift_incr : BOOLEAN := FALSE;
g_fixed_shift : BOOLEAN := FALSE -- If data_in_shift is constant, set to TRUE
); -- for better timing results
@@ -261,6 +263,7 @@ BEGIN
-----------------------------------------------------------------------------
u_common_ram_r_w: ENTITY common_lib.common_ram_r_w
GENERIC MAP (
+ g_technology => g_technology,
g_ram => c_ram,
g_init_file => "UNUSED",
g_true_dual_port => FALSE
diff --git a/libraries/base/dp/src/vhdl/dp_distribute.vhd b/libraries/base/dp/src/vhdl/dp_distribute.vhd
index 079fa0faf6..f703d0954b 100644
--- a/libraries/base/dp/src/vhdl/dp_distribute.vhd
+++ b/libraries/base/dp/src/vhdl/dp_distribute.vhd
@@ -19,13 +19,6 @@
--
--------------------------------------------------------------------------------
-LIBRARY IEEE,common_lib;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE work.dp_stream_pkg.ALL;
-
-
-- Purpose: Distribute the frames from n input streams on to m output streams.
-- Description:
-- * First the n input streams are demultiplexed in n*m internal streams and
@@ -82,8 +75,16 @@ USE work.dp_stream_pkg.ALL;
-- . Thanks to the non-blocking dp_mux the distribution continuous when a frame
-- gets lost or an input is not used.
+LIBRARY IEEE,common_lib, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY dp_distribute IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
-- Distribution IO
g_tx : BOOLEAN;
g_nof_input : NATURAL := 4; -- >= 1
@@ -161,6 +162,7 @@ BEGIN
gen_input : FOR I IN 0 TO g_nof_input-1 GENERATE
u_fifo : ENTITY work.dp_fifo_fill
GENERIC MAP (
+ g_technology => g_technology,
g_bsn_w => g_bsn_w,
g_data_w => g_data_w,
g_empty_w => g_empty_w,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
index 308bf9f634..aaebaa7fe6 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
@@ -19,12 +19,6 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE work.dp_stream_pkg.ALL;
-
-- Purpose:
-- Provide input ready control and use output ready control to the FIFO.
-- Pass sop and eop along with the data through the FIFO if g_use_ctrl=TRUE.
@@ -45,8 +39,16 @@ USE work.dp_stream_pkg.ALL;
-- combinatorially connected, so this can ease the timing closure for the
-- ready signal.
+LIBRARY IEEE, common_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY dp_fifo_core IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_use_dual_clock : BOOLEAN := FALSE;
g_use_lut_sc : BOOLEAN := FALSE; -- when TRUE then force using LUTs instead of block RAM for single clock FIFO (bot available for dual clock FIFO)
g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
@@ -168,6 +170,7 @@ BEGIN
gen_common_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
u_common_fifo_sc : ENTITY common_lib.common_fifo_sc
GENERIC MAP (
+ g_technology => g_technology,
g_use_lut => g_use_lut_sc,
g_dat_w => c_fifo_dat_w,
g_nof_words => g_fifo_size
@@ -191,6 +194,7 @@ BEGIN
gen_common_fifo_dc : IF g_use_dual_clock=TRUE GENERATE
u_common_fifo_dc : ENTITY common_lib.common_fifo_dc
GENERIC MAP (
+ g_technology => g_technology,
g_dat_w => c_fifo_dat_w,
g_nof_words => g_fifo_size
)
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
index 83ca7d820a..c421daa4c7 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
@@ -22,14 +22,16 @@
-- Purpose: DP FIFO for dual clock (= dc) domain wr and rd.
-- Description: See dp_fifo_core.vhd.
-LIBRARY IEEE,common_lib;
+LIBRARY IEEE,common_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY dp_fifo_dc IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
g_bsn_w : NATURAL := 1;
g_empty_w : NATURAL := 1;
@@ -71,6 +73,7 @@ BEGIN
u_dp_fifo_core : ENTITY work.dp_fifo_core
GENERIC MAP (
+ g_technology => g_technology,
g_use_dual_clock => TRUE,
g_data_w => g_data_w,
g_bsn_w => g_bsn_w,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
index 5e39f97f71..5b80900353 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
@@ -18,13 +18,7 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-
-LIBRARY IEEE, common_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE work.dp_stream_pkg.ALL;
-
+--
-- Purpose:
-- Provide input ready control and use output ready control to the mixed
-- width FIFO.
@@ -106,8 +100,16 @@ USE work.dp_stream_pkg.ALL;
-- 4 Simulate with multi tb-tb test bench for regression tests
-- . add this multi tb-tb test bench to tb_tb_tb_dp_backpressure.vhd
+LIBRARY IEEE, common_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY dp_fifo_dc_mixed_widths IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_wr_data_w : NATURAL := 18;
g_rd_data_w : NATURAL := 9;
g_use_ctrl : BOOLEAN := TRUE;
@@ -198,6 +200,7 @@ BEGIN
gen_equal : IF c_nof_narrow = 1 GENERATE -- fall back to equal width FIFO
u_dp_fifo_dc : ENTITY work.dp_fifo_dc
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_wr_data_w,
g_empty_w => 1,
g_channel_w => 1,
@@ -263,6 +266,7 @@ BEGIN
u_fifo_mw : ENTITY common_lib.common_fifo_dc_mixed_widths
GENERIC MAP (
+ g_technology => g_technology,
g_nof_words => g_wr_fifo_size, -- FIFO size in nof wr_dat words
g_wr_dat_w => c_fifo_wr_dat_w,
g_rd_dat_w => c_fifo_rd_dat_w
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
index 0df58b0a47..d69e8d3e97 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
@@ -21,13 +21,6 @@
-- Reuse from LOFAR rad_frame_scheduler.vhd and rad_frame_scheduler(rtl).vhd
-LIBRARY IEEE,common_lib;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE work.dp_stream_pkg.ALL;
-
-
-- Purpose:
-- The FIFO starts outputting data when the output is ready and it has been
-- filled with more than g_fifo_fill words. Given a fixed frame length, this
@@ -62,8 +55,16 @@ USE work.dp_stream_pkg.ALL;
-- invalid cycle at the output which means you cannot feed 100% valid data
-- to this FIFO; a minimum of one dead cycle inbetween packets is required.
+LIBRARY IEEE, common_lib, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY dp_fifo_fill IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_data_w : NATURAL := 16;
g_bsn_w : NATURAL := 1;
g_empty_w : NATURAL := 1;
@@ -135,6 +136,7 @@ BEGIN
dp_fifo_sc : ENTITY work.dp_fifo_sc
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_data_w,
g_bsn_w => g_bsn_w,
g_empty_w => g_empty_w,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
index d1454b79e9..1026b7c03b 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
@@ -51,14 +51,16 @@
-- src_in.ready is often more clear to comprehend then using next_src_out
-- directly.
-LIBRARY IEEE,common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY dp_fifo_fill_core IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_use_dual_clock : BOOLEAN := FALSE;
g_data_w : NATURAL := 16;
g_bsn_w : NATURAL := 1;
@@ -141,6 +143,7 @@ BEGIN
gen_dp_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
u_dp_fifo_sc : ENTITY work.dp_fifo_sc
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_data_w,
g_bsn_w => g_bsn_w,
g_empty_w => g_empty_w,
@@ -178,6 +181,7 @@ BEGIN
gen_dp_fifo_dc : IF g_use_dual_clock=TRUE GENERATE
u_dp_fifo_dc : ENTITY work.dp_fifo_dc
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_data_w,
g_bsn_w => g_bsn_w,
g_empty_w => g_empty_w,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
index b16f3ba2f0..95e5e8568a 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
@@ -23,14 +23,16 @@
-- been filled with more than g_fifo_fill words.
-- Description: See dp_fifo_fill_core.vhd.
-LIBRARY IEEE,common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY dp_fifo_fill_dc IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_data_w : NATURAL := 16;
g_bsn_w : NATURAL := 1;
g_empty_w : NATURAL := 1;
@@ -72,6 +74,7 @@ BEGIN
u_dp_fifo_fill_core : ENTITY work.dp_fifo_fill_core
GENERIC MAP (
+ g_technology => g_technology,
g_use_dual_clock => TRUE,
g_data_w => g_data_w,
g_bsn_w => g_bsn_w,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
index 8ea990468d..dc6fb88f5a 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
@@ -23,14 +23,16 @@
-- been filled with more than g_fifo_fill words.
-- Description: See dp_fifo_fill_core.vhd.
-LIBRARY IEEE,common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY dp_fifo_fill_sc IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_data_w : NATURAL := 16;
g_bsn_w : NATURAL := 1;
g_empty_w : NATURAL := 1;
@@ -71,6 +73,7 @@ BEGIN
u_dp_fifo_fill_core : ENTITY work.dp_fifo_fill_core
GENERIC MAP (
+ g_technology => g_technology,
g_use_dual_clock => FALSE,
g_data_w => g_data_w,
g_bsn_w => g_bsn_w,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_info.vhd b/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
index e7fc9935b3..45d3c99b5b 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
@@ -19,12 +19,6 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE work.dp_stream_pkg.ALL;
-
-- Purpose:
-- Realign the snk_in info with the snk_in data that got delayed
-- Description:
@@ -58,8 +52,16 @@ USE work.dp_stream_pkg.ALL;
-- . The dp_fifo_info preserves the RL=1 but is does delay the data by one
-- cycle.
+LIBRARY IEEE, common_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY dp_fifo_info IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_use_sync : BOOLEAN := FALSE;
g_use_bsn : BOOLEAN := FALSE;
g_use_channel : BOOLEAN := FALSE;
@@ -166,6 +168,7 @@ BEGIN
u_common_fifo_sc : ENTITY common_lib.common_fifo_sc
GENERIC MAP (
+ g_technology => g_technology,
g_note_is_ful => FALSE, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_use_lut => TRUE, -- when TRUE then force using LUTs via Altera eab="OFF",
g_dat_w => c_fifo_sop_dat_w,
@@ -203,6 +206,7 @@ BEGIN
u_common_fifo_sc : ENTITY common_lib.common_fifo_sc
GENERIC MAP (
+ g_technology => g_technology,
g_note_is_ful => FALSE, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_use_lut => TRUE, -- when TRUE then force using LUTs via Altera eab="OFF",
g_dat_w => c_fifo_eop_dat_w,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
index 6568ed5a7c..caf411938d 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
@@ -22,14 +22,16 @@
-- Purpose: DP FIFO for single clock (= sc) domain wr and rd.
-- Description: See dp_fifo_core.vhd.
-LIBRARY IEEE,common_lib;
+LIBRARY IEEE,common_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY dp_fifo_sc IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_use_lut : BOOLEAN := FALSE; -- when TRUE then force using LUTs instead of block RAM
g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
g_bsn_w : NATURAL := 1;
@@ -69,6 +71,7 @@ BEGIN
u_dp_fifo_core : ENTITY work.dp_fifo_core
GENERIC MAP (
+ g_technology => g_technology,
g_use_dual_clock => FALSE,
g_use_lut_sc => g_use_lut,
g_data_w => g_data_w,
diff --git a/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
index 354a76e40a..11b2ef47f6 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
@@ -21,13 +21,6 @@
-- Reuse from LOFAR rad_frame_scheduler.vhd and rad_frame_scheduler(rtl).vhd
-LIBRARY IEEE,common_lib;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE work.dp_stream_pkg.ALL;
-
-
-- Purpose:
-- Schedule one or more input frames streams into one output stream.
-- Description:
@@ -47,8 +40,16 @@ USE work.dp_stream_pkg.ALL;
-- dp_xonoff ensures that in_dis is applied during entire frames and before
-- they are written into the input FIFO.
+LIBRARY IEEE,common_lib, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY dp_frame_scheduler IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_dat_w : NATURAL := 16;
g_nof_input : NATURAL := 2; -- >= 1
g_fifo_rl : NATURAL := 1; -- for all input use 0 for look ahead FIFO, 1 for normal FIFO
@@ -181,6 +182,7 @@ BEGIN
u_fill : ENTITY work.dp_fifo_fill
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_dat_w,
g_empty_w => 1,
g_channel_w => 1,
diff --git a/libraries/base/dp/src/vhdl/dp_mux.vhd b/libraries/base/dp/src/vhdl/dp_mux.vhd
index 2f397cfb8d..34ece06dc5 100644
--- a/libraries/base/dp/src/vhdl/dp_mux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mux.vhd
@@ -19,13 +19,6 @@
--
--------------------------------------------------------------------------------
-LIBRARY IEEE,common_lib;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE work.dp_stream_pkg.ALL;
-
-
-- Purpose:
-- Multiplex frames from one or more input streams into one output stream.
-- Description:
@@ -85,8 +78,16 @@ USE work.dp_stream_pkg.ALL;
-- . For multiplexing time series frames or sample it can be applicable to
-- use g_append_channel_lo=FALSE in combination with g_mode=2.
+LIBRARY IEEE,common_lib, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY dp_mux IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
-- MUX
g_mode : NATURAL := 0;
g_nof_input : NATURAL := 2; -- >= 1
@@ -214,6 +215,7 @@ BEGIN
gen_fifo : IF g_use_fifo=TRUE GENERATE
u_fill : ENTITY work.dp_fifo_fill
GENERIC MAP (
+ g_technology => g_technology,
g_bsn_w => g_bsn_w,
g_data_w => g_data_w,
g_empty_w => g_empty_w,
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
index 29aec41853..c30227eaec 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
@@ -35,16 +35,18 @@
-- overflow upstream. dp_plit should not do that, or better, something simpler such as dp_tail_remove
-- should be used instead.
-LIBRARY IEEE, common_lib, work, mm_lib;
+LIBRARY IEEE, common_lib, technology_lib, mm_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE work.dp_stream_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY dp_offload_tx IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_nof_streams : NATURAL;
g_data_w : NATURAL;
g_use_complex : BOOLEAN; -- TRUE uses re(0..g_data_w/2 -1) & im(0..g_data_w/2-1) as input instead of data(0..g_data_w-1).
@@ -254,6 +256,7 @@ BEGIN
gen_dp_fifo_fill : FOR i IN 0 TO sel_a_b(g_use_post_split_fifo, g_nof_streams, 0)-1 GENERATE
u_dp_fifo_fill : ENTITY work.dp_fifo_fill
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_data_w,
g_fifo_fill => c_dp_fifo_fill,
g_fifo_size => c_dp_fifo_size
diff --git a/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
index 28525d8e9f..9430dc0903 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
@@ -19,15 +19,17 @@
--
--------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY dp_ram_from_mm IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_ram_wr_nof_words : NATURAL;
g_ram_rd_dat_w : NATURAL;
g_init_file : STRING := "UNUSED"
@@ -154,6 +156,7 @@ BEGIN
u_ram : ENTITY common_lib.common_ram_cr_cw_ratio
GENERIC MAP (
+ g_technology => g_technology,
g_ram_wr => c_mm_ram_wr,
g_ram_rd => c_mm_ram_rd,
g_init_file => g_init_file
diff --git a/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
index 04b4176472..a6aa70d926 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
@@ -19,15 +19,17 @@
--
--------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY dp_ram_to_mm IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_ram_rd_nof_words : NATURAL;
g_ram_wr_dat_w : NATURAL
);
@@ -132,6 +134,7 @@ BEGIN
u_ram : ENTITY common_lib.common_ram_cr_cw_ratio
GENERIC MAP (
+ g_technology => g_technology,
g_ram_wr => c_mm_ram_wr,
g_ram_rd => c_mm_ram_rd,
g_init_file => "UNUSED"
diff --git a/libraries/base/dp/src/vhdl/dp_shiftram.vhd b/libraries/base/dp/src/vhdl/dp_shiftram.vhd
index 1e88fabcfd..a7119e6d3d 100644
--- a/libraries/base/dp/src/vhdl/dp_shiftram.vhd
+++ b/libraries/base/dp/src/vhdl/dp_shiftram.vhd
@@ -22,16 +22,18 @@
-- Purpose:
-- Description:
-LIBRARY IEEE,common_lib, mm_lib;
+LIBRARY IEEE, common_lib, technology_lib, mm_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY dp_shiftram IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_nof_streams : NATURAL;
g_nof_words : NATURAL;
g_data_w : NATURAL
@@ -76,6 +78,7 @@ BEGIN
gen_common_shiftram : FOR i IN 0 TO g_nof_streams-1 GENERATE
u_common_shiftram : ENTITY common_lib.common_shiftram
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_data_w,
g_nof_words => g_nof_words
)
--
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