diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
index c854fbb25961c387d6ba0ccfda5a233dab1bd38c..b45b48b74132a6b57e3dd8ea406b5e1f1c03d8be 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = lofar2_unb2b_adc
hdl_library_clause_name = lofar2_unb2b_adc_lib
-hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tr_10GbE diagnostics diag aduh tech_jesd204b
+hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tr_10GbE diagnostics diag aduh tech_jesd204b lofar2_sdp
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..f2e2c0667939a5a81e493dc9aaef0509a40bba71
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml
@@ -0,0 +1,137 @@
+schema_name : args
+schema_version: 1.0
+schema_type : fpga
+
+hdl_library_name: lofar2_unb2b_adc
+fpga_name : lofar2_unb2b_adc
+fpga_description: "FPGA design lofar2_unb2b_adc"
+
+peripherals:
+ #############################################################################
+ # Factory / minimal (from ctrl_unb2b_board.vhd)
+ #############################################################################
+ - peripheral_name: unb2b_board/system_info
+ mm_port_names:
+ - ROM_SYSTEM_INFO
+ - PIO_SYSTEM_INFO
+ lock_base_address: 0x10000
+
+ - peripheral_name: unb2b_board/wdi
+ mm_port_names:
+ - PIO_WDI
+
+ - peripheral_name: unb2b_board/unb2_fpga_sens
+ mm_port_names:
+ - REG_FPGA_TEMP_SENS
+ - REG_FPGA_VOLTAGE_SENS
+
+ - peripheral_name: unb2b_board/ram_scrap
+ mm_port_names:
+ - RAM_SCRAP
+
+ - peripheral_name: eth/eth
+ mm_port_names:
+ - AVS_ETH_0_TSE
+ - AVS_ETH_0_REG
+ - AVS_ETH_0_RAM
+
+ - peripheral_name: ppsh/ppsh
+ mm_port_names:
+ - PIO_PPS
+
+ - peripheral_name: epcs/epcs
+ mm_port_names:
+ - REG_EPCS
+
+ - peripheral_name: dp/dpmm
+ mm_port_names:
+ - REG_DPMM_CTRL
+ - REG_DPMM_DATA
+
+ - peripheral_name: dp/mmdp
+ mm_port_names:
+ - REG_MMDP_CTRL
+ - REG_MMDP_DATA
+
+ - peripheral_name: remu/remu
+ mm_port_names:
+ - REG_REMU
+
+ #############################################################################
+ # AIT = ADC Input and Timing (from node_adc_input_and_timing.vhd)
+ #############################################################################
+
+ - peripheral_name: tech_jesd204b/jesd_ctrl
+ mm_port_names:
+ - PIO_JESD_CTRL
+
+ - peripheral_name: tech_jesd204b/jesd204b_arria10
+ mm_port_names:
+ - JESD204B
+
+ - peripheral_name: dp/dp_shiftram
+ parameter_overrides:
+ - { name: g_nof_streams, value: 12 } # = S_pn
+ - { name: g_nof_words, value: 4096 }
+ - { name: g_data_w, value: 16 }
+ mm_port_names:
+ - REG_DP_SHIFTRAM
+
+ - peripheral_name: dp/dp_bsn_source
+ parameter_overrides:
+ - { name: g_nof_block_per_sync, value: 195313 } # 390625 = 2 * 195312, to have integer number of blocks in 2 s sync interval
+ mm_port_names:
+ - REG_BSN_SOURCE
+
+ # TODO: Use REG_BSN_SOURCE_V2 instead of REG_BSN_SOURCE
+ #peripheral_name: dp/dp_bsn_source_v2
+ #parameter_overrides:
+ # - { name: g_nof_clk_per_sync, value: 200000000 } # = f_adc
+ # - { name: g_block_size, value: 1024 } # = N_fft
+ # - { name: g_bsn_time_offset_w, value: 10 } # note: g_bsn_time_offset_w = ceil_log2(g_block_size)
+ #mm_port_names:
+ # - REG_BSN_SOURCE_V2
+
+ - peripheral_name: dp/dp_bsn_scheduler
+ mm_port_names:
+ - REG_BSN_SCHEDULER
+
+ - peripheral_name: dp/dp_bsn_monitor
+ peripheral_group: input
+ mm_port_names:
+ - REG_BSN_MONITOR_INPUT
+
+ - peripheral_name: diag/diag_wg_wideband
+ parameter_overrides:
+ - { name: g_nof_streams, value: 12 } # = S_pn
+ mm_port_names:
+ - REG_DIAG_WG
+ - RAM_DIAG_WG
+
+ - peripheral_name: aduh/aduh_mon_dc_power
+ parameter_overrides:
+ - { name: g_nof_streams, value: 12 } # = S_pn
+ mm_port_names:
+ - REG_ADUH_MON
+
+ # Commented RAM_ADUH_MON, because use RAM_DIAG_DATA_BUF_BSN instead
+ #- peripheral_name: aduh/aduh_mon_data_buffer
+ # parameter_overrides:
+ # - { name: g_nof_streams, value: 12 } # = S_pn
+ # - { name: g_symbol_w, value: 16 }
+ # - { name: g_nof_symbols_per_data, value: 1 }
+ # - { name: g_buffer_nof_symbols, value: 512 }
+ # - { name: g_buffer_use_sync, value: true }
+ # mm_port_names:
+ # - RAM_ADUH_MON
+
+ - peripheral_name: diag/diag_data_buffer
+ peripheral_group: bsn
+ parameter_overrides:
+ - { name: g_nof_streams, value: 12 } # = S_pn
+ - { name: g_data_w, value: 16 }
+ - { name: g_nof_data, value: 1024 }
+ mm_port_names:
+ - REG_DIAG_DATA_BUF_BSN
+ - RAM_DIAG_DATA_BUF_BSN
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 8b1fd257b00d9900b3a2a5f9a52e7540b3d5497b..96e3c42900bd80357dc8c4f7ef22ca834fa67a6e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -26,7 +26,7 @@
-- Contains all the signal processing blocks to receive and time the ADC input data
-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -37,6 +37,7 @@ USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE work.lofar2_unb2b_adc_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
ENTITY node_adc_input_and_timing IS
GENERIC (
@@ -329,7 +330,7 @@ BEGIN
g_buf_addr_w => c_wg_buf_addr_w,
g_calc_support => TRUE,
g_calc_gain_w => 1,
- g_calc_dat_w => c_wg_buf_dat_w
+ g_calc_dat_w => c_sdp_W_adc
)
PORT MAP (
-- Memory-mapped clock domain
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..15c8d9491520943af0974a751f9a88452407ecdf
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
@@ -0,0 +1,277 @@
+schema_name: args
+schema_version: 1.0
+schema_type: fpga
+
+hdl_library_name: lofar2_unb2b_beamformer
+fpga_name: lofar2_unb2b_beamformer
+fpga_description: "FPGA design lofar2_unb2b_beamformer"
+parameters:
+ - { name: c_N_pol_bf, value: 2 } # NOTE: define c_N_pol_bf before c_N_pol, to avoid that c_N_pol_bf gets substituted by 2_bf
+ - { name: c_N_pol, value: 2 }
+ - { name: c_N_beamsets, value: 2 }
+ - { name: c_N_sub, value: 512 }
+ - { name: c_N_fft, value: 1024 }
+ - { name: c_S_pn, value: 12 }
+ - { name: c_Q_fft, value: 2 }
+ - { name: c_N_taps, value: 16 }
+ - { name: c_W_adc_jesd, value: 16 }
+ - { name: c_W_adc, value: 14 }
+ - { name: c_V_sample_delay, value: 4096 }
+ - { name: c_V_si_db_large, value: 131072 }
+ - { name: c_V_si_db, value: 1024 }
+ - { name: c_W_fir_coef, value: 16 }
+ - { name: c_W_subband, value: 18 }
+ - { name: c_P_pfb, value: c_S_pn / c_Q_fft } # = 6
+ - { name: c_A_pn, value: c_S_pn / c_N_pol } # = 6
+ - { name: c_S_sub_bf, value: 488 }
+ - { name: c_f_adc_MHz, value: 200 }
+ - { name: c_W_sub_weight, value: 16 }
+ - { name: c_W_bf_weight, value: 16 }
+ - { name: c_W_beamlet_scale, value: 16 }
+ - { name: c_W_beamlet_resolution, value: 0 - 15 } # EK: FIXME support passing on negative values, workaround use 0 - positive
+ - { name: c_W_beamlet, value: 8 }
+ - { name: c_nof_clk_per_pps, value: c_f_adc_MHz * 10**6 } # = 200000000
+ - { name: c_nof_block_per_sync, value: 195313 } # TBD temporarily use 390625 = 2 * 195312, to have integer number of blocks in 2 s sync interval, TODO: remove when REG_BSN_SOURCE_V2 is used
+
+peripherals:
+ #############################################################################
+ # Factory / minimal (see ctrl_unb2b_board.vhd)
+ #############################################################################
+ - peripheral_name: unb2b_board/system_info
+ mm_port_names:
+ - ROM_SYSTEM_INFO
+ - PIO_SYSTEM_INFO
+ lock_base_address: 0x10000
+
+ - peripheral_name: unb2b_board/wdi
+ mm_port_names:
+ - PIO_WDI
+
+ - peripheral_name: unb2b_board/unb2_fpga_sens
+ mm_port_names:
+ - REG_FPGA_TEMP_SENS
+ - REG_FPGA_VOLTAGE_SENS
+
+ - peripheral_name: unb2b_board/ram_scrap
+ mm_port_names:
+ - RAM_SCRAP
+
+ - peripheral_name: eth/eth
+ mm_port_names:
+ - AVS_ETH_0_TSE
+ - AVS_ETH_0_REG
+ - AVS_ETH_0_RAM
+
+ - peripheral_name: ppsh/ppsh
+ mm_port_names:
+ - PIO_PPS
+
+ - peripheral_name: epcs/epcs
+ mm_port_names:
+ - REG_EPCS
+
+ - peripheral_name: dp/dpmm
+ mm_port_names:
+ - REG_DPMM_CTRL
+ - REG_DPMM_DATA
+
+ - peripheral_name: dp/mmdp
+ mm_port_names:
+ - REG_MMDP_CTRL
+ - REG_MMDP_DATA
+
+ - peripheral_name: remu/remu
+ mm_port_names:
+ - REG_REMU
+
+ #############################################################################
+ # AIT = ADC Input and Timing (see node_adc_input_and_timing.vhd)
+ #############################################################################
+
+ - peripheral_name: tech_jesd204b/jesd_ctrl
+ mm_port_names:
+ - PIO_JESD_CTRL
+
+ - peripheral_name: tech_jesd204b/jesd204b_arria10
+ mm_port_names:
+ - JESD204B
+
+ - peripheral_name: dp/dp_shiftram
+ parameter_overrides:
+ - { name: g_nof_streams, value: c_S_pn }
+ - { name: g_nof_words, value: c_V_sample_delay }
+ - { name: g_data_w, value: c_W_adc_jesd }
+ mm_port_names:
+ - REG_DP_SHIFTRAM
+
+ - peripheral_name: dp/dp_bsn_source
+ parameter_overrides:
+ - { name: g_nof_block_per_sync, value: c_nof_block_per_sync }
+ mm_port_names:
+ - REG_BSN_SOURCE
+
+ # TODO: Use REG_BSN_SOURCE_V2 instead of REG_BSN_SOURCE
+ #peripheral_name: dp/dp_bsn_source_v2
+ #parameter_overrides:
+ # - { name: g_nof_clk_per_sync, value: c_nof_clk_per_pps }
+ # - { name: g_block_size, value: c_N_fft }
+ # - { name: g_bsn_time_offset_w, value: ceil_log2(c_N_fft) }
+ #mm_port_names:
+ # - REG_BSN_SOURCE_V2
+
+ - peripheral_name: dp/dp_bsn_scheduler
+ mm_port_names:
+ - REG_BSN_SCHEDULER
+
+ - peripheral_name: dp/dp_bsn_monitor
+ peripheral_group: input
+ mm_port_names:
+ - REG_BSN_MONITOR_INPUT
+
+ - peripheral_name: diag/diag_wg_wideband
+ parameter_overrides:
+ - { name: g_nof_streams, value: c_S_pn }
+ mm_port_names:
+ - REG_DIAG_WG
+ - RAM_DIAG_WG
+
+ - peripheral_name: aduh/aduh_mon_dc_power
+ parameter_overrides:
+ - { name: g_nof_streams, value: c_S_pn }
+ mm_port_names:
+ - REG_ADUH_MON
+
+ # Commented RAM_ADUH_MON, because use RAM_DIAG_DATA_BUF_BSN instead
+ #- peripheral_name: aduh/aduh_mon_data_buffer
+ # parameter_overrides:
+ # - { name: g_nof_streams, value: c_S_pn }
+ # - { name: g_symbol_w, value: c_W_adc_jesd }
+ # - { name: g_nof_symbols_per_data, value: 1 }
+ # - { name: g_buffer_nof_symbols, value: 512 }
+ # - { name: g_buffer_use_sync, value: True }
+ # mm_port_names:
+ # - RAM_ADUH_MON
+
+ - peripheral_name: diag/diag_data_buffer
+ peripheral_group: bsn
+ parameter_overrides:
+ - { name: g_nof_streams, value: c_S_pn }
+ - { name: g_data_w, value: c_W_adc_jesd }
+ - { name: g_nof_data, value: c_V_si_db }
+ mm_port_names:
+ - REG_DIAG_DATA_BUF_BSN
+ - RAM_DIAG_DATA_BUF_BSN
+
+ #############################################################################
+ # Fsub = Subband Filterbank (from node_sdp_filterbank.vhd)
+ #############################################################################
+
+ - peripheral_name: si/si
+ mm_port_names:
+ - REG_SI
+
+ - peripheral_name: filter/fil_ppf_w
+ parameter_overrides:
+ - { name: g_nof_taps, value: c_N_taps }
+ - { name: g_nof_bands, value: c_N_fft }
+ - { name: g_coef_dat_w, value: c_W_fir_coef }
+ mm_port_names:
+ - RAM_FIL_COEFS
+
+ - peripheral_name: sdp/sdp_subband_equalizer
+ mm_port_names:
+ - RAM_EQUALIZER_GAINS
+
+ - peripheral_name: dp/dp_selector
+ mm_port_names:
+ - REG_DP_SELECTOR # input_select = 0 for weighted subbands, input_select = 1 for raw subbands
+
+ - peripheral_name: st/st_sst_for_sdp
+ mm_port_names:
+ - RAM_ST_SST
+
+ - peripheral_name: common/common_variable_delay
+ peripheral_group: sst
+ mm_port_names:
+ - REG_STAT_ENABLE
+
+ - peripheral_name: sdp/sdp_statistics_offload_hdr_dat_sst
+ peripheral_group: sst
+ mm_port_names:
+ - REG_STAT_HDR_INFO
+
+ #############################################################################
+ # BF = Beamformer (from node_sdp_beamformer.vhd)
+ #############################################################################
+
+ - peripheral_name: sdp/sdp_info
+ mm_port_names:
+ - REG_SDP_INFO
+
+ - peripheral_name: reorder/reorder_col_wide
+ number_of_peripherals: c_N_beamsets # lofar2_unb2b_beamformer.vhd
+ parameter_overrides:
+ - { name: g_wb_factor, value: c_P_pfb }
+ - { name: g_nof_ch_in, value: c_N_sub * c_Q_fft }
+ - { name: g_nof_ch_sel, value: c_S_sub_bf * c_Q_fft }
+ mm_port_names:
+ - RAM_SS_SS_WIDE
+
+ - peripheral_name: sdp/sdp_bf_weights
+ number_of_peripherals: c_N_beamsets # lofar2_unb2b_beamformer.vhd
+ parameter_overrides:
+ - { name: g_nof_instances, value: c_N_pol_bf * c_A_pn } # A_pn = P_pfb = 6
+ - { name: g_nof_gains, value: c_N_pol * c_S_sub_bf } # N_pol = Q_fft = 2
+ mm_port_names:
+ - RAM_BF_WEIGHTS
+
+ - peripheral_name: sdp/sdp_bf_scale
+ number_of_peripherals: c_N_beamsets # lofar2_unb2b_beamformer.vhd
+ parameter_overrides:
+ - { name: g_gain_w, value: c_W_beamlet_scale }
+ - { name: g_lsb_w, value: 0 - c_W_beamlet_resolution}
+ mm_port_names:
+ - REG_BF_SCALE
+
+ - peripheral_name: sdp/sdp_beamformer_output_hdr_dat
+ number_of_peripherals: c_N_beamsets # lofar2_unb2b_beamformer.vhd
+ mm_port_names:
+ - REG_HDR_DAT
+
+ - peripheral_name: dp/dp_xonoff
+ number_of_peripherals: c_N_beamsets # lofar2_unb2b_beamformer.vhd
+ parameter_overrides:
+ - { name: g_nof_streams, value: 1 }
+ - { name: g_combine_streams, value: False }
+ mm_port_names:
+ - REG_DP_XONOFF
+
+ - peripheral_name: st/st_bst_for_sdp
+ mm_port_names:
+ - RAM_ST_BST
+
+ - peripheral_name: common/common_variable_delay
+ peripheral_group: bst
+ mm_port_names:
+ - REG_STAT_ENABLE_BST
+
+ - peripheral_name: sdp/sdp_statistics_offload_hdr_dat_bst
+ peripheral_group: bst
+ mm_port_names:
+ - REG_STAT_HDR_INFO_BST
+
+ - peripheral_name: nw_10GbE/nw_10GbE_unb2legacy
+ peripheral_group: beamlet_output
+ parameter_overrides:
+ - { name: g_nof_macs, value: 1 }
+ mm_port_names:
+ - REG_NW_10GBE_MAC
+
+ - peripheral_name: nw_10GbE/nw_10GbE_eth10g
+ peripheral_group: beamlet_output
+ parameter_overrides:
+ - { name: g_nof_macs, value: 1 }
+ mm_port_names:
+ - REG_NW_10GBE_ETH10G
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl
index b9b185d65f45da9dd8b0cba70ebb5c255029ec7e..851a631d744084345d1228d08c4c7b09bce10c5c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl
@@ -72,40 +72,41 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[4]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST
-### QSFP_0_0
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[0]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0]
-
-### QSFP_0_RX
-set_location_assignment PIN_AN38 -to QSFP_0_RX[0]
-set_location_assignment PIN_AM40 -to QSFP_0_RX[1]
-set_location_assignment PIN_AK40 -to QSFP_0_RX[2]
-set_location_assignment PIN_AJ38 -to QSFP_0_RX[3]
-
-### QSFP_0_TX
-set_location_assignment PIN_AN42 -to QSFP_0_TX[0]
-set_location_assignment PIN_AM44 -to QSFP_0_TX[1]
-set_location_assignment PIN_AK44 -to QSFP_0_TX[2]
-set_location_assignment PIN_AJ42 -to QSFP_0_TX[3]
+### QSFP_1_0
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[0]
+
+### QSFP_1_RX
+set_location_assignment PIN_AC38 -to QSFP_1_RX[0]
+set_location_assignment PIN_AD40 -to QSFP_1_RX[1]
+set_location_assignment PIN_AF40 -to QSFP_1_RX[2]
+set_location_assignment PIN_AG38 -to QSFP_1_RX[3]
+
+### QSFP_1_TX
+set_location_assignment PIN_AC42 -to QSFP_1_TX[0]
+set_location_assignment PIN_AD44 -to QSFP_1_TX[1]
+set_location_assignment PIN_AF44 -to QSFP_1_TX[2]
+set_location_assignment PIN_AG42 -to QSFP_1_TX[3]
+
#=====================
# JESD pins
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
index d1e04a698ce4bcbee592cde4a04cfd68fe45efd4..f81831264c54622703af2c96fabe1c164ced74af 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
@@ -77,8 +77,8 @@ ENTITY lofar2_unb2b_beamformer_one_node IS
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
-- front transceivers
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
@@ -160,8 +160,8 @@ BEGIN
SA_CLK => SA_CLK,
-- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
-- LEDs
QSFP_LED => QSFP_LED,
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
index f71e3bc47ae99291e402634751d1410167a3e742..b543da94832479e51499a57d5fcbe6974a8c86dc 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
@@ -77,8 +77,8 @@ ENTITY lofar2_unb2b_beamformer_one_node_256MHz IS
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
-- front transceivers
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
@@ -160,8 +160,8 @@ BEGIN
SA_CLK => SA_CLK,
-- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
-- LEDs
QSFP_LED => QSFP_LED,
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
index 713a076bafdea9b2bc0346797ea45a4e1551446c..f894280241e8152fb4286f01898c31d001f18756 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
@@ -88,8 +88,8 @@ ENTITY lofar2_unb2b_beamformer IS
-- Transceiver clocks
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
-- front transceivers
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
@@ -652,7 +652,8 @@ BEGIN
dp_clk => dp_clk,
dp_rst => dp_rst,
- -- mm control buses
+ -- mm control buses
+ jesd_ctrl_mosi => c_mem_mosi_rst,
jesd204b_mosi => jesd204b_mosi,
jesd204b_miso => jesd204b_miso,
reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
@@ -720,7 +721,13 @@ BEGIN
ram_gains_mosi => ram_equalizer_gains_mosi,
ram_gains_miso => ram_equalizer_gains_miso,
reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso
+ reg_selector_miso => reg_dp_selector_miso,
+
+ sdp_info => sdp_info,
+ gn_id => ID(c_sdp_W_gn_id-1 DOWNTO 0),
+ eth_src_mac => eth_src_mac,
+ ip_src_addr => ip_src_addr,
+ udp_src_port => udp_src_port
);
@@ -913,8 +920,8 @@ BEGIN
-----------------------------------------------------------------------------
-- put the QSFP_TX/RX ports into arrays
- i_QSFP_RX(0) <= QSFP_0_RX;
- QSFP_0_TX <= i_QSFP_TX(0);
+ i_QSFP_RX(0) <= QSFP_1_RX;
+ QSFP_1_TX <= i_QSFP_TX(0);
------------
-- Front IO
------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
index 2835898c6e22aca78028e8df312539a1a65d3313..6b60e21f0ab95664410e5e844ebb2c187d442c36 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
@@ -93,9 +93,9 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_beamformer IS
CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
-- WG
- CONSTANT c_full_scale_ampl : REAL := REAL(2**(18-1)-1); -- = full scale of WG
+ CONSTANT c_full_scale_ampl : REAL := REAL(2**(14-1)-1); -- = full scale of WG
CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/2; -- in number of lsb
+ CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1) / 2; -- in number of lsb
CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
@@ -215,7 +215,7 @@ BEGIN
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
- proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
jesd204b_sysref <= pps;
ext_pps <= pps;
@@ -261,8 +261,8 @@ BEGIN
-- Transceiver clocks
SA_CLK => SA_CLK,
-- front transceivers
- QSFP_0_RX => si_lpbk_0,
- QSFP_0_TX => si_lpbk_0,
+ QSFP_1_RX => si_lpbk_0,
+ QSFP_1_TX => si_lpbk_0,
-- LEDs
QSFP_LED => open,
@@ -337,7 +337,7 @@ BEGIN
-- Enable UDP offload (dp_xonoff) of beamset 0
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff,0 , 1, tb_clk);
- --mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff,2 , 1, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff,2 , 1, tb_clk);
----------------------------------------------------------------------------
-- Enable BS
@@ -458,7 +458,7 @@ BEGIN
-- Read 10GbE Stream
---------------------------------------------------------------------------
proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.sop);
- FOR I IN 0 TO 9 LOOP -- Packet header
+ FOR I IN 0 TO 8 LOOP -- Packet header is 9.25 words wide, which can be discarded
proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
proc_common_wait_some_cycles(ext_clk, 1);
END LOOP;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..8913b3d218334598cac6e04fa4428ffba9c867ed
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
@@ -0,0 +1,173 @@
+schema_name : args
+schema_version: 1.0
+schema_type : fpga
+
+hdl_library_name: lofar2_unb2b_filterbank
+fpga_name : lofar2_unb2b_filterbank
+fpga_description: "FPGA design lofar2_unb2b_filterbank"
+
+peripherals:
+ #############################################################################
+ # Factory / minimal (see ctrl_unb2b_board.vhd)
+ #############################################################################
+ - peripheral_name: unb2b_board/system_info
+ mm_port_names:
+ - ROM_SYSTEM_INFO
+ - PIO_SYSTEM_INFO
+ lock_base_address: 0x10000
+
+ - peripheral_name: unb2b_board/wdi
+ mm_port_names:
+ - PIO_WDI
+
+ - peripheral_name: unb2b_board/unb2_fpga_sens
+ mm_port_names:
+ - REG_FPGA_TEMP_SENS
+ - REG_FPGA_VOLTAGE_SENS
+
+ - peripheral_name: unb2b_board/ram_scrap
+ mm_port_names:
+ - RAM_SCRAP
+
+ - peripheral_name: eth/eth
+ mm_port_names:
+ - AVS_ETH_0_TSE
+ - AVS_ETH_0_REG
+ - AVS_ETH_0_RAM
+
+ - peripheral_name: ppsh/ppsh
+ mm_port_names:
+ - PIO_PPS
+
+ - peripheral_name: epcs/epcs
+ mm_port_names:
+ - REG_EPCS
+
+ - peripheral_name: dp/dpmm
+ mm_port_names:
+ - REG_DPMM_CTRL
+ - REG_DPMM_DATA
+
+ - peripheral_name: dp/mmdp
+ mm_port_names:
+ - REG_MMDP_CTRL
+ - REG_MMDP_DATA
+
+ - peripheral_name: remu/remu
+ mm_port_names:
+ - REG_REMU
+
+ #############################################################################
+ # AIT = ADC Input and Timing (see node_adc_input_and_timing.vhd)
+ #############################################################################
+
+ - peripheral_name: tech_jesd204b/jesd_ctrl
+ mm_port_names:
+ - PIO_JESD_CTRL
+
+ - peripheral_name: tech_jesd204b/jesd204b_arria10
+ mm_port_names:
+ - JESD204B
+
+ - peripheral_name: dp/dp_shiftram
+ parameter_overrides:
+ - { name: g_nof_streams, value: 12 } # = S_pn
+ - { name: g_nof_words, value: 4096 }
+ - { name: g_data_w, value: 16 }
+ mm_port_names:
+ - REG_DP_SHIFTRAM
+
+ - peripheral_name: dp/dp_bsn_source
+ parameter_overrides:
+ - { name: g_nof_block_per_sync, value: 195313 } # 390625 = 2 * 195312, to have integer number of blocks in 2 s sync interval
+ mm_port_names:
+ - REG_BSN_SOURCE
+
+ # TODO: Use REG_BSN_SOURCE_V2 instead of REG_BSN_SOURCE
+ #peripheral_name: dp/dp_bsn_source_v2
+ #parameter_overrides:
+ # - { name: g_nof_clk_per_sync, value: 200000000 } # = f_adc
+ # - { name: g_block_size, value: 1024 } # = N_fft
+ # - { name: g_bsn_time_offset_w, value: 10 } # note: g_bsn_time_offset_w = ceil_log2(g_block_size)
+ #mm_port_names:
+ # - REG_BSN_SOURCE_V2
+
+ - peripheral_name: dp/dp_bsn_scheduler
+ mm_port_names:
+ - REG_BSN_SCHEDULER
+
+ - peripheral_name: dp/dp_bsn_monitor
+ peripheral_group: input
+ mm_port_names:
+ - REG_BSN_MONITOR_INPUT
+
+ - peripheral_name: diag/diag_wg_wideband
+ parameter_overrides:
+ - { name: g_nof_streams, value: 12 } # = S_pn
+ mm_port_names:
+ - REG_DIAG_WG
+ - RAM_DIAG_WG
+
+ - peripheral_name: aduh/aduh_mon_dc_power
+ parameter_overrides:
+ - { name: g_nof_streams, value: 12 } # = S_pn
+ mm_port_names:
+ - REG_ADUH_MON
+
+ # Commented RAM_ADUH_MON, because use RAM_DIAG_DATA_BUF_BSN instead
+ #- peripheral_name: aduh/aduh_mon_data_buffer
+ # parameter_overrides:
+ # - { name: g_nof_streams, value: 12 } # = S_pn
+ # - { name: g_symbol_w, value: 16 }
+ # - { name: g_nof_symbols_per_data, value: 1 }
+ # - { name: g_buffer_nof_symbols, value: 512 }
+ # - { name: g_buffer_use_sync, value: true }
+ # mm_port_names:
+ # - RAM_ADUH_MON
+
+ - peripheral_name: diag/diag_data_buffer
+ peripheral_group: bsn
+ parameter_overrides:
+ - { name: g_nof_streams, value: 12 } # = S_pn
+ - { name: g_data_w, value: 16 }
+ - { name: g_nof_data, value: 1024 }
+ mm_port_names:
+ - REG_DIAG_DATA_BUF_BSN
+ - RAM_DIAG_DATA_BUF_BSN
+
+ #############################################################################
+ # Fsub = Subband Filterbank (from node_sdp_filterbank.vhd)
+ #############################################################################
+
+ - peripheral_name: si/si
+ mm_port_names:
+ - REG_SI
+
+ - peripheral_name: filter/fil_ppf_w
+ parameter_overrides:
+ - { name: g_wb_factor, value: 1 }
+ - { name: g_nof_taps, value: 16 } # = N_taps
+ - { name: g_nof_bands, value: 1024 } # = N_fft
+ - { name: g_coef_dat_w, value: 16 } # = W_fir_coef
+ mm_port_names:
+ - RAM_FIL_COEFS
+
+ - peripheral_name: sdp/sdp_subband_equalizer
+ mm_port_names:
+ - RAM_EQUALIZER_GAINS
+
+ - peripheral_name: dp/dp_selector
+ mm_port_names:
+ - REG_DP_SELECTOR # input_select = 0 for weighted subbands, input_select = 1 for raw subbands
+
+ - peripheral_name: st/st_sst_for_sdp
+ mm_port_names:
+ - RAM_ST_SST
+
+ - peripheral_name: common/common_variable_delay
+ mm_port_names:
+ - REG_STAT_ENABLE
+
+ - peripheral_name: sdp/sdp_statistics_offload_hdr_dat_sst
+ mm_port_names:
+ - REG_STAT_HDR_INFO
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_eth_0.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_eth_0.ip
index 4e21d21150344b6e7ed0b700bb14822d13c23b0b..dfcf76b7fdf34f0aa290f54c0e39140e94038507 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_eth_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_eth_0.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_avs_eth_0</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_avs_eth_0</spirit:library>
<spirit:name>avs_eth_0</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -55,7 +55,7 @@
<spirit:parameter>
<spirit:name>associatedAddressablePoint</spirit:name>
<spirit:displayName>Associated addressable interface</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">qsys_unb2c_minimal_avs_eth_0.mms_reg</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">qsys_lofar2_unb2b_filterbank_avs_eth_0.mms_reg</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
@@ -2101,7 +2101,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_avs_eth_0</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_avs_eth_0</spirit:library>
<spirit:name>avs2_eth_coe</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -2201,7 +2201,7 @@
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
- <value>qsys_unb2c_minimal_avs_eth_0.mms_reg</value>
+ <value>qsys_lofar2_unb2b_filterbank_avs_eth_0.mms_reg</value>
</entry>
<entry>
<key>associatedClock</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_clk_0.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_clk_0.ip
index 1c5f2f856736d4dd45540a8c65ed3bfb8dca0ebc..c41f9c5653b879ef719b44836f1c9f8bd76db192 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_clk_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_clk_0.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>Altera Corporation</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_clk_0</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_clk_0</spirit:library>
<spirit:name>clk_0</spirit:name>
<spirit:version>18.0</spirit:version>
<spirit:busInterfaces>
@@ -229,7 +229,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>Altera Corporation</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_clk_0</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_clk_0</spirit:library>
<spirit:name>clock_source</spirit:name>
<spirit:version>18.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
index adf4c447bd056ed52e13154a1f131b2fb9ffda57..366e44d371e5ae91aa9d1e4e26418a2c3cdfb328 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x300' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3200' end='0x3240' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3240' end='0x3260' datawidth='32' /><slave name='reg_epcs.mem' start='0x3260' end='0x3280' datawidth='32' /><slave name='reg_remu.mem' start='0x3280' end='0x32A0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x32A0' end='0x32B0' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x32B0' end='0x32C0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x32C0' end='0x32C8' datawidth='32' /><slave name='reg_si.mem' start='0x32C8' end='0x32D0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x32D0' end='0x32D8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x32D8' end='0x32E0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x32E0' end='0x32E8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x32E8' end='0x32F0' datawidth='32' /><slave name='pio_pps.mem' start='0x32F0' end='0x32F8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x32F8' end='0x3300' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='jesd204b.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_wg.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x40000' end='0x50000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x50000' end='0x60000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x70000' end='0x78000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0x78000' end='0x7A000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x7A000' end='0x7B000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_wg.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x300' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3300' end='0x3340' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3340' end='0x3380' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3380' end='0x33A0' datawidth='32' /><slave name='reg_epcs.mem' start='0x33A0' end='0x33C0' datawidth='32' /><slave name='reg_remu.mem' start='0x33C0' end='0x33E0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x33E0' end='0x33F0' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x33F0' end='0x3400' datawidth='32' /><slave name='reg_stat_enable.mem' start='0x3400' end='0x3408' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3408' end='0x3410' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3410' end='0x3418' datawidth='32' /><slave name='reg_si.mem' start='0x3418' end='0x3420' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3420' end='0x3428' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3428' end='0x3430' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3430' end='0x3438' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3438' end='0x3440' datawidth='32' /><slave name='pio_pps.mem' start='0x3440' end='0x3448' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3448' end='0x3450' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='jesd204b.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_wg.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x40000' end='0x50000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x50000' end='0x60000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x70000' end='0x78000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0x78000' end='0x7A000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x7A000' end='0x7B000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x300' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3200' end='0x3240' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3240' end='0x3260' datawidth='32' /><slave name='reg_epcs.mem' start='0x3260' end='0x3280' datawidth='32' /><slave name='reg_remu.mem' start='0x3280' end='0x32A0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x32A0' end='0x32B0' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x32B0' end='0x32C0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x32C0' end='0x32C8' datawidth='32' /><slave name='reg_si.mem' start='0x32C8' end='0x32D0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x32D0' end='0x32D8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x32D8' end='0x32E0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x32E0' end='0x32E8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x32E8' end='0x32F0' datawidth='32' /><slave name='pio_pps.mem' start='0x32F0' end='0x32F8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x32F8' end='0x3300' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='jesd204b.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_wg.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x40000' end='0x50000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x50000' end='0x60000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x70000' end='0x78000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0x78000' end='0x7A000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x7A000' end='0x7B000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_wg.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x300' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3300' end='0x3340' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3340' end='0x3380' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3380' end='0x33A0' datawidth='32' /><slave name='reg_epcs.mem' start='0x33A0' end='0x33C0' datawidth='32' /><slave name='reg_remu.mem' start='0x33C0' end='0x33E0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x33E0' end='0x33F0' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x33F0' end='0x3400' datawidth='32' /><slave name='reg_stat_enable.mem' start='0x3400' end='0x3408' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3408' end='0x3410' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3410' end='0x3418' datawidth='32' /><slave name='reg_si.mem' start='0x3418' end='0x3420' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3420' end='0x3428' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3428' end='0x3430' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3430' end='0x3438' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3438' end='0x3440' datawidth='32' /><slave name='pio_pps.mem' start='0x3440' end='0x3448' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3448' end='0x3450' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='jesd204b.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_wg.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x40000' end='0x50000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x50000' end='0x60000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x70000' end='0x78000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0x78000' end='0x7A000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x7A000' end='0x7B000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jtag_uart_0.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jtag_uart_0.ip
index 2c36bb55a9b3d00fdbd3ca724aede8dc93ba5297..4568efe882e441e82b48e67ba93b908840b30236 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jtag_uart_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jtag_uart_0.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>Intel Corporation</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_jtag_uart_0</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_jtag_uart_0</spirit:library>
<spirit:name>jtag_uart_0</spirit:name>
<spirit:version>18.0</spirit:version>
<spirit:busInterfaces>
@@ -347,7 +347,7 @@
<spirit:parameter>
<spirit:name>associatedAddressablePoint</spirit:name>
<spirit:displayName>Associated addressable interface</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">qsys_unb2c_minimal_jtag_uart_0.avalon_jtag_slave</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">qsys_lofar2_unb2b_filterbank_jtag_uart_0.avalon_jtag_slave</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
@@ -549,7 +549,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>Intel Corporation</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_jtag_uart_0</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_jtag_uart_0</spirit:library>
<spirit:name>altera_avalon_jtag_uart</spirit:name>
<spirit:version>18.0</spirit:version>
</altera:entity_info>
@@ -1114,7 +1114,7 @@
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
- <value>qsys_unb2c_minimal_jtag_uart_0.avalon_jtag_slave</value>
+ <value>qsys_lofar2_unb2b_filterbank_jtag_uart_0.avalon_jtag_slave</value>
</entry>
<entry>
<key>associatedClock</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_onchip_memory2_0.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_onchip_memory2_0.ip
index 09b10365fa9eb74435bc768b229a528506db5644..011047695d2d6ed30a89b400e6e4d1940915449f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_onchip_memory2_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_onchip_memory2_0.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>Intel Corporation</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_onchip_memory2_0</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_onchip_memory2_0</spirit:library>
<spirit:name>onchip_memory2_0</spirit:name>
<spirit:version>18.0</spirit:version>
<spirit:busInterfaces>
@@ -518,7 +518,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>Intel Corporation</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_onchip_memory2_0</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_onchip_memory2_0</spirit:library>
<spirit:name>altera_avalon_onchip_memory2</spirit:name>
<spirit:version>18.0</spirit:version>
</altera:entity_info>
@@ -652,7 +652,7 @@
<spirit:parameter>
<spirit:name>autoInitializationFileName</spirit:name>
<spirit:displayName>autoInitializationFileName</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="autoInitializationFileName">qsys_unb2c_minimal_onchip_memory2_0_onchip_memory2_0</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="autoInitializationFileName">qsys_lofar2_unb2b_filterbank_onchip_memory2_0_onchip_memory2_0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.ip
new file mode 100644
index 0000000000000000000000000000000000000000..ec11145c07827c744579019beefb67ea1b76af85
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.ip
@@ -0,0 +1,1439 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip
index 1d2e8bf5dad59d5d29d0720764db4458522ea73e..0c5a26c79053362dc2bf1931592eb270db04b14f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_pio_pps</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_pio_pps</spirit:library>
<spirit:name>pio_pps</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -766,7 +766,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_pio_pps</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_pio_pps</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip
index 0fc6e8f1bdfdf7cbfa8d01fc2465da3443766f24..e80b5b2e873387a2c4f06c3523a8da5be60d0d66 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_pio_system_info</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_pio_system_info</spirit:library>
<spirit:name>pio_system_info</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_pio_system_info</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_pio_system_info</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip
index b6c98aaa6799fb7df90c035819a393fa46f0ac9c..b522f0c3cfd6d95b815c76f1acf8e6bd74a9d402 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>Intel Corporation</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_pio_wdi</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_pio_wdi</spirit:library>
<spirit:name>pio_wdi</spirit:name>
<spirit:version>18.0</spirit:version>
<spirit:busInterfaces>
@@ -498,7 +498,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>Intel Corporation</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_pio_wdi</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_pio_wdi</spirit:library>
<spirit:name>altera_avalon_pio</spirit:name>
<spirit:version>18.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip
index eaa2adcc8488d8a80c26c9990d6901d193f7c749..9bd29c2746c3a6475e48d8f0771d9bb76b2c66d1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_dpmm_ctrl</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</spirit:library>
<spirit:name>reg_dpmm_ctrl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -766,7 +766,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_dpmm_ctrl</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip
index 564b626b4013fe44dee45248c8f7f743b7419c61..76c7e7b885772efdc33d6b8ec1342722791dfc03 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_dpmm_data</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</spirit:library>
<spirit:name>reg_dpmm_data</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -766,7 +766,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_dpmm_data</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip
index b07b1b402e172532483dc1ef8d9d09c7095eef71..ec98f8b08116b8b1acb7dddb6b71bff9063809de 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_epcs</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_epcs</spirit:library>
<spirit:name>reg_epcs</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_epcs</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_epcs</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip
index 9efe5c57caeabcbdbfb92af45d701d3dc187068f..e2050a89fcfc14da92d5e6eb9564b9b8baeacc5a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_fpga_temp_sens</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</spirit:library>
<spirit:name>reg_fpga_temp_sens</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_fpga_temp_sens</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip
index 4d652f96ceccd7fdbd240e65b5f0ee806000a463..72c022d88b3406438ca6ec4c201bee897ff2ab4a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_fpga_voltage_sens</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</spirit:library>
<spirit:name>reg_fpga_voltage_sens</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_fpga_voltage_sens</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip
index 4fff1367f07a2f1261f8e62c4069470bd930e1f2..f3c0dd12daade60ac83baf8996fd537f228531a0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_mmdp_ctrl</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</spirit:library>
<spirit:name>reg_mmdp_ctrl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -766,7 +766,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_mmdp_ctrl</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip
index 450ee4447b7ade031675181089797226ea80e01b..b5cad0190ea6466cae1c6b6e5e1c2a069a31316a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_mmdp_data</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</spirit:library>
<spirit:name>reg_mmdp_data</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -766,7 +766,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_mmdp_data</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip
index 6f360cba7bd7b3657e0d7d1d5428aa2042ceae7c..397734ec37f21561fd6a540aceb48c029ecf2e47 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_remu</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_remu</spirit:library>
<spirit:name>reg_remu</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_remu</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_remu</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_sdp_info.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_sdp_info.ip
new file mode 100644
index 0000000000000000000000000000000000000000..170c1166f70df77886b9690a692b047e7121d78e
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_sdp_info.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_sdp_info</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_filterbank_reg_sdp_info</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>3</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>3</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_sdp_info</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>64</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>6</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_filterbank_reg_sdp_info.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_filterbank_reg_sdp_info.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_filterbank_reg_sdp_info.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_filterbank_reg_sdp_info.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_filterbank_reg_sdp_info.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_filterbank_reg_sdp_info.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_filterbank_reg_sdp_info.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_filterbank_reg_sdp_info.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_filterbank_reg_sdp_info.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_filterbank_reg_sdp_info.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_enable.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_enable.ip
new file mode 100644
index 0000000000000000000000000000000000000000..eafb11f78cd9df02557d28cd186a2b6d03cb8678
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_enable.ip
@@ -0,0 +1,1439 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_stat_enable</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_filterbank_reg_stat_enable</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_stat_enable</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_enable.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_enable.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_enable.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_enable.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_enable.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_enable.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_enable.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_enable.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_enable.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_enable.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.ip
new file mode 100644
index 0000000000000000000000000000000000000000..47df3ffaaf9ed09f09484d743ace0926381f16fa
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>5</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>5</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_pmbus.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_pmbus.ip
index b4758115354d88a81255e5a80f01d6eee34f0c5f..6e0d4cc59d664b9ae27ea5c3c970852f7ecec2cd 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_pmbus.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_pmbus.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_unb_pmbus</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_unb_pmbus</spirit:library>
<spirit:name>reg_unb_pmbus</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_unb_pmbus</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_unb_pmbus</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_sens.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_sens.ip
index 8494572d5c37c2482118d8e7fe5f926f304d7e21..f864342f163bebc016f43764ab27e7863c99806d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_sens.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_sens.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_unb_sens</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_unb_sens</spirit:library>
<spirit:name>reg_unb_sens</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_unb_sens</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_unb_sens</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wdi.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wdi.ip
index 9d869abbb1c1d0327f606185d5986fe15b2956cd..470b754e7d1042eac69d9af7198ec503d97810ae 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wdi.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wdi.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_wdi</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_wdi</spirit:library>
<spirit:name>reg_wdi</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -766,7 +766,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_reg_wdi</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_reg_wdi</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
index 6a022a4ad6872eb4f018f1a1b7129ba2d000c943..397f28f6c14859580d6cf52f7f213bc5fad2d497 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_rom_system_info</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_rom_system_info</spirit:library>
<spirit:name>rom_system_info</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_rom_system_info</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_rom_system_info</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_timer_0.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_timer_0.ip
index 1b867a0f5823e0af3b30bb17b25f2de51a3e5177..84e64358ce6bfba72e0f49e464d77aad58abf0fd 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_timer_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_timer_0.ip
@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>Intel Corporation</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_timer_0</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_timer_0</spirit:library>
<spirit:name>timer_0</spirit:name>
<spirit:version>18.0</spirit:version>
<spirit:busInterfaces>
@@ -55,7 +55,7 @@
<spirit:parameter>
<spirit:name>associatedAddressablePoint</spirit:name>
<spirit:displayName>Associated addressable interface</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">qsys_unb2c_minimal_timer_0.s1</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">qsys_lofar2_unb2b_filterbank_timer_0.s1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
@@ -517,7 +517,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>Intel Corporation</spirit:vendor>
- <spirit:library>qsys_unb2c_minimal_timer_0</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_filterbank_timer_0</spirit:library>
<spirit:name>altera_avalon_timer</spirit:name>
<spirit:version>18.0</spirit:version>
</altera:entity_info>
@@ -768,7 +768,7 @@
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
- <value>qsys_unb2c_minimal_timer_0.s1</value>
+ <value>qsys_lofar2_unb2b_filterbank_timer_0.s1</value>
</entry>
<entry>
<key>associatedClock</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank.sdc b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank.sdc
index a041aae6d83c1972821b3e27f333568006a8c93e..46111751707cc59f2c76e125f70af2409c25abb2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank.sdc
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank.sdc
@@ -98,7 +98,8 @@ set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_nat
#-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
# false paths added for the jesd test design
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|link_clk}]
-set_false_path -from [get_clocks {*core_pll|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|frame_clk}]
-set_false_path -from [get_clocks {*core_pll|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|link_clk}]
+set_false_path -from [get_clocks {*iopll_0|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*u_ip_arria10_e1sg_jesd204b_rx_corepll_200MHz|iopll_0|frame_clk}]
+set_false_path -from [get_clocks {*u_ip_arria10_e1sg_jesd204b_rx_corepll_200MHz|iopll_0|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/qsys_lofar2_unb2b_filterbank.qsys b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/qsys_lofar2_unb2b_filterbank.qsys
index ac72e12048038507d43471a2df6516f12d3f4e8a..5789d953891f37af312dfa2809a09eb454675365 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/qsys_lofar2_unb2b_filterbank.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/qsys_lofar2_unb2b_filterbank.qsys
@@ -78,6 +78,11 @@
value = "21";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
}
element jesd204b.mem
{
@@ -99,7 +104,7 @@
{
datum baseAddress
{
- value = "13048";
+ value = "13384";
type = "String";
}
}
@@ -132,6 +137,22 @@
type = "String";
}
}
+ element pio_jesd_ctrl
+ {
+ datum _sortIndex
+ {
+ value = "43";
+ type = "int";
+ }
+ }
+ element pio_jesd_ctrl.mem
+ {
+ datum baseAddress
+ {
+ value = "12296";
+ type = "String";
+ }
+ }
element pio_pps
{
datum _sortIndex
@@ -141,7 +162,7 @@
}
datum sopceditor_expanded
{
- value = "0";
+ value = "1";
type = "boolean";
}
}
@@ -149,7 +170,7 @@
{
datum baseAddress
{
- value = "13040";
+ value = "13376";
type = "String";
}
}
@@ -162,7 +183,7 @@
}
datum sopceditor_expanded
{
- value = "0";
+ value = "1";
type = "boolean";
}
}
@@ -330,7 +351,7 @@
{
datum baseAddress
{
- value = "512";
+ value = "768";
type = "String";
}
}
@@ -341,6 +362,11 @@
value = "22";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
}
element reg_bsn_monitor_input.mem
{
@@ -357,12 +383,17 @@
value = "25";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
}
element reg_bsn_scheduler.mem
{
datum baseAddress
{
- value = "12992";
+ value = "13328";
type = "String";
}
}
@@ -373,12 +404,17 @@
value = "24";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
}
element reg_bsn_source.mem
{
datum baseAddress
{
- value = "12960";
+ value = "13280";
type = "String";
}
}
@@ -410,7 +446,7 @@
{
datum baseAddress
{
- value = "12976";
+ value = "13296";
type = "String";
}
}
@@ -426,7 +462,7 @@
{
datum baseAddress
{
- value = "12296";
+ value = "13320";
type = "String";
}
}
@@ -437,6 +473,11 @@
value = "26";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
}
element reg_dp_shiftram.mem
{
@@ -463,7 +504,7 @@
{
datum baseAddress
{
- value = "13032";
+ value = "13368";
type = "String";
}
}
@@ -484,7 +525,7 @@
{
datum baseAddress
{
- value = "13024";
+ value = "13360";
type = "String";
}
}
@@ -505,7 +546,7 @@
{
datum baseAddress
{
- value = "12896";
+ value = "13216";
type = "String";
}
}
@@ -521,7 +562,7 @@
{
datum baseAddress
{
- value = "12864";
+ value = "13184";
type = "String";
}
}
@@ -542,7 +583,7 @@
{
datum baseAddress
{
- value = "12800";
+ value = "13120";
type = "String";
}
}
@@ -563,7 +604,7 @@
{
datum baseAddress
{
- value = "13016";
+ value = "13352";
type = "String";
}
}
@@ -584,7 +625,7 @@
{
datum baseAddress
{
- value = "13008";
+ value = "13344";
type = "String";
}
}
@@ -605,7 +646,23 @@
{
datum baseAddress
{
- value = "12928";
+ value = "13248";
+ type = "String";
+ }
+ }
+ element reg_sdp_info
+ {
+ datum _sortIndex
+ {
+ value = "40";
+ type = "int";
+ }
+ }
+ element reg_sdp_info.mem
+ {
+ datum baseAddress
+ {
+ value = "13056";
type = "String";
}
}
@@ -621,7 +678,39 @@
{
datum baseAddress
{
- value = "13000";
+ value = "13336";
+ type = "String";
+ }
+ }
+ element reg_stat_enable
+ {
+ datum _sortIndex
+ {
+ value = "41";
+ type = "int";
+ }
+ }
+ element reg_stat_enable.mem
+ {
+ datum baseAddress
+ {
+ value = "13312";
+ type = "String";
+ }
+ }
+ element reg_stat_hdr_dat
+ {
+ datum _sortIndex
+ {
+ value = "42";
+ type = "int";
+ }
+ }
+ element reg_stat_hdr_dat.mem
+ {
+ datum baseAddress
+ {
+ value = "256";
type = "String";
}
}
@@ -637,7 +726,7 @@
{
datum baseAddress
{
- value = "768";
+ value = "12544";
type = "String";
}
}
@@ -653,7 +742,7 @@
{
datum baseAddress
{
- value = "12544";
+ value = "12800";
type = "String";
}
}
@@ -690,12 +779,17 @@
value = "23";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
}
element reg_wg.mem
{
datum baseAddress
{
- value = "256";
+ value = "512";
type = "String";
}
}
@@ -917,6 +1011,41 @@
internal="jesd204b.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="pio_jesd_ctrl_address"
+ internal="pio_jesd_ctrl.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_jesd_ctrl_clk"
+ internal="pio_jesd_ctrl.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_jesd_ctrl_read"
+ internal="pio_jesd_ctrl.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_jesd_ctrl_readdata"
+ internal="pio_jesd_ctrl.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_jesd_ctrl_reset"
+ internal="pio_jesd_ctrl.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_jesd_ctrl_write"
+ internal="pio_jesd_ctrl.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_jesd_ctrl_writedata"
+ internal="pio_jesd_ctrl.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="pio_pps_address"
internal="pio_pps.address"
@@ -1800,6 +1929,41 @@
internal="reg_remu.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_sdp_info_address"
+ internal="reg_sdp_info.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_sdp_info_clk"
+ internal="reg_sdp_info.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_sdp_info_read"
+ internal="reg_sdp_info.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_sdp_info_readdata"
+ internal="reg_sdp_info.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_sdp_info_reset"
+ internal="reg_sdp_info.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_sdp_info_write"
+ internal="reg_sdp_info.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_sdp_info_writedata"
+ internal="reg_sdp_info.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_si_address"
internal="reg_si.address"
@@ -1819,6 +1983,76 @@
internal="reg_si.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_stat_enable_address"
+ internal="reg_stat_enable.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_clk"
+ internal="reg_stat_enable.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_read"
+ internal="reg_stat_enable.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_readdata"
+ internal="reg_stat_enable.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_reset"
+ internal="reg_stat_enable.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_write"
+ internal="reg_stat_enable.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_writedata"
+ internal="reg_stat_enable.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_address"
+ internal="reg_stat_hdr_dat.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_clk"
+ internal="reg_stat_hdr_dat.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_read"
+ internal="reg_stat_hdr_dat.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_readdata"
+ internal="reg_stat_hdr_dat.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_reset"
+ internal="reg_stat_hdr_dat.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_write"
+ internal="reg_stat_hdr_dat.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_writedata"
+ internal="reg_stat_hdr_dat.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_unb_pmbus_address"
internal="reg_unb_pmbus.address"
@@ -3846,20 +4080,12 @@
<isStart>true</isStart>
<ports>
<port>
- <name>d_write</name>
- <role>write</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_debugaccess_to_roms</name>
- <role>debugaccess</role>
+ <name>d_address</name>
+ <role>address</role>
<direction>Output</direction>
- <width>1</width>
+ <width>19</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
<name>d_byteenable</name>
@@ -3870,17 +4096,17 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>d_readdata</name>
- <role>readdata</role>
- <direction>Input</direction>
- <width>32</width>
+ <name>d_read</name>
+ <role>read</role>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>d_writedata</name>
- <role>writedata</role>
- <direction>Output</direction>
+ <name>d_readdata</name>
+ <role>readdata</role>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -3894,21 +4120,29 @@
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>d_read</name>
- <role>read</role>
+ <name>d_write</name>
+ <role>write</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>d_address</name>
- <role>address</role>
+ <name>d_writedata</name>
+ <role>writedata</role>
<direction>Output</direction>
- <width>19</width>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
+ <port>
+ <name>debug_mem_slave_debugaccess_to_roms</name>
+ <role>debugaccess</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
</ports>
<assignments>
<assignmentValueMap>
@@ -4064,20 +4298,20 @@
<isStart>false</isStart>
<ports>
<port>
- <name>debug_mem_slave_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
+ <name>debug_mem_slave_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>9</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>debug_mem_slave_write</name>
- <role>write</role>
+ <name>debug_mem_slave_byteenable</name>
+ <role>byteenable</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
<name>debug_mem_slave_debugaccess</name>
@@ -4088,12 +4322,12 @@
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>debug_mem_slave_address</name>
- <role>address</role>
+ <name>debug_mem_slave_read</name>
+ <role>read</role>
<direction>Input</direction>
- <width>9</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
<name>debug_mem_slave_readdata</name>
@@ -4104,26 +4338,26 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>debug_mem_slave_read</name>
- <role>read</role>
- <direction>Input</direction>
+ <name>debug_mem_slave_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>debug_mem_slave_writedata</name>
- <role>writedata</role>
+ <name>debug_mem_slave_write</name>
+ <role>write</role>
<direction>Input</direction>
- <width>32</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>debug_mem_slave_byteenable</name>
- <role>byteenable</role>
+ <name>debug_mem_slave_writedata</name>
+ <role>writedata</role>
<direction>Input</direction>
- <width>4</width>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -4367,12 +4601,12 @@
<isStart>true</isStart>
<ports>
<port>
- <name>i_waitrequest</name>
- <role>waitrequest</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>i_address</name>
+ <role>address</role>
+ <direction>Output</direction>
+ <width>18</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
<name>i_read</name>
@@ -4391,12 +4625,12 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>i_address</name>
- <role>address</role>
- <direction>Output</direction>
- <width>18</width>
+ <name>i_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -4589,16 +4823,16 @@
<isStart>false</isStart>
<ports>
<port>
- <name>reset_req</name>
- <role>reset_req</role>
+ <name>reset_n</name>
+ <role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>reset_n</name>
- <role>reset_n</role>
+ <name>reset_req</name>
+ <role>reset_req</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -4938,7 +5172,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x300' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3200' end='0x3240' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3240' end='0x3260' datawidth='32' /><slave name='reg_epcs.mem' start='0x3260' end='0x3280' datawidth='32' /><slave name='reg_remu.mem' start='0x3280' end='0x32A0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x32A0' end='0x32B0' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x32B0' end='0x32C0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x32C0' end='0x32C8' datawidth='32' /><slave name='reg_si.mem' start='0x32C8' end='0x32D0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x32D0' end='0x32D8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x32D8' end='0x32E0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x32E0' end='0x32E8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x32E8' end='0x32F0' datawidth='32' /><slave name='pio_pps.mem' start='0x32F0' end='0x32F8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x32F8' end='0x3300' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='jesd204b.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_wg.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x40000' end='0x50000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x50000' end='0x60000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x70000' end='0x78000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0x78000' end='0x7A000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x7A000' end='0x7B000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_wg.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x300' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3300' end='0x3340' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3340' end='0x3380' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3380' end='0x33A0' datawidth='32' /><slave name='reg_epcs.mem' start='0x33A0' end='0x33C0' datawidth='32' /><slave name='reg_remu.mem' start='0x33C0' end='0x33E0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x33E0' end='0x33F0' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x33F0' end='0x3400' datawidth='32' /><slave name='reg_stat_enable.mem' start='0x3400' end='0x3408' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3408' end='0x3410' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3410' end='0x3418' datawidth='32' /><slave name='reg_si.mem' start='0x3418' end='0x3420' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3420' end='0x3428' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3428' end='0x3430' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3430' end='0x3438' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3438' end='0x3440' datawidth='32' /><slave name='pio_pps.mem' start='0x3440' end='0x3448' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3448' end='0x3450' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='jesd204b.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_wg.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x40000' end='0x50000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x50000' end='0x60000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x70000' end='0x78000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0x78000' end='0x7A000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x7A000' end='0x7B000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -6949,7 +7183,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="pio_pps"
+ name="pio_jesd_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -7535,37 +7769,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_pio_pps</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="pio_system_info"
+ name="pio_pps"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -7581,7 +7815,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -7645,7 +7879,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -7714,7 +7948,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -8120,11 +8354,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -8151,37 +8385,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_pio_system_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_pio_pps</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="pio_wdi"
+ name="pio_system_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -8189,17 +8423,17 @@
<boundary>
<interfaces>
<interface>
- <name>clk</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -8208,26 +8442,25 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>external_connection</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>out_port</name>
+ <name>coe_clk_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -8254,58 +8487,28 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s1</name>
+ <name>mem</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
- <name>address</name>
+ <name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>write_n</name>
- <role>write_n</role>
+ <name>avs_mem_write</name>
+ <role>write</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>writedata</name>
+ <name>avs_mem_writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
@@ -8313,15 +8516,15 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>chipselect</name>
- <role>chipselect</role>
+ <name>avs_mem_read</name>
+ <role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>readdata</name>
+ <name>avs_mem_readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
@@ -8353,7 +8556,7 @@
<parameterValueMap>
<entry>
<key>addressAlignment</key>
- <value>NATIVE</value>
+ <value>DYNAMIC</value>
</entry>
<entry>
<key>addressGroup</key>
@@ -8361,7 +8564,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>4</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -8373,11 +8576,11 @@
</entry>
<entry>
<key>associatedClock</key>
- <value>clk</value>
+ <value>system</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>reset</value>
+ <value>system_reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
@@ -8464,15 +8667,15 @@
</entry>
<entry>
<key>readLatency</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>readWaitStates</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>readWaitTime</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
@@ -8516,88 +8719,735 @@
</entry>
</parameterValueMap>
</parameters>
- <cmsisInfo>
- <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
-<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
- <peripherals>
- <peripheral>
- <name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>32</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>DATA</name>
- <displayName>Data</displayName>
- <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
- <addressOffset>0x0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>data</name>
- <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>DIRECTION</name>
- <displayName>Direction</displayName>
- <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>direction</name>
- <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>IRQ_MASK</name>
- <displayName>Interrupt mask</displayName>
- <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>interruptmask</name>
- <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>EDGE_CAP</name>
- <displayName>Edge capture</displayName>
- <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
- <addressOffset>0xc</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>edgecapture</name>
- <description>Edge detection for each input port.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>7</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_pio_system_info</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="pio_wdi"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>external_connection</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>out_port</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>s1</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>write_n</name>
+ <role>write_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>chipselect</name>
+ <role>chipselect</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>NATIVE</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>4</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ <cmsisInfo>
+ <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
+ <peripherals>
+ <peripheral>
+ <name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>32</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>DATA</name>
+ <displayName>Data</displayName>
+ <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
+ <addressOffset>0x0</addressOffset>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <resetMask>0xffffffff</resetMask>
+ <fields>
+ <field><name>data</name>
+ <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
+ <bitOffset>0x0</bitOffset>
+ <bitWidth>32</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DIRECTION</name>
+ <displayName>Direction</displayName>
+ <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
+ <addressOffset>0x4</addressOffset>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <resetMask>0xffffffff</resetMask>
+ <fields>
+ <field><name>direction</name>
+ <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
+ <bitOffset>0x0</bitOffset>
+ <bitWidth>32</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IRQ_MASK</name>
+ <displayName>Interrupt mask</displayName>
+ <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
+ <addressOffset>0x8</addressOffset>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <resetMask>0xffffffff</resetMask>
+ <fields>
+ <field><name>interruptmask</name>
+ <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
+ <bitOffset>0x0</bitOffset>
+ <bitWidth>32</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EDGE_CAP</name>
+ <displayName>Edge capture</displayName>
+ <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
+ <addressOffset>0xc</addressOffset>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <resetMask>0xffffffff</resetMask>
+ <fields>
+ <field><name>edgecapture</name>
+ <description>Edge detection for each input port.</description>
+ <bitOffset>0x0</bitOffset>
+ <bitWidth>32</bitWidth>
+ <access>read-write</access>
+ </field>
</fields>
</register>
<register>
@@ -8647,17 +9497,1942 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>altera_avalon_pio</className>
- <version>18.0</version>
- <displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
+ <className>altera_avalon_pio</className>
+ <version>18.0</version>
+ <displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>0</parameterDefaultValue>
+ <parameterName>clockRate</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>clk</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>clk</key>
+ <value>
+ <connectionPointName>clk</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>s1</key>
+ <value>
+ <connectionPointName>s1</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>4</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_pio_wdi</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.CAPTURE</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.DATA_WIDTH</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.EDGE_TYPE</key>
+ <value>NONE</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.FREQ</key>
+ <value>100000000</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.HAS_IN</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.HAS_OUT</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.HAS_TRI</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.IRQ_TYPE</key>
+ <value>NONE</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.CMacro.RESET_VALUE</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.compatible</key>
+ <value>altr,pio-1.0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.group</key>
+ <value>gpio</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.name</key>
+ <value>pio</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.params.altr,gpio-bank-width</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.params.resetvalue</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.vendor</key>
+ <value>altr</value>
+ </entry>
+ </assignmentValueMap>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="ram_aduh_monitor"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32768</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>15</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="ram_diag_data_buf_bsn"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>65536</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="ram_diag_data_buf_jesd"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>11</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>11</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8192</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
- <parameterDefaultValue>0</parameterDefaultValue>
- <parameterName>clockRate</parameterName>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
<parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>clk</systemInfoArgs>
+ <systemInfoArgs>system</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
</descriptors>
@@ -8665,30 +11440,17 @@
<systemInfos>
<connPtSystemInfos>
<entry>
- <key>clk</key>
- <value>
- <connectionPointName>clk</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>s1</key>
+ <key>mem</key>
<value>
- <connectionPointName>s1</connectionPointName>
+ <connectionPointName>mem</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x2000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>13</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -8698,118 +11460,54 @@
<consumedSystemInfos/>
</value>
</entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_pio_wdi</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.CAPTURE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.DATA_WIDTH</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.EDGE_TYPE</key>
- <value>NONE</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.FREQ</key>
- <value>100000000</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.HAS_IN</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.HAS_OUT</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.HAS_TRI</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.IRQ_TYPE</key>
- <value>NONE</value>
- </entry>
- <entry>
- <key>embeddedsw.CMacro.RESET_VALUE</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.compatible</key>
- <value>altr,pio-1.0</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.group</key>
- <value>gpio</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.name</key>
- <value>pio</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.params.altr,gpio-bank-width</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.params.resetvalue</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.dts.vendor</key>
- <value>altr</value>
- </entry>
- </assignmentValueMap>
+ <assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_aduh_monitor"
+ name="ram_equalizer_gains"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -9395,37 +12093,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_diag_data_buf_bsn"
+ name="ram_fil_coefs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -10011,37 +12709,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_fil_coefs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_fil_coefs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_fil_coefs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_fil_coefs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_fil_coefs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_diag_data_buf_jesd"
+ name="ram_scrap"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -10057,7 +12755,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>11</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -10121,7 +12819,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>11</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -10190,7 +12888,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8192</value>
+ <value>2048</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -10596,11 +13294,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x2000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>13</value>
+ <value>11</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -10627,37 +13325,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_scrap</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_scrap</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_scrap.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_equalizer_gains"
+ name="ram_st_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -10673,7 +13371,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -10737,7 +13435,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -10806,7 +13504,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -11212,11 +13910,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -11243,37 +13941,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_st_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_st_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_st_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_fil_coefs"
+ name="ram_wg"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -11859,37 +14557,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_fil_coefs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_wg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_fil_coefs.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_scrap"
+ name="reg_aduh_monitor"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -11905,7 +14603,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>9</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -11969,7 +14667,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>9</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12038,7 +14736,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>2048</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -12444,11 +15142,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>11</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -12475,37 +15173,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_scrap</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_aduh_monitor</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_scrap.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_aduh_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_sst"
+ name="reg_bsn_monitor_input"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -12521,7 +15219,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12585,7 +15283,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12654,7 +15352,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -13060,11 +15758,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -13091,37 +15789,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_st_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_st_sst.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_wg"
+ name="reg_bsn_scheduler"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -13137,7 +15835,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13201,7 +15899,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13270,7 +15968,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -13676,11 +16374,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -13707,37 +16405,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_ram_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_wg.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_aduh_monitor"
+ name="reg_bsn_source"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -13753,7 +16451,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13817,7 +16515,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13886,7 +16584,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -14292,11 +16990,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -14323,37 +17021,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_aduh_monitor</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_bsn_source</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_source</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_source</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_source</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_source.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_input"
+ name="reg_diag_data_buf_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14369,7 +17067,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14433,7 +17131,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14502,7 +17200,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -14908,11 +17606,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -14939,37 +17637,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_diag_data_buf_jesd"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14985,7 +17683,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15049,7 +17747,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15118,7 +17816,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15524,11 +18222,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15555,37 +18253,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_source"
+ name="reg_dp_selector"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15601,7 +18299,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15665,7 +18363,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15734,7 +18432,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -16140,11 +18838,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -16171,37 +18869,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_bsn_source</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_dp_selector</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dp_selector</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_source.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_selector.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buf_bsn"
+ name="reg_dp_shiftram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16787,37 +19485,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_dp_shiftram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_shiftram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buf_jesd"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16833,7 +19531,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16897,7 +19595,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16966,7 +19664,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17372,11 +20070,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17403,37 +20101,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_selector"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18019,37 +20717,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_dp_selector</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_selector.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_shiftram"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18065,7 +20763,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18129,7 +20827,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18198,7 +20896,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18604,11 +21302,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18635,37 +21333,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_dp_shiftram</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_shiftram.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18681,7 +21379,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18745,7 +21443,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18814,7 +21512,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -19220,11 +21918,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19251,37 +21949,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19297,7 +21995,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19361,7 +22059,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19430,7 +22128,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -19836,11 +22534,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19867,37 +22565,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19913,7 +22611,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19977,7 +22675,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20046,7 +22744,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20452,11 +23150,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20483,37 +23181,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20529,7 +23227,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20593,7 +23291,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20662,7 +23360,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21068,11 +23766,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21099,37 +23797,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21145,7 +23843,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21209,7 +23907,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21278,7 +23976,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21684,11 +24382,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21715,37 +24413,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_sdp_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21761,7 +24459,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21825,7 +24523,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21894,7 +24592,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -22300,11 +24998,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22331,37 +25029,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_sdp_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_sdp_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_sdp_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_si"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22947,37 +25645,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_si</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_si</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_si</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_si</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_si.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_stat_enable"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22993,7 +25691,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23057,7 +25755,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23126,7 +25824,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -23532,11 +26230,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23563,37 +26261,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_stat_enable</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_stat_enable</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_stat_enable</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_stat_enable</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_stat_enable</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_stat_enable</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_stat_enable</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_enable.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_si"
+ name="reg_stat_hdr_dat"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23609,7 +26307,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23673,7 +26371,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23742,7 +26440,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24148,11 +26846,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24179,30 +26877,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_si</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_si.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -28017,7 +30715,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x32f8" />
+ <parameter name="baseAddress" value="0x3448" />
</connection>
<connection
kind="avalon"
@@ -28031,7 +30729,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_unb_sens.mem">
- <parameter name="baseAddress" value="0x3100" />
+ <parameter name="baseAddress" value="0x3200" />
</connection>
<connection
kind="avalon"
@@ -28052,7 +30750,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x32f0" />
+ <parameter name="baseAddress" value="0x3440" />
</connection>
<connection
kind="avalon"
@@ -28066,63 +30764,63 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x3280" />
+ <parameter name="baseAddress" value="0x33c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x3260" />
+ <parameter name="baseAddress" value="0x33a0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x32e8" />
+ <parameter name="baseAddress" value="0x3438" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x32e0" />
+ <parameter name="baseAddress" value="0x3430" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x32d8" />
+ <parameter name="baseAddress" value="0x3428" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x32d0" />
+ <parameter name="baseAddress" value="0x3420" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x3240" />
+ <parameter name="baseAddress" value="0x3380" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_unb_pmbus.mem">
- <parameter name="baseAddress" value="0x0300" />
+ <parameter name="baseAddress" value="0x3100" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="baseAddress" value="0x3200" />
+ <parameter name="baseAddress" value="0x3340" />
</connection>
<connection
kind="avalon"
@@ -28136,7 +30834,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x32c8" />
+ <parameter name="baseAddress" value="0x3418" />
</connection>
<connection
kind="avalon"
@@ -28164,7 +30862,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_diag_data_buf_jesd.mem">
- <parameter name="baseAddress" value="0x32b0" />
+ <parameter name="baseAddress" value="0x33f0" />
</connection>
<connection
kind="avalon"
@@ -28178,7 +30876,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_aduh_monitor.mem">
- <parameter name="baseAddress" value="0x0200" />
+ <parameter name="baseAddress" value="0x0300" />
</connection>
<connection
kind="avalon"
@@ -28213,21 +30911,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x32c0" />
+ <parameter name="baseAddress" value="0x3410" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_source.mem">
- <parameter name="baseAddress" value="0x32a0" />
+ <parameter name="baseAddress" value="0x33e0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_wg.mem">
- <parameter name="baseAddress" value="0x0100" />
+ <parameter name="baseAddress" value="0x0200" />
</connection>
<connection
kind="avalon"
@@ -28248,7 +30946,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x3008" />
+ <parameter name="baseAddress" value="0x3408" />
</connection>
<connection
kind="avalon"
@@ -28257,6 +30955,34 @@
end="ram_equalizer_gains.mem">
<parameter name="baseAddress" value="0x8000" />
</connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_sdp_info.mem">
+ <parameter name="baseAddress" value="0x3300" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_stat_enable.mem">
+ <parameter name="baseAddress" value="0x3400" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_stat_hdr_dat.mem">
+ <parameter name="baseAddress" value="0x0100" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="pio_jesd_ctrl.mem">
+ <parameter name="baseAddress" value="0x3008" />
+ </connection>
<connection
kind="avalon"
version="18.0"
@@ -28448,6 +31174,26 @@
version="18.0"
start="clk_0.clk"
end="ram_equalizer_gains.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_sdp_info.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_stat_enable.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_stat_hdr_dat.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="pio_jesd_ctrl.system" />
<connection
kind="interrupt"
version="18.0"
@@ -28654,6 +31400,26 @@
version="18.0"
start="clk_0.clk_reset"
end="ram_equalizer_gains.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_sdp_info.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_stat_enable.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_stat_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="pio_jesd_ctrl.system_reset" />
<connection
kind="reset"
version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/hdllib.cfg
index 18b472ec840d3bcdee6203e397c54b81da522337..755479f56e47802b1b991541f5842c8daf91d483 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/hdllib.cfg
@@ -84,5 +84,9 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wg.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_timer_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_sdp_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_enable.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
index 1587113a05f4fe345479a2b8195cf5c79668965b..1ad3eb3ae671b261e13c3980fbf478f6203b54eb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
@@ -26,11 +26,12 @@
-- Unb2b version for lab testing
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, eth_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
@@ -39,6 +40,7 @@ USE dp_lib.dp_stream_pkg.ALL;
USE wpfb_lib.wpfb_pkg.ALL;
USE lofar2_sdp_lib.sdp_pkg.ALL;
USE work.lofar2_unb2b_filterbank_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
ENTITY lofar2_unb2b_filterbank IS
GENERIC (
@@ -111,6 +113,13 @@ ARCHITECTURE str OF lofar2_unb2b_filterbank IS
CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS
+ CONSTANT c_udp_offload_nof_streams : NATURAL := c_eth_nof_udp_ports;
+
+ -- Read only sdp_info values
+ CONSTANT c_f_adc : STD_LOGIC := '1'; -- '0' => 160M, '1' => 200M
+ CONSTANT c_fsub_type : STD_LOGIC := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
+ SIGNAL gn_index : NATURAL := 0;
+
-- System
SIGNAL cs_sim : STD_LOGIC;
SIGNAL xo_ethclk : STD_LOGIC;
@@ -252,13 +261,43 @@ ARCHITECTURE str OF lofar2_unb2b_filterbank IS
SIGNAL ram_scrap_mosi : t_mem_mosi;
SIGNAL ram_scrap_miso : t_mem_miso;
+ -- SDP Info
+ SIGNAL reg_sdp_info_mosi : t_mem_mosi;
+ SIGNAL reg_sdp_info_miso : t_mem_miso;
+
+ -- Statistics Enable
+ SIGNAL reg_stat_enable_mosi : t_mem_mosi;
+ SIGNAL reg_stat_enable_miso : t_mem_miso;
+
+ -- Statistics header info
+ SIGNAL reg_stat_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_stat_hdr_dat_miso : t_mem_miso;
+
+ -- Statistics ??
+ SIGNAL id_backplane : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+ SIGNAL id_chip : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+
+ SIGNAL udp_tx_sosi_arr : t_dp_sosi_arr(c_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+ SIGNAL udp_tx_siso_arr : t_dp_siso_arr(c_udp_offload_nof_streams-1 DOWNTO 0);
+
+ SIGNAL eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ SIGNAL ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ SIGNAL udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+
+ SIGNAL sdp_info : t_sdp_info := c_sdp_info_rst;
+
+
-- QSFP leds
SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
SIGNAL ait_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
- SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+
+ -- JESD control
+ SIGNAL jesd_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL jesd_ctrl_miso : t_mem_miso := c_mem_miso_rst;
BEGIN
@@ -267,21 +306,23 @@ BEGIN
-----------------------------------------------------------------------------
u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
GENERIC MAP (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_dp_clk_freq,
- g_dp_clk_use_pll => FALSE
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_dp_clk_freq,
+ g_dp_clk_use_pll => FALSE,
+ g_udp_offload => TRUE,
+ g_udp_offload_nof_streams => c_eth_nof_udp_ports
)
PORT MAP (
-- Clock an reset signals
@@ -360,6 +401,10 @@ BEGIN
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
+ -- eth1g UDP streaming
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
ram_scrap_mosi => ram_scrap_mosi,
ram_scrap_miso => ram_scrap_miso,
@@ -481,7 +526,19 @@ BEGIN
reg_dp_selector_mosi => reg_dp_selector_mosi,
reg_dp_selector_miso => reg_dp_selector_miso,
ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- Jesd reset control
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Statistics offload
+ reg_sdp_info_mosi => reg_sdp_info_mosi,
+ reg_sdp_info_miso => reg_sdp_info_miso,
+ reg_stat_enable_mosi => reg_stat_enable_mosi,
+ reg_stat_enable_miso => reg_stat_enable_miso,
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_miso
);
@@ -531,6 +588,8 @@ BEGIN
ram_aduh_monitor_miso => ram_aduh_monitor_miso,
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
-- Jesd external IOs
jesd204b_serial_data => JESD204B_SERIAL_DATA,
@@ -542,6 +601,40 @@ BEGIN
out_sosi_arr => ait_sosi_arr
);
+ -----------------------------------------------------------------------------
+ -- SDP Info register
+ -----------------------------------------------------------------------------
+ gn_index <= TO_UINT(ID(c_sdp_W_gn_id-1 DOWNTO 0));
+
+ u_sdp_info : ENTITY lofar2_sdp_lib.sdp_info
+ PORT MAP(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
+
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
+
+ -- sdp info
+ sdp_info => sdp_info
+ );
+
+ -- derive MAC, IP and UDP Port from ID
+ id_backplane <= RESIZE_UVEC(ID(c_sdp_W_gn_id-1 DOWNTO 2), c_byte_w);
+ id_chip <= RESIZE_UVEC(ID(1 DOWNTO 0), c_byte_w); -- Unb2 has 4 FPGA chips
+
+ -- The eth_src_mac and ip_src_addr for SST offload are the same as for M&C, because they share the same 1GbE interface
+ eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & id_backplane & id_chip;
+ ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & id_backplane & INCR_UVEC(id_chip, 1); -- +1, because IP address must be > 0
+ udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
u_fsub : ENTITY lofar2_sdp_lib.node_sdp_filterbank
GENERIC MAP(
@@ -550,26 +643,41 @@ BEGIN
g_scope_selected_subband => g_scope_selected_subband
)
PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- in_sosi_arr => ait_sosi_arr,
+ in_sosi_arr => ait_sosi_arr,
pfb_sosi_arr => pfb_sosi_arr,
fsub_sosi_arr => fsub_sosi_arr,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso,
+
+ reg_enable_mosi => reg_stat_enable_mosi,
+ reg_enable_miso => reg_stat_enable_miso,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
+
+ sdp_info => sdp_info,
+ gn_id => ID(c_sdp_W_gn_id-1 DOWNTO 0),
+
+ eth_src_mac => eth_src_mac,
+ ip_src_addr => ip_src_addr,
+ udp_src_port => udp_src_port
);
END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
index c5d41e715e106ea1755254a189fd801d0dae509e..5c98a6406407f62ac0b85082e0cf55399565f7da 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
@@ -102,6 +102,10 @@ ENTITY mmm_lofar2_unb2b_filterbank IS
jesd204b_mosi : OUT t_mem_mosi;
jesd204b_miso : IN t_mem_miso;
+ -- Jesd reset control
+ jesd_ctrl_mosi : OUT t_mem_mosi;
+ jesd_ctrl_miso : IN t_mem_miso;
+
-- Dp shiftram
reg_dp_shiftram_mosi : OUT t_mem_mosi;
reg_dp_shiftram_miso : IN t_mem_miso;
@@ -154,17 +158,29 @@ ENTITY mmm_lofar2_unb2b_filterbank IS
reg_si_mosi : OUT t_mem_mosi;
reg_si_miso : IN t_mem_miso;
- -- Equalizer gains
- ram_equalizer_gains_mosi : OUT t_mem_mosi;
- ram_equalizer_gains_miso : IN t_mem_miso;
+ -- Equalizer gains
+ ram_equalizer_gains_mosi : OUT t_mem_mosi;
+ ram_equalizer_gains_miso : IN t_mem_miso;
- -- DP Selector
- reg_dp_selector_mosi : OUT t_mem_mosi;
- reg_dp_selector_miso : IN t_mem_miso;
+ -- DP Selector
+ reg_dp_selector_mosi : OUT t_mem_mosi;
+ reg_dp_selector_miso : IN t_mem_miso;
-- Scrap ram
ram_scrap_mosi : OUT t_mem_mosi;
- ram_scrap_miso : IN t_mem_miso
+ ram_scrap_miso : IN t_mem_miso;
+
+ -- SDP info
+ reg_sdp_info_mosi : OUT t_mem_mosi;
+ reg_sdp_info_miso : IN t_mem_miso;
+
+ -- Statistics enable
+ reg_stat_enable_mosi : OUT t_mem_mosi;
+ reg_stat_enable_miso : IN t_mem_miso;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_mosi : OUT t_mem_mosi;
+ reg_stat_hdr_dat_miso : IN t_mem_miso
);
END mmm_lofar2_unb2b_filterbank;
@@ -263,6 +279,16 @@ BEGIN
u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
PORT MAP(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+
+ u_mm_file_reg_sdp_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+ PORT MAP(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+
+ u_mm_file_reg_stat_enable : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE")
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_mosi, reg_stat_enable_miso );
+
+ u_mm_file_reg_stat_hdr_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_INFO")
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_mosi, reg_stat_hdr_dat_miso);
+
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -389,6 +415,14 @@ BEGIN
jesd204b_read_export => jesd204b_mosi.rd,
jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_jesd_ctrl_reset_export => OPEN,
+ pio_jesd_ctrl_clk_export => OPEN,
+ pio_jesd_ctrl_address_export => jesd_ctrl_mosi.address(0 downto 0),
+ pio_jesd_ctrl_write_export => jesd_ctrl_mosi.wr,
+ pio_jesd_ctrl_writedata_export => jesd_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_jesd_ctrl_read_export => jesd_ctrl_mosi.rd,
+ pio_jesd_ctrl_readdata_export => jesd_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+
reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(c_sdp_reg_bsn_monitor_input_addr_w-1 DOWNTO 0),
reg_bsn_monitor_input_clk_export => OPEN,
reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
@@ -565,7 +599,31 @@ BEGIN
ram_scrap_write_export => ram_scrap_mosi.wr,
ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_scrap_read_export => ram_scrap_mosi.rd,
- ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w-1 DOWNTO 0)
+ ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_sdp_info_clk_export => OPEN,
+ reg_sdp_info_reset_export => OPEN,
+ reg_sdp_info_address_export => reg_sdp_info_mosi.address(c_sdp_reg_sdp_info_addr_w-1 DOWNTO 0),
+ reg_sdp_info_write_export => reg_sdp_info_mosi.wr,
+ reg_sdp_info_writedata_export => reg_sdp_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_sdp_info_read_export => reg_sdp_info_mosi.rd,
+ reg_sdp_info_readdata_export => reg_sdp_info_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_stat_enable_clk_export => OPEN,
+ reg_stat_enable_reset_export => OPEN,
+ reg_stat_enable_address_export => reg_stat_enable_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+ reg_stat_enable_write_export => reg_stat_enable_mosi.wr,
+ reg_stat_enable_writedata_export => reg_stat_enable_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_read_export => reg_stat_enable_mosi.rd,
+ reg_stat_enable_readdata_export => reg_stat_enable_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_stat_hdr_dat_clk_export => OPEN,
+ reg_stat_hdr_dat_reset_export => OPEN,
+ reg_stat_hdr_dat_address_export => reg_stat_hdr_dat_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_write_export => reg_stat_hdr_dat_mosi.wr,
+ reg_stat_hdr_dat_writedata_export => reg_stat_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_read_export => reg_stat_hdr_dat_mosi.rd,
+ reg_stat_hdr_dat_readdata_export => reg_stat_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
index abe9daa6f4630121a4ec1292bb631445dd418bfc..e15bdce19d10082f87dd9c41060afeb367a6f36d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
@@ -126,6 +126,29 @@ PACKAGE qsys_lofar2_unb2b_filterbank_pkg IS
ram_wg_reset_export : out std_logic; -- export
ram_wg_write_export : out std_logic; -- export
ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_clk_export : out std_logic; -- export
+ reg_stat_enable_read_export : out std_logic; -- export
+ reg_stat_enable_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_reset_export : out std_logic; -- export
+ reg_stat_enable_write_export : out std_logic; -- export
+ reg_stat_enable_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+
reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
reg_aduh_monitor_clk_export : out std_logic; -- export
reg_aduh_monitor_read_export : out std_logic; -- export
@@ -133,6 +156,7 @@ PACKAGE qsys_lofar2_unb2b_filterbank_pkg IS
reg_aduh_monitor_reset_export : out std_logic; -- export
reg_aduh_monitor_write_export : out std_logic; -- export
reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+
reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
reg_bsn_monitor_input_clk_export : out std_logic; -- export
reg_bsn_monitor_input_read_export : out std_logic; -- export
@@ -280,7 +304,14 @@ PACKAGE qsys_lofar2_unb2b_filterbank_pkg IS
rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
rom_system_info_reset_export : out std_logic; -- export
rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
);
end component qsys_lofar2_unb2b_filterbank;
END qsys_lofar2_unb2b_filterbank_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
index 0bf899960c69d62bae6140cb5b4111254ba47a84..5d34c3b1694a0e9606596ca41a80c1b08af62206 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
@@ -195,7 +195,7 @@ BEGIN
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
- proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+ proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
jesd204b_sysref <= pps;
ext_pps <= pps;
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_deliverables.txt b/applications/lofar2/doc/prestudy/station2_sdp_deliverables.txt
old mode 100755
new mode 100644
index ca85b6f5912606001bc5c41916cec10bf80efac5..0f084180c7f642469f0c412f22a300976b6b827a
--- a/applications/lofar2/doc/prestudy/station2_sdp_deliverables.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_deliverables.txt
@@ -1,7 +1,7 @@
D1 UniBoard2 Detailed Design document
D2 Gemini LRU board for initial SW M&C tests
D3 unb2c_test_pinning (using 10GbE)
-D4 unb2c_test_pinning_jesd (using JESD204b) ~= lofar2_unb2b_adc_one_node
+D4 unb2c_test_pinning_jesd (using JESD204b)
D5 unb2c_heater (verify speed grade)
D6 unb2c_test_ddr4 (both slots)
D7 unb2c_test_10GbE (QSFP + ring, back)
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt b/applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt
index 23e42f2222f0ff7f13498e0379653226d608b337..d38353335ce8115ac49306e2f0e667cd1c4eff71 100755
--- a/applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt
@@ -2,8 +2,8 @@
* Rules
*******************************************************************************
-1) Continuously plan increment of 4 sprints (= 1 increment) ahead
- After initial planning for the whole project (at PDR) it remains necessary
+1) Continuously plan increment of 4 sprint ahead
+ After initial planning for thge whole project (at PDR) it remains necessary
to keep on adapting / fine tuning the planning per quarter, so about 4
sprints ahead. This concerns not only time but also expectations, interfaces
and work
@@ -51,7 +51,7 @@ This then means that with the SDP work starting 1 jan 2020 it can complete mid
1) Lab Test Station (LTS) - First-light Mai 2020
Objectives: Verification of (parts of) individyual elements and their
interfaces
-- 1 UniBoard2b Rev 2 (use different FPGA on same UniBoard for FW, SW tests)
+- 1 UniBoard2 Rev 2 (use different FPGA on same UniBoard for FW, SW tests)
Setups for:
- SW
- FW
@@ -63,7 +63,7 @@ Setups for:
Objectives: Verify that a complete signal chain using the first iteration of
L3 hardware design shows no serious issues and that it can be
reliably installed in a LOFAR station.
-- 1 UniBoard2c Rev 3a
+- 1 UniBoard2 Rev 2
- First iteration of electronic boards --> 2 UniBoard2 Rev 3a
3) Prototype Test Station (PTS) - First-light Mai 2021
@@ -71,7 +71,7 @@ Objectives: Verify Station L2 requirements through testing and analysis, and
provide evidence to the CDR review panel that the designs ensure
compliance with all L2 requirements.
- Second iteration of electronic boards --> 4 UniBoard2 Rev 3b
-- 4 UniBoard2c Rev 3b in two subracks (one for LBA with 32 RCU2, one for HBA
+- 4 UniBoard2 Rev 3b in two subracks (one for LBA with 32 RCU2, one for HBA
with 32 RCU2)
- Output to CEP for correlation with other stations
@@ -586,11 +586,7 @@ all 12-2021 CDR M Complete SDP document package for Station CDR
So the difference is -10 weeks, which means that the 2019 PDR is about -10
/ 230 = 5 % more time then the 2018 AAD estimate.
-- 2020-jul
- Planning differences occur due to:
- - pre PDR work was not budgetted (L2 Station work)
- - SC-SDP Translator work was not budgetted
-
+
*******************************************************************************
* SDP effort estimates in LOFAR2.0 Station WP5 (since jan 2020)
*
@@ -621,204 +617,234 @@ all 12-2021 CDR M Complete SDP document package for Station CDR
20 800 - T5.14 Station test and verification after CDR (using
unb2c_sdp_station)
-
*******************************************************************************
-* Notes
+* Q1 = Increment 1 Lab Test Station (LTS)
*******************************************************************************
-1) Nof UniBoard2 per subrack (15 dec 2020)
-
-Wim van Cappellen: 10:14 AM
-Stel dat we 1 Uniboard per subrack doen (ben ik geen voorstander van, maar stel...), zouden we dan nog AARTFAAC kunnen doen?
-
-Eric Kooistra 8:42 AM
-Op basis van conclusie in https://support.astron.nl/confluence/display/L2M/L2+STAT+Decision%3A+Number+of+UniBoard2+per+subrack: Waarschijnlijk zal subband offload voor AARTFAAC nog wel passen, samen met de beamformer en de subband correlator. Het transient buffer wordt ook zonder AARTFAAC al moeilijk. De bottleneck zit in de hoeveelheid beschikbare RAM in de FPGA per ADC signal input.
-New
-
-Wim van Cappellen: 8:59 AM
-Bedankt. Durf jij je hand ervoor in het voor te steken dat als we de transient buffer nu niet doen (die kant gaat het wel op), �n slechts 1 UB per subrack hebben, de stations nog wel AARTFAAC data kunnen leveren?
-
-Eric Kooistra 9:13 AM
-Ja ik denk dat beamformer + subband correlator + AARTFAAC wel zal passen in optie B. Echter de FPGAs zijn dan voller en gaan mogelijk teveel power nemen en dat wordt dan ook een risk (zie sectie 3.5 in design decision doc). Kunnen we niet wachten tot CDR met deze beslissing, dan hebben we meetgegevens, dat was het idee van optie C die we gekozen hebben. Als je nu al optie B kiest, dan kan transient buffer misschien nooit niet (zie sectie 3.4.1). De onzekerheid komt doordat ik geen goede resource estimates van TBB in LOFAR1 heb.
-
-
-2) Test cases (15 dec 2020)
-
-Mark Ruiter:house_with_garden: 2:35 PM
-Hoi, Zou je de tests aan lts kunnen toevoegen bij: https://support.astron.nl/confluence/display/L2M/LTS+Measurement+Journal
-
-Eric Kooistra 9:25 AM
-Leon doet op het moment ADC - FPGA JESD interface stress tests met LTS. Is de bedoeling dat hij hiervan dan een logbook met test + meetresultaten bijhoud in Confluence?
-
-Mark Ruiter:house_with_garden: 10:09 AM
-Als ze belangrijk zijn voor ICD of terug gekoppeld moeten worden naar requirements dan graag.
-Ik wil graag kunnen zien hoever we zijn met testen van fpga firmware, en de resultaten bekijken.
-zodat we die aan de requirements in polarion kunnen linken.
-
-Eric Kooistra 1:05 PM
-Dit heb ik al qua test cases in Polarion: https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L3%20Station%20requirements/SDP%20Test%20Case%20Specification. De link met LTS is er echter nog niet. Dwz Leon werkt nog met eigen test scripts. De link tussen Polarion en echt doen van tests gaat dan via logbooks?
-
-Mark Ruiter:house_with_garden: 1:34 PM
-In Polarion is de LTS testrun gedefineerd door jouw: https://plm.astron.nl/polarion/#/project/LOFAR2System/workitems?query=TEST_RECORDS%3A(%2[?]2%2C%40null)&sidebar=testrun&testrun=LOFAR2System%2FLTS-1
-We willen weten of deze tests zijn gedaan en of ze succesvol waren.
-Dit doen we door de testrun te runnen en het resultaat en een link naar de meting toe te voegen:
-https://plm.astron.nl/polarion/#/project/LOFAR2System/testrun?id=LTS-1
-zo duidelijk?
-
-Eric Kooistra 1:40 PM
-Ja dit helpt. Ik zie dat we (SDP) de Test Steps nog in moeten vullen. Die Test Steps zijn dan bijvoorbeeld het runnen van een bepaald script of het doen van een bepaald commando?
-New
-
-Mark Ruiter:house_with_garden: 1:41 PM
-Ja, dat is voor nu een beetje te veel werk. Het is al goed als we weten welke tests gedaan zijn, welke nog moeten, welke issues hebben en nog werk nodig hebben. (edited)
-
-Eric Kooistra 1:47 PM
-Geen van de SDP Test cases is al compleet af. Leon werkt nu aan de ADC - FPGA JESD interface stress tests, als hij dat af heeft dan covered dat denk ik LOFAR2-8427, 8206, 7945.
-
-Eric Kooistra 12:42 PM
-Leon houdt voor ADC - FPGA JESD interface tests een meet logbook bij in: https://support.astron.nl/confluence/pages/viewpage.action?spaceKey=L2M&title=Testing+Notebook+Alignment
-
-*******************************************************************************
-* New sprint
-*******************************************************************************
-- how are you
-- retrospective last sprints
-- tasks for next sprint + availability
-- sprint goal (e.g. achieve some test case)
-
-
-
-
-
-*******************************************************************************
-* Bits & chips
-*******************************************************************************
-
-https://bits-chips.nl/artikel/engineering-the-corona-response/?utm_source=Bits%26Chips+newsletter&utm_campaign=fbb051f6dc-EMAIL_CAMPAIGN_2020_10_01_13%3A00&utm_medium=email&utm_term=0_cea2018fda-fbb051f6dc-322493781
-- Engineering Principle #1: define what you want to achieve (goal).
-- Engineering Principle #2: make a model of the process you want to control, based on what you see in the real world (keep SNR >> 10 dB, noise is added by fools).
-- Engineering Principle #3: understand the math (exponential growth, statistics are blind spot to most people, they understand the mean, but not much more).
-- Engineering principle #4: what you don?t measure, you can?t control. When you?ve devised a model, you can build a control system of your process by feeding back relevant measurements into your control loop. But there?s a pitfall: lag. When you drive a car with a blinded front window, using a video of the road from last week, everybody understands that you have to be very careful.
-Currently, we face a virus with an incubation period of six days and a test system that yields results after a few days. So the lag in the control system for the government is about two weeks: it takes two weeks before you measure the response of your control system. Thus, the corona dashboard shows the results of previous control actions. Good luck trying to develop an optimal control strategy from these figures!
-
-https://waitbutwhy.com/2015/01/artificial-intelligence-revolution-1.html
-
-
-https://bits-chips.nl/artikel/cracking-the-code-to-craftsmanship/?utm_source=Bits%26Chips+newsletter&utm_campaign=a67ee91488-EMAIL_CAMPAIGN_2020_09_08_13%3A00&utm_medium=email&utm_term=0_cea2018fda-a67ee91488-322493781
-
-
-*******************************************************************************
-* Time management
-*******************************************************************************
+Main deliverables
+- EK: D19/20 SDP design documents for LTS
+- EK: D41 ICD SC-SDP for unb2b_minimal_gp
+- JH: D25 unb2b_adc_full
+- PD: D11 unb2b_minimal_gp (= BSP)
+- LH: D42 SDP OPC-UA server prototype
+- RW: D10 10GbE arp, ping
+
+Planning per person:
+
+RW:
+ Q1: finish unb2c_network for 10GbE with ARP request and ping response on HW
+
+GS: unb2c
+ - Production package proto unb2c (D9)
+
+JH: ADC ingest and timing
+ sp1: finish unb2b_test_adc_one_node (D8,24) using revisions
+ . unb2b arria10 libraries working in simulation, including tech_jesd
+ sp2: unb2b_test_adc_full (D25), includes timing, DB, WG, statistics and M&C
+ sp3: lab test integration of unb2b_test_adc_full (D25)
+ sp4: finish unb2c pinning and heater designs (D3,4,5) for Uniboard2
+ production package (D9)
+
+PD: BSP (= unb2b_minimal_gp)
+ sp1: ARP and ping on unb2b HW + use VHDL MM bus
+ sp2: Add Gemini Protocol (GP) firmware and read version in simulation
+ sp3: Gemini Protocol (GP) on hardware (D11)
+ sp4: lab test integration of unb2b_minimal_gp (D11)
+
+EK: Designs Documentation
+ sp1: Design documents for SDP in confluence
+ . top level, timing and ADC
+ . BSP (= unb2b_minimal_gp)
+ . prestudy note on oversampled filterbank
+ sp2: Assist with new VHDL:
+ . BSN source with BSN offset
+ . synchronous SOSI reset
+ . ADC and processing clock domains
+ sp3: Design documents for SDP in confluence
+ . ring
+ . correlator
+ sp4: Prepare for Q2
+
+LH: SDP-OPC-UA server
+ sp1: Investigate M&C software from CSIRO. Describe MM map of unb2b_minimal_gp
+ in ARGS yaml.
+ sp2: Investigate representation of MM map in OPC-UA. Draft design for SDP
+ OPC-UA server
+ sp3: Prototype of SDP OPC-UA server
+ sp4: lab test integration of SDP OPC-UA server with unb2b_minimal_gp
+
+Other:
+- synchronous sosi reset
+- rename g_revision_id into g_stamp_revision (unb2b, unb2c) and add it to unb1
+- remove g_technology from unb2b board designs, rely on c_technology_default
+
+-------------------------------------------------------------------------------
+-- BSP Detailed planning:
+-------------------------------------------------------------------------------
+
+BSP - PD
+1) arp, ping
+- reply arp and ping in eth1g_master
+- pass on other traffic to external master
+==> working unb2b_arp_ping in simulation
+==> working unb2b_arp_ping on HW
+
+2) gp_master = gemini protocol master
+- create gp library
+- extract gemini protocol master (gp_master) from CSIRO at Rx/Tx packet
+ interface
+- simulate gp_master in tb_gp_master with rx MM request and tx MM response to
+ simulate a MM access via GP to a MM slave reg
+==> working gp_master with tb_gp_master in simulation
+- integrate gp_master + eth1g_master in mmm_unb2b_arp_ping_gp
+==> working unb2b_arp_ping_gp in simulation
+==> working unb2b_arp_ping_gp on HW
+
+3) unb2b_minimal_gp
+- create unb2b_minimal_gp design library (so not a revision of unb2b_minimal)
+- integrate MM bus
+- manually connect all ctrl_unb2b_minimal slaves to the MM bus
+==> working unb2b_minimal_gp in simulation (at least compile, load, run 1 us)
+==> working unb2b_minimal_gp on HW
+
+4) MM bus from YAML
+- use unb2b_minimal_gp reg map in YAML and use this to automaticly generate
+ mmm_<design_name> MM bus
+
+
+The SDP work of increment 1 is described in section 6.1 of:
+
+https://support.astron.nl/confluence/display/STAT/WP-5+SDP
+
+1) D25 unb2b_adc_full with the ADC input and timing section on UniBoard2
+
+Jira GS: prepare a second jesd_us2 ADC test board for the Lab Test Station
+Jira JH: finish unb2b_test_adc_one_node (D8,24) using revisions
+Jira JH: unb2b arria10 libraries working in simulation, including tech_jesd
+Jira JH: setup structure of unb2b_adc_full including timing, DB, WG,
+ statistics and M&C in VHDL
+Jira JH: simulate ADC input section using multiple ADC
+Jira JH: demonstrate ADC input section on HW using two jesd_u2 ADC boards
+Jira EK: Define update of bsn_source.vhd with BSN offset
+Jira ?: Implement update of bsn_source.vhd with BSN offset
+
+
+2) D42 SDP OPC-UA server prototype
+
+Assumptions (do you agree PD, LH):
+- first use a temporary platform (e.g. LCU, raspberry pi)
+- use UniBoard Control Protocol
+- only the low rate M&C will go via OPC-UA, so BF weights and statistics via
+ a separate UDP path between LCU2 and SDP
+
+Jira PD: Decribe unb2_minimal in ARGS-YAML, so that we can use that YAML file
+ as input for the OPC-UA translator
+Jira PD: Decribe unb2b_adc_full in ARGS-YAML, so that we can use that YAML
+ file as input for the OPC-UA translator
+Jira LH: Demonstrate M&C access using YAML file of regmap and UCP, e.g. via
+ a GUI
+Jira LH: Present regmap as OPC-UA interface based on ARGS-YAML file
+Jira LH: Investigate possible microcontroller platform
+
+Jira EK: L2 STAT DD Location of SC-SDP translator function
+ Update downselect of location of OPC-UA translator (combined task of
+ SDP and station Control)
+ - different types of M&C (volume, high rate, low rate, time critical)
+ - BF weights with timestamp to apply in future, or immediately if in
+ the past.
+ - Statistics read or stream at PPS or shorter intervals. Also stream
+ low rate BST, because streaming is for any time critical monitoring
+ not only for high rate time critical.
+Jira EK: L3 SDP DD Monitoring and Control
+ Finish downselect of Gemini Protocol and Uniboard COntrol Protocol
+ (mainly task within SDP)
+ - GP-UCP, QSYS-RTL, NiosII-RTL
+ - risk of delay due to:
+ . complexity of porting to VHDL (64b-32b, Axi-Avalon, IP data mover)
+ . low TRL of GP
+ . tight SDP planning
+ - unclear or too little benifit of GP compared to UCP
+ - not used for SDP or DESP future, if we have a SOC then direct
+ OPC-UA via TCP/IP
+
+Jira PD: demonstrate unb2b_arp_ping on UniBoard2, to show that the VHDL works
+ (part of learning VHDL).
+ - why are the IP files in git and why have they changed on the branch,
+ this change may be only a change in date
+ - Get unb2b_minimal working on HW when synthesizedfrom git branch, is
+ it still working when created on the master branch?
+ - Compare synthesis report of unb2b_arp_ping and unb2b_minimal
+ - check UniBoard_FP7/UniBoard/trunk/Firmware/doc/howto/
+ how_to_write_VHDL.txt e.g. coding style, latches and debugging tips
+ - make sure that eth1g_master makes the same TSE and ETH settings as
+ unb_osy.c
+ - tb_unb2b_arp_ping should always work before trying synthesis or
+ commit
+
+3) D9 : Production package proto unb2c
+
+Firmware (can be prepared and ready for use without hardware)
+Jira JH : D3 unb2c_test_pinning (using 10GbE)
+Jira JH : D4 unb2c_test_pinning_jesd (using JESD204b)
+Jira JH : D5 unb2c_heater (verify speed grade)
+Jira JH : D6 unb2c_test_ddr4 (both slots)
+Jira JH : D7 unb2c_test_10GbE (QSFP + ring, back)
+Jira JH : D8 unb2c_test_adc (= lofar2_unb2b_adc_one_node for unb2c)
+
+Hardware (to be able to manufacture and test the board)
+Jira GS : D1 UniBoard2 Detailed Design document
+Jira GS : D9 Production package proto UniBoard2
+
+
+4) Write the SDP design documents and ICDs (EK)
+
+D19 SDP requirements specification (for DDR, CDR)
+D20 SDP architectural design document (for DDR, CDR)
+
+Jira EK : L3 SDP ADD Toplevel
+Jira EK : L3 SDP DD Timing
+Jira EK : L3 SDP DD Monitoring and Control
+
+Jira EK : L4 SDP DD Firmware
+Jira EK : L5 SDP DD ADC input and timing
+ - ADC align @ sysref in JESD IP or in seperate RTL or in input
+ buffer?
+ - The sysref of the FPGA always arrives and arrives before the
+ data of the ADC, so sysref of FPGA is the stable reference for
+ ADC align that also works when an ADC is off.
+ - sysref of FPGA is PPS with 200M samples per period and can
+ serve as interface towards OpenCL. Define a sample sequence
+ number (SSN) that counts samples and is initialized at PPS.
+ - timing of WG
+ - new BSN source with BSN offset
+Jira EK : L5 SDP DD beamformer
+Jira EK : L5 SDP DD SDP correlator
+Jira EK : L5 SDP DD SDP ring
+
+Jira EK : D41 ICD SC-SDP for SDP-OPC-UA server
+
+
+5) Other
+Jira RW: dp_sosi_rst only for the control
+Jira PD: VHDL regression test running also for Git
+Jira EK: L3 SDP prestudy note on oversampled filterbank
+
+Questions:
+a) How many days are you available for SDP sprint 3?
+b) What do you think we should and can achieve for this increment regarding
+ the Lab Test Station and what can you do for that?
+c) Jonathan can you still prepare the unb2c test firmware in sprint 4?
+d) Reviewers
-* 5 valkuilen van thuiswerken
- - blurring (prive, werk)
- - onderbrekingen
- - overbelasting (wat belangrijker dan hoe, want anderen zien alleen wat)
- - vereenzaming
- - minder groeikansen (zichtbaar blijven)
-
- Goede werkplek:
- - Ik kies een plek die ik alleen gebruik om te werken
- - Ik houd rekening met mijn gezondheid - arboregels: stoel, bureau, licht
- . 20-20-20 regel: iedere 20 minuten kijk je 20 seconden van je beeldscherm weg, naar een punt 20 meter in de verte
- . iedere twee uur minimaal een kwartier pauze. Sta op, loop wat rond
- . minimale afstand van 50 cm afstand tussen ogen en beeldscherm, en zorg ervoor dat de bovenkant van het beeldscherm gelijk is aan ooghoogte.
- - Ik elimineer afleiding zoveel mogelijk
- - Ik houd mijn werkomgeving opgeruimd en deze oogt prettig
- . een plant
-
-* Niet zeggen als je krachtig wil overkomen:
- - ik wil alleen maar even checken --> direct vragen
- - ik weet het ook niet zeker maar --> gegeven de feiten
- - ik denk niet dat --> zeg wat je wel denkt
- - misschien kunnen we * proberen
- - begrijp je wat ik zeg (zaait twijfel, die er misschien niet was)
-
-* Gesprekstechnieken (ijsbrekers):
- 1) nieuwsgierige vragen nav van wat iemand zegt of deed werken goed want:
- ?Ze zeggen ?ik leid dit gesprek, en dit is wat ik specifiek van je wil weten?. Wanneer je zo zelfverzekerd en duidelijk in je verwachtingen bent, helpt dat je gesprekspartner om te ontspannen en een meer natuurlijk gesprek te voeren.?
- 2) verhaal vertellende vragen, hoe heb je dat gedaan of zou je dat doen:
- ?Met storytelling vragen krijg je echt waar voor je geld. Je hoeft maar ��n vraag te stellen om een lang antwoord van je gesprekspartner te krijgen.?
- 3) vervolgdetail vragen: bijv. waarom is dat zo denk je, hoe reageerde hij toen, wanneer viel het je voor het eerst op.
-
- Samengevat: ?Vertel me daar eens meer over.?:
- Kun je die reactie onthouden, en dat moet vast lukken ? dan zit je altijd goed. Het is h�t format dat altijd werkt om meer informatie uit je gesprekspartner te halen over een bepaald topic dat jou aanstaat. Jij leidt, hij spreekt, jij luistert.
-
-* Levensstijl:
- - https://timemanagement.nl/intermittent-fasting/
- Tijdgebonden eten bevordert de interne genezingsprocessen in het lichaam. Enerzijds doordat het de kans op kanker verlaagt, anderzijds omdat het de microbacteri�n in de darm verbetert ? zaken die beide belangrijk zijn voor een hogere levensverwachting.
- - 16/8 methode: elke dag gedurende 16 uren niet eten, bijv van 20u - 12u
- . verhoogde concentratie.
- . minder last van het hongergevoel
- . je went er snel aan.
- . meest flexibele methode.
- - ADF (alternate day fasting): ene dag van 8-20u eten andere dag vanaf 20u
- . minder last van een hongergevoel
- . relatief eenvoudig vol te houden.
- . meest effectieve intermittent fasting methode. Vooral wanneer het op gewichtsverlies en voorkomen van hart-en vaatziekten aankomt.
-
-* Evaluatiegesprek
- - Niet te gevoelig of te hard of te vaag, claimt Kim Scott
- - Wel oprecht, integer, zorgzaam:
- . Ga het gesprek niet uit de weg. Want, zegt Scott: ?iets slechts wordt niet beter met de tijd?.
- . Neem geen lange aanloop. Kom direct to the point met je belangrijkste feedback-punt.
- . Wees duidelijk. Geef �f een verbeterpunt, �f een compliment. Geen combinatie. Geen sandwich. Geen ?heel goed, maar??.
-
-* 5 Navy SEAL?s Tactieken om Je Wilskracht te Vergroten
- . positief te blijven, zelfs wanneer alles tegenzit (bedenk het is tijdelijk, heeft oorzaak, is niet persoonlijk)
- . Door door te zetten, ook al schreeuwt je brein dat het op is. Vaak zit je pas op 40%.
- . Door doelen te stellen en te kijken welke stap je vandaag kunt nemen om die te bereiken.
- . Door je een voorstelling te maken (visualiseren) van je aanpak en de eventuele obstakels die je tegenkomt.
- . Door om hulp te vragen wanneer je iets niet weet.
-
-* Lezen
- . Ik lees een half uur per dag, op een vast tijdstip, iedere dag
-
-* Omgaan met kritiek (of eigenlijk omgaan advies)
-. Vraag om verbeter tip nav de kritiek
-
-
-* 4 stappen om doelen te bereiken:
-
- - Kijk eerst naar het verleden ? wat ging er goed en wat kun je ervan leren?
- . Wat waren vorig jaar mijn hoogte- en dieptepunten?
- . Wat waren de beste �n slechtste (bewuste) keuzes die ik vorig jaar heb gemaakt?
- . Wie waren de belangrijkste mensen in mijn leven en welke relaties kan ik beter be�indigen?
-
- - Bepaal de ideale levensstijl ? hoe ziet jouw ideale leven eruit?
- . Hoe wil ik het liefst mijn geld verdienen?
- . Onder welke omstandigheden wil ik werken?
- . Hoe zijn mijn financi�n geregeld?
- . Hoe ziet de ideale relatie voor mij uit?
- . Hoe spendeer ik mijn vrije tijd?
- . Hoe ziet een gezonde levensstijl er voor mij uit?
- . Leef ik volgens mijn eigen overtuigingen?
- . Hoe ziet mijn optimale sociale leven eruit?
-
- - Bepaal concrete doelen die je moet nastreven om het ideaalbeeld te bereiken ? wat moet jij doen wil jij dat leven binnen handbereik hebben?
- . Categerie: werk, financi�n, vrije tijd, gezondheid, sociaal leven, relaties en spiritualiteit
- . Per categorie 1 doel SMART (Specifiek, Meetbaar, Acceptabel, Realistisch en Tijdsgebonden) maken.
-
- - Bekijk welke veranderingen je moet doorvoeren in je levensstijl, om de doelen te kunnen bereiken.
-
*******************************************************************************
-* Algemeen
+* Q2 = Increment 2
*******************************************************************************
-* https://getpocket.com/explore/item/want-to-work-smarter-not-harder-10-scientifically-proven-ways-to-be-incredibly-productive?utm_source=pocket-newtab
- Ten Scientifically Proven Ways to Be Incredibly Productive
-
- 1 Rework Your To-Do List (Focus only on today)
- 2 Measure Your Results, Not Your Time
- 3 Build Habits to Help You Start Working
- 4 Track Where You Waste Time
- 5 Build Habits to Help You Stop Working (stop wanneer je weet wat je morgen zult doen, plan iets leuks voor na werk)
- 6 Take More Breaks
- 7 Take More Naps
- 8 Spend More Time in Nature
- 9 Move and Work in Blocks
- 10 Check Your Email First Thing
-
-* Start before you are ready.
+- finish unb2c_test designs
+- design document for SDP BF, BF output to CEP (D21)
+- design document for SDP Transient buffer
+- subband filterbank
+- subband correlator on one node
+- beamformer output to CEP
+- ring (C�dric Dumez-Viou ?)
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_icd.txt b/applications/lofar2/doc/prestudy/station2_sdp_icd.txt
index bbae5cec5cff3f6fdbbfd7f5f35bdf80869259a9..c6083f79f0991fd7d7a5b3dfb44b6fc601721aeb 100755
--- a/applications/lofar2/doc/prestudy/station2_sdp_icd.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_icd.txt
@@ -695,9 +695,15 @@ band[0:1]/sdpfw
De SDP Translator is valt ook onder beheer EC2.
-Enianess:
+Endianess:
The Nios II architecture uses little-endian byte ordering. Words and halfwords are stored inmemory with the more-significant bytes at higher addresses.
+_RW is control punt in SDP, wordt niet gelezen door SC, maar kan wel want SDPTR bewaard de _RW van de SDPFW
+ . '_RW' is read from Tango (W is cached in Tango)
+_R is corresponding monitor punt, komt vanuit SDPFW voor fpga_ of uit SDPTR voor tr_:
+ . elke _RW heeft een _R, should be equal from cached _RW write in Tango
+ . er zijn ook _R zonder _RW
+
###################################################################################################
diff --git a/applications/lofar2/images/images.txt b/applications/lofar2/images/images.txt
new file mode 100644
index 0000000000000000000000000000000000000000..a228338d6096069dc448a6e2a00e894c69b1311d
--- /dev/null
+++ b/applications/lofar2/images/images.txt
@@ -0,0 +1,5 @@
+Image name | Date | Author | Usage
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+lofar2_unb2b_filterbank_full-r8a75c955b | 2021-03-01 | R vd Walle | See $UPE_GEAR/peripherals/tc_lofar2_unb2b_filterbank.py
+
+
diff --git a/applications/lofar2/images/lofar2_unb2b_filterbank_full-r8a75c955b.tar.gz b/applications/lofar2/images/lofar2_unb2b_filterbank_full-r8a75c955b.tar.gz
new file mode 100644
index 0000000000000000000000000000000000000000..f9122f1d372bfb3683a62517a5d25f40102ff5f6
Binary files /dev/null and b/applications/lofar2/images/lofar2_unb2b_filterbank_full-r8a75c955b.tar.gz differ
diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..dc9b8b805a4c6f04e9da0b69b7b019340f280c6d
--- /dev/null
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -0,0 +1,435 @@
+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: sdp
+hdl_library_description: "Station Digital Processor (SDP) for LOFAR2.0"
+
+peripherals:
+ - peripheral_name: sdp_info # pi_sdp_info.py ?
+ peripheral_description: "SDP info."
+ mm_ports:
+ # MM port for sdp_info.vhd
+ - mm_port_name: REG_SDP_INFO
+ mm_port_description: |
+ "The SDP info contains central SDP information. The station_id applies to the entire station.
+ The other info fields apply per antenna band (low band or high band). An FPGA node only
+ participates in one band."
+ mm_port_type: REG
+ fields:
+ - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x0 }
+ - - { field_name: antenna_band_index, width: 1, access_mode: RO, address_offset: 0x4 }
+ - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: nyquist_zone_index, width: 2, access_mode: RW, address_offset: 0xC }
+ - - { field_name: f_adc, width: 1, access_mode: RO, address_offset: 0x10 }
+ - - { field_name: fsub_type, width: 1, access_mode: RO, address_offset: 0x14 }
+ - - { field_name: beam_repositioning_flag, width: 1, access_mode: RW, address_offset: 0x18 }
+ - - { field_name: subband_calibrated_flag, width: 1, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: O_si, width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: N_si, width: 8, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: O_rn, width: 8, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: N_rn, width: 8, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: block_period, width: 16, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: beamlet_scale, width: 16, access_mode: RW, address_offset: 0x34 }
+
+
+ - peripheral_name: sdp_subband_equalizer # pi_sdp_subband_equalizer.py
+ peripheral_description: "SDP Subband equalizer coefficients."
+ parameters:
+ # Parameters of pi_sdp_subband_equalizer.py, fixed in sdp_subband_equalizer.vhd / sdp_pkg.vhd
+ - { name: g_nof_instances, value: 6 } # P_pfb = S_pn / Q_fft = 12 / 2 = 6
+ mm_ports:
+ # MM port for sdp_subband_equalizer.vhd
+ - mm_port_name: RAM_EQUALIZER_GAINS
+ mm_port_description: |
+ "The subband weigths are stored in g_nof_instances = P_pfb = S_pn / Q_fft = 6 blocks of
+ Q_fft * N_sub = 2 * 512 = 1024 complex coefficients as:
+
+ (cint16)subband_weights[S_pn/Q_fft]_[Q_fft][N_sub]
+
+ where S_pn = 12, Q_fft = 2 and N_sub = 512 are defined in sdp_pkg.vhd."
+ mm_port_type: RAM
+ number_of_mm_ports: g_nof_instances
+ fields:
+ - - field_name: coef
+ field_description: |
+ "Complex coefficient to calibrate the gain and phase per subband. Packed as imaginary in high part,
+ real in low part of width = N_complex * W_sub_weight = 2 * 16 = 32 bit."
+ width: 32 # = N_complex * W_sub_weight
+ address_offset: 0x0
+ number_of_fields: 1024 # = Q_fft * N_sub = 2 signal inputs * 512 subbands
+ radix: complx
+
+
+ - peripheral_name: sdp_bf_weights # pi_sdp_bf_weights.py
+ peripheral_description: "SDP Beamformer weights (= beamlet weights)."
+ parameters:
+ # Parameters of pi_sdp_bf_weights.py, fixed in sdp_bf_weights.vhd / sdp_pkg.vhd
+ - { name: g_nof_instances, value: 12 } # = N_pol_bf * P_pfb
+ - { name: g_nof_gains, value: 976 } # = Q_fft * S_sub_bf
+ mm_ports:
+ # MM port for sdp_beamformer_local.vhd / sdp_bf_weights.vhd / mms_dp_gain_serial_arr.vhd
+ - mm_port_name: RAM_BF_WEIGHTS
+ mm_port_description: |
+ "The beamlet weigths are stored in g_nof_instances = N_pol_bf * P_pfb = 2 * 6 = 12, where
+ P_pfb = S_pn / Q_fft = 6. Per instance there is a block of Q_fft * S_sub_bf =
+ 2 * 488 = 976 complex BF weights. The N_pol_bf = 2 represents the two beamformer
+ polarizations, to distinguish these from the N_pol = 2 antenna polarizations. The
+ beamlet weigths for S_pn = P_pfb * Q_fft = 12 signal inputs are therefore defined by:
+
+ (cint16)bf_weights[N_pol_bf][P_pfb]_[Q_fft][S_sub_bf]
+
+ where N_pol_bf = 2, P_pfb = 6 and Q_fft = 2 and S_sub_bf = 488, defined in sdp_pkg.vhd.
+
+ The pairs of Q_fft signal inputs that are multiplexed per block are mapped to the N_pol = 2
+ polarizations of an antenna. Therefore A_pn = P_pfb = 6 is the number dual polarization
+ antennas per peripheral. The beamlet weigths for S_pn = A_pn * N_pol = 12 signal inputs
+ are therefore defined by:
+
+ (cint16)bf_weights[N_pol_bf][A_pn]_[N_pol][S_sub_bf]
+
+ where N_pol_bf = 2, A_pn = 6 and N_pol = 2 and S_sub_bf = 488, defined in sdp_pkg.vhd.
+
+ The BF weights can implement the full 2x2 Jones matrix for weighting and adding the
+ signal input polarizations [x, y] per dual polarization antenna. The polarization index
+ mapping is index 0 = X and index 1 = Y. The co-polarization BF weights (XX, YY) are set
+ when index of N_pol_bf and index of N_pol are the same. The cross-polarization BF
+ weights (XY, YX) are set when index of N_pol_bf and index of N_pol are different. If
+ no cross-polarization weighting is needed, then these weights can be kept 0."
+ mm_port_type: RAM
+ number_of_mm_ports: g_nof_instances
+ fields:
+ - - field_name: coef
+ field_description: |
+ "Complex weight per subband. Packed as imaginary in high part, real in low part
+ of width = N_complex * W_bf_weight = 2 * 16 = 32 bit."
+ width: 32 # = N_complex * W_bf_weight
+ address_offset: 0x0
+ number_of_fields: g_nof_gains
+ radix: complx
+
+
+ - peripheral_name: sdp_bf_scale # pi_sdp_bf_scale.py
+ peripheral_description: "SDP BF beamlet data output scaling and requantization."
+ parameters:
+ # Parameters fixed in node_sdp_beamformer.vhd / mms_dp_scale.vhd / sdp_pkg.vhd
+ - { name: g_gain_w, value: 16 }
+ - { name: g_lsb_w, value: 15 }
+ mm_ports:
+ # MM port for node_sdp_beamformer.vhd / mms_dp_scale.vhd / mms_dp_gain.vhd / mms_dp_gain_arr.vhd
+ - mm_port_name: REG_BF_SCALE
+ mm_port_description: |
+ "The beamlet scale function scales the beamlet sum with a real scale factor and then
+ requantizes the result to beamlet data output with less bits.
+ The beamlet scale factor has g_gain_w bits and the value 2**g_lsb_w represents a gain of 1.
+ For example for g_gain_w = 16, g_lsb_w = 15, a beamlet sum of 18 bits and beamlet data
+ output of 8 bits, a scale value of:
+ . 2**g_lsb_w = 2**15 selects the lowest 8 bits of the beamlet sum and clips the highest
+ 10 bits,
+ . 2**11 rounds the lowest 4 bits, selects the next 8 bits of the beamlet sum and clips
+ the highest 6 bits,
+ . 2**5 rounds the lowest 10 bits and selects the highest 8 bits of the beamlet sum."
+ mm_port_type: REG
+ fields:
+ - - field_name: scale
+ field_description: ""
+ width: g_gain_w
+ address_offset: 0x0
+ number_of_fields: 1
+ radix: unsigned
+ #radix_width: g_gain_w
+ radix_resolution: 0 - g_lsb_w
+ - - field_name: unused
+ field_description: "Not used."
+ address_offset: 0x4
+
+
+ - peripheral_name: sdp_beamformer_output_hdr_dat # pi_dp_offload_tx_hdr_dat_lofar2_beamformer_output.py
+ peripheral_description: "SDP BF beamlet data output header."
+ mm_ports:
+ # MM port for sdp_beamformer_output.vhd / dp_offload_tx_v3.vhd
+ - mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
+ mm_port_description: |
+ "The ETH/IP/UDP/application header fields for the beamlet data output offload UDP packets.
+
+ The header fields are described in ICD STAT-CEP [1].
+
+ https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L1%20Interface%20Control%20Documents/STAT%20to%20CEP%20ICD
+
+ From tb_dp_offload_tx_v3.vhd simulation it follows that:
+ . the header fields are stored in reversed address order due to that the array in VHDL has
+ range (h downto 0) where the first header field (eth_destination_mac) is at index h.
+ . the RO fields are filled in by the logic, when the packet header is transmitted, however
+ the read value does not still represents the MM write value, not the transmitted value.
+ . dp_bsn with radix_width = 64 is stored as:
+ word byte
+ addr addr bits
+ 0 0x0 [31:0] = dp_bsn[31:0]
+ 1 0x4 [31:0] = dp_bsn[63:32]
+ . eth_dst_mac with radix_width = 48 is stored as:
+ word byte
+ addr addr bits
+ 21 0x84 [31:0] = eth_dst_mac[31:0]
+ 22 0x88 [15:0] = eth_dst_mac[47:32]
+ "
+ mm_port_type: REG
+ fields:
+ # eth field group
+ - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 }
+ - - { field_name: eth_source_mac, width: 32, access_mode: RO, address_offset: 0x7C, radix_width: 48 }
+ - - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
+ # ip field group
+ - - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_length, width: 4, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_services, width: 8, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_total_length, width: 16, access_mode: RW, address_offset: 0x68 }
+ - - { field_name: ip_identification, width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: ip_flags, width: 3, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: ip_fragment_offset, width: 13, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: ip_time_to_live, width: 8, access_mode: RW, address_offset: 0x58 }
+ - - { field_name: ip_protocol, width: 8, access_mode: RW, address_offset: 0x54 }
+ - - { field_name: ip_header_checksum, width: 16, access_mode: RW, address_offset: 0x50 }
+ - - { field_name: ip_source_address, width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: ip_destination_address, width: 32, access_mode: RW, address_offset: 0x48 }
+ # udp field group
+ - - { field_name: udp_source_port, width: 16, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: udp_destination_port, width: 16, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: udp_length, width: 16, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: udp_checksum, width: 16, access_mode: RW, address_offset: 0x38 }
+ # application field group
+ - - { field_name: marker, width: 8, access_mode: RO, address_offset: 0x34 }
+ - - { field_name: version_id, width: 8, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: source_info, width: 16, access_mode: RW, address_offset: 0x24 }
+ - "source_info":
+ - { field_name: antenna_band_index, width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
+ - { field_name: nyquist_zone_index, width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
+ - { field_name: f_adc, width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
+ - { field_name: fsub_type, width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
+ - { field_name: payload_error, width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
+ - { field_name: repositioning_flag, width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
+ - { field_name: beamlet_width, width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
+ - { field_name: gn_index, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+
+ - - { field_name: reserved, width: 32, access_mode: RW, address_offset: 0x1C, radix_width: 40 }
+ - - { field_name: beamlet_scale, width: 16, access_mode: RW, address_offset: 0x18 }
+ - - { field_name: beamlet_index, width: 16, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: nof_blocks_per_packet, width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: nof_beamlets_per_block, width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, width: 32, access_mode: RW, address_offset: 0x0, radix_width: 64 }
+
+
+ - peripheral_name: sdp_statistics_offload_hdr_dat_sst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
+ peripheral_description: "SDP statistics offload header for the subband statistics (SST)."
+ mm_ports:
+ # MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd
+ - mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
+ mm_port_description: |
+ "The ETH/IP/UDP/application header fields for the SST offload UDP packets.
+
+ The Subband statistics (SST) are integrated auto power values of the subbands per signal input.
+ The SST specific settings are defined by data_id_sst.
+
+ The statistics offload header fields are described in ICD SC-SDP [1].
+
+ [1] https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD
+ "
+ mm_port_type: REG
+ fields:
+ # eth field group
+ - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 }
+ - - { field_name: eth_source_mac, width: 32, access_mode: RO, address_offset: 0x7C, radix_width: 48 }
+ - - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
+ # ip field group
+ - - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_length, width: 4, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_services, width: 8, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_total_length, width: 16, access_mode: RW, address_offset: 0x68 }
+ - - { field_name: ip_identification, width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: ip_flags, width: 3, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: ip_fragment_offset, width: 13, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: ip_time_to_live, width: 8, access_mode: RW, address_offset: 0x58 }
+ - - { field_name: ip_protocol, width: 8, access_mode: RW, address_offset: 0x54 }
+ - - { field_name: ip_header_checksum, width: 16, access_mode: RW, address_offset: 0x50 }
+ - - { field_name: ip_source_address, width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: ip_destination_address, width: 32, access_mode: RW, address_offset: 0x48 }
+ # udp field group
+ - - { field_name: udp_source_port, width: 16, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: udp_destination_port, width: 16, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: udp_length, width: 16, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: udp_checksum, width: 16, access_mode: RW, address_offset: 0x38 }
+ # application field group
+ - - { field_name: marker, width: 8, access_mode: RO, address_offset: 0x34 }
+ - - { field_name: version_id, width: 8, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: source_info, width: 16, access_mode: RW, address_offset: 0x24 }
+ - "source_info":
+ - { field_name: antenna_band_index, width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
+ - { field_name: nyquist_zone_index, width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
+ - { field_name: f_adc, width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
+ - { field_name: fsub_type, width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
+ - { field_name: payload_error, width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
+ - { field_name: beam_repositioning_flag, width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
+ - { field_name: subband_calibrated_flag, width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
+ - { field_name: reserved, width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
+ - { field_name: gn_index, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+
+ - - { field_name: reserved, width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: integration_interval, width: 24, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: data_id, width: 32, access_mode: RW, address_offset: 0x18 }
+ - "data_id_sst":
+ - { field_name: reserved, width: 24, bit_offset: 8, access_mode: RW, address_offset: 0x18 }
+ - { field_name: signal_input_index, width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
+
+ - - { field_name: nof_signal_inputs, width: 8, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: nof_bytes_per_statistic, width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: nof_statistics_per_packet, width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, width: 32, access_mode: RW, address_offset: 0x0, radix_width: 64 }
+
+
+ - peripheral_name: sdp_statistics_offload_hdr_dat_bst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
+ peripheral_description: "SDP statistics offload header for the beamlet statistics (BST)."
+ mm_ports:
+ # MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd
+ - mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
+ mm_port_description: |
+ "The ETH/IP/UDP/application header fields for the BST offload UDP packets.
+
+ The beamlet statistics (BST) are integrated auto power values of the beamlets per beamset
+ The BST specific settings are defined by data_id_bst.
+
+ The statistics offload header fields are described in ICD SC-SDP [1].
+
+ [1] https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD
+ "
+ mm_port_type: REG
+ fields:
+ # eth field group
+ - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 }
+ - - { field_name: eth_source_mac, width: 32, access_mode: RO, address_offset: 0x7C, radix_width: 48 }
+ - - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
+ # ip field group
+ - - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_length, width: 4, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_services, width: 8, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_total_length, width: 16, access_mode: RW, address_offset: 0x68 }
+ - - { field_name: ip_identification, width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: ip_flags, width: 3, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: ip_fragment_offset, width: 13, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: ip_time_to_live, width: 8, access_mode: RW, address_offset: 0x58 }
+ - - { field_name: ip_protocol, width: 8, access_mode: RW, address_offset: 0x54 }
+ - - { field_name: ip_header_checksum, width: 16, access_mode: RW, address_offset: 0x50 }
+ - - { field_name: ip_source_address, width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: ip_destination_address, width: 32, access_mode: RW, address_offset: 0x48 }
+ # udp field group
+ - - { field_name: udp_source_port, width: 16, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: udp_destination_port, width: 16, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: udp_length, width: 16, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: udp_checksum, width: 16, access_mode: RW, address_offset: 0x38 }
+ # application field group
+ - - { field_name: marker, width: 8, access_mode: RO, address_offset: 0x34 }
+ - - { field_name: version_id, width: 8, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: source_info, width: 16, access_mode: RW, address_offset: 0x24 }
+ - "source_info":
+ - { field_name: antenna_band_index, width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
+ - { field_name: nyquist_zone_index, width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
+ - { field_name: f_adc, width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
+ - { field_name: fsub_type, width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
+ - { field_name: payload_error, width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
+ - { field_name: beam_repositioning_flag, width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
+ - { field_name: subband_calibrated_flag, width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
+ - { field_name: reserved, width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
+ - { field_name: gn_index, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+
+ - - { field_name: reserved, width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: integration_interval, width: 24, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: data_id, width: 32, access_mode: RW, address_offset: 0x18 }
+ - "data_id_bst":
+ - { field_name: reserved, width: 16, bit_offset: 16, access_mode: RW, address_offset: 0x18 }
+ - { field_name: beamlet_index, width: 16, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
+
+ - - { field_name: nof_signal_inputs, width: 8, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: nof_bytes_per_statistic, width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: nof_statistics_per_packet, width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, width: 32, access_mode: RW, address_offset: 0x0, radix_width: 64 }
+
+
+ - peripheral_name: sdp_statistics_offload_hdr_dat_xst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
+ peripheral_description: "SDP statistics offload header for the cross-subband statistics (XST)."
+ mm_ports:
+ # MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd
+ - mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
+ mm_port_description: |
+ "The ETH/IP/UDP/application header fields for the XST offload UDP packets.
+
+ The crosslet statistics (XST) are integrated cross power values of the subbands from all
+ pairs of signal inputs per suband.
+ The XST specific settings are defined by data_id_xst.
+
+ The statistics offload header fields are described in ICD SC-SDP [1].
+
+ [1] https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD
+ "
+ mm_port_type: REG
+ fields:
+ # eth field group
+ - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 }
+ - - { field_name: eth_source_mac, width: 32, access_mode: RO, address_offset: 0x7C, radix_width: 48 }
+ - - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
+ # ip field group
+ - - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_length, width: 4, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_services, width: 8, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_total_length, width: 16, access_mode: RW, address_offset: 0x68 }
+ - - { field_name: ip_identification, width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: ip_flags, width: 3, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: ip_fragment_offset, width: 13, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: ip_time_to_live, width: 8, access_mode: RW, address_offset: 0x58 }
+ - - { field_name: ip_protocol, width: 8, access_mode: RW, address_offset: 0x54 }
+ - - { field_name: ip_header_checksum, width: 16, access_mode: RW, address_offset: 0x50 }
+ - - { field_name: ip_source_address, width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: ip_destination_address, width: 32, access_mode: RW, address_offset: 0x48 }
+ # udp field group
+ - - { field_name: udp_source_port, width: 16, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: udp_destination_port, width: 16, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: udp_length, width: 16, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: udp_checksum, width: 16, access_mode: RW, address_offset: 0x38 }
+ # application field group
+ - - { field_name: marker, width: 8, access_mode: RO, address_offset: 0x34 }
+ - - { field_name: version_id, width: 8, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: source_info, width: 16, access_mode: RW, address_offset: 0x24 }
+ - "source_info":
+ - { field_name: antenna_band_index, width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
+ - { field_name: nyquist_zone_index, width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
+ - { field_name: f_adc, width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
+ - { field_name: fsub_type, width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
+ - { field_name: payload_error, width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
+ - { field_name: beam_repositioning_flag, width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
+ - { field_name: subband_calibrated_flag, width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
+ - { field_name: reserved, width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
+ - { field_name: gn_index, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+
+ - - { field_name: reserved, width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: integration_interval, width: 24, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: data_id, width: 32, access_mode: RW, address_offset: 0x18 }
+ - "data_id_xst":
+ - { field_name: reserved, width: 7, bit_offset: 25, access_mode: RW, address_offset: 0x18 }
+ - { field_name: subband_index, width: 9, bit_offset: 16, access_mode: RW, address_offset: 0x18 }
+ - { field_name: signal_input_A_index, width: 8, bit_offset: 8, access_mode: RW, address_offset: 0x18 }
+ - { field_name: signal_input_B_index, width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
+
+ - - { field_name: nof_signal_inputs, width: 8, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: nof_bytes_per_statistic, width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: nof_statistics_per_packet, width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, width: 32, access_mode: RW, address_offset: 0x0, radix_width: 64 }
+
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index d8c90a54662260b2af8f72c5cf10f1f87136d3f2..a33fdb59910caf81e2b261cb293cb73906a3e8e6 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -35,10 +35,11 @@
-- .
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib, rTwoSDF_lib, wpfb_lib, filter_lib, si_lib, st_lib;
+LIBRARY IEEE, common_lib, dp_lib, rTwoSDF_lib, wpfb_lib, filter_lib, si_lib, st_lib, mm_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE rTwoSDF_lib.rTwoSDFPkg.ALL;
USE filter_lib.fil_pkg.ALL;
@@ -49,7 +50,8 @@ ENTITY node_sdp_filterbank IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
- g_scope_selected_subband : NATURAL := 0
+ g_scope_selected_subband : NATURAL := 0;
+ g_offload_time : NATURAL := 0
);
PORT (
dp_clk : IN STD_LOGIC;
@@ -58,6 +60,8 @@ ENTITY node_sdp_filterbank IS
in_sosi_arr : IN t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
pfb_sosi_arr : OUT t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
fsub_sosi_arr : OUT t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ sst_udp_sosi : OUT t_dp_sosi;
+ sst_udp_siso : IN t_dp_siso := c_dp_siso_rst;
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
@@ -71,7 +75,18 @@ ENTITY node_sdp_filterbank IS
ram_gains_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_gains_miso : OUT t_mem_miso;
reg_selector_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_selector_miso : OUT t_mem_miso
+ reg_selector_miso : OUT t_mem_miso;
+ reg_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_enable_miso : OUT t_mem_miso;
+ reg_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_hdr_dat_miso : OUT t_mem_miso;
+
+ sdp_info : IN t_sdp_info;
+ gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
+
+ eth_src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ udp_src_port : IN STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0)
);
END node_sdp_filterbank;
@@ -82,9 +97,20 @@ ARCHITECTURE str OF node_sdp_filterbank IS
CONSTANT c_subband_equalizer_latency : NATURAL := 4;
+ CONSTANT c_nof_masters : POSITIVE := 2;
+
SIGNAL ram_st_sst_mosi_arr : t_mem_mosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL ram_st_sst_miso_arr : t_mem_miso_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ -- Subband statistics
+ SIGNAL ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL master_mosi_arr : t_mem_mosi_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
+ SIGNAL master_miso_arr : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
+
SIGNAL si_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL wpfb_unit_out_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL wpfb_unit_fil_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
@@ -234,12 +260,32 @@ BEGIN
g_mult_addr_w => ceil_log2(c_sdp_N_sub*c_sdp_Q_fft*g_wpfb.stat_data_sz)
)
PORT MAP (
- mosi => ram_st_sst_mosi,
- miso => ram_st_sst_miso,
+ mosi => master_mem_mux_mosi,
+ miso => master_mem_mux_miso,
mosi_arr => ram_st_sst_mosi_arr,
miso_arr => ram_st_sst_miso_arr
);
+ -- Connect 2 mm_masters to the common_mem_mux output
+ master_mosi_arr(0) <= ram_st_sst_mosi; -- MM access via QSYS MM bus
+ ram_st_sst_miso <= master_miso_arr(0);
+ master_mosi_arr(1) <= ram_st_offload_mosi; -- MM access by SST offload
+ ram_st_offload_miso <= master_miso_arr(1);
+
+ u_mem_master_mux : ENTITY mm_lib.mm_master_mux
+ GENERIC MAP (
+ g_nof_masters => c_nof_masters,
+ g_rd_latency_min => 1 -- TODO, make constant and check if value is right
+ )
+ PORT MAP (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => master_mosi_arr,
+ master_miso_arr => master_miso_arr,
+ mux_mosi => master_mem_mux_mosi,
+ mux_miso => master_mem_mux_miso
+ );
+
---------------------------------------------------------------
-- SIGNAL SCOPE
---------------------------------------------------------------
@@ -258,4 +304,40 @@ BEGIN
scope_sosi_arr => scope_sosi_arr
);
+ ---------------------------------------------------------------
+ -- STATISTICS OFFLOAD
+ ---------------------------------------------------------------
+ u_sdp_sst_udp_offload: ENTITY work.sdp_statistics_offload
+ GENERIC MAP (
+ g_statistics_type => "SST",
+ g_offload_time => g_offload_time
+ )
+ PORT MAP (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ master_mosi => ram_st_offload_mosi,
+ master_miso => ram_st_offload_miso,
+
+ reg_enable_mosi => reg_enable_mosi,
+ reg_enable_miso => reg_enable_miso,
+
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+
+ sdp_info => sdp_info,
+ gn_index => TO_UINT(gn_id),
+
+ in_sosi => dp_selector_out_sosi_arr(0),
+ out_sosi => sst_udp_sosi,
+ out_siso => sst_udp_siso,
+
+ eth_src_mac => eth_src_mac,
+ udp_src_port => udp_src_port,
+ ip_src_addr => ip_src_addr
+ );
+
END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 051475bce5e7639eef97df1c1b3e3fc360dd512e..4e6691032fa2714d9e381802cf2cfae89d1640f6 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -160,6 +160,9 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_reg_dp_xonoff_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
CONSTANT c_sdp_ram_st_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
+ -- SST UDP offload MM address widths
+ CONSTANT c_sdp_reg_stat_enable_addr_w :NATURAL := 1;
+
-- 10GbE offload (cep = central processor)
CONSTANT c_sdp_cep_eth_src_mac_47_16 : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00228608"; -- 47:16, 15:8 = backplane, 7:0 = node
CONSTANT c_sdp_cep_ip_src_addr_31_16 : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"C0A8"; -- 31:16, 15:8 = backplane, 7:0 = node + 1 = 192.168.xx.yy
@@ -217,14 +220,26 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_reg_nw_10GbE_eth10g_addr_w : NATURAL := 1;
-- statistics offload
+ -- The statistics offload uses the same 1GbE port as the NiosII for M&C. The 1GbE addresses defined in SW and here in FW.
+ -- See NiosII code:
+ -- https://git.astron.nl/desp/hdl/-/blob/master/libraries/unb_osy/unbos_eth.h
+ -- https://git.astron.nl/desp/hdl/-/blob/master/libraries/unb_osy/unbos_eth.c
+ -- and g_base_ip = x"0A63" in:
+ -- https://git.astron.nl/desp/hdl/-/blob/master/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+
+ CONSTANT c_sdp_stat_eth_src_mac_47_16 : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00228608"; -- 00:22:86:08:pp:qq
+ CONSTANT c_sdp_stat_ip_src_addr_31_16 : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0A63"; -- 10.99.xx.yy
+ CONSTANT c_sdp_sst_udp_src_port_15_8 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D0"; -- TBC
+ CONSTANT c_sdp_bst_udp_src_port_15_8 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D1"; -- TBC
+ CONSTANT c_sdp_xst_udp_src_port_15_8 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D2"; -- TBC
+
CONSTANT c_sdp_stat_nof_hdr_fields : NATURAL := 3+12+4+20+1; -- 592b; 9.25 64b words
CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111001"&"0111"&"01000000000000000000"&"0"; -- 0=data path, 1=MM controlled TODO
CONSTANT c_sdp_stat_hdr_field_arr : t_common_field_arr(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := (
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"00074306C700") ), -- 00074306C700=DOP36-eth0
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B217176B9") ), -- 001B217176B9 = DOP36-enp2s0
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
-
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
@@ -236,16 +251,13 @@ PACKAGE sdp_pkg is
( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ), -- C0A80001=DOP36-eth0 '192.168.0.1'
-
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"0A6300FE") ), -- 0A6300FE = DOP36-enp2s0 '10.99.0.254'
( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(5001) ),
( field_name_pad("udp_total_length" ), "RW", 16, field_default(7848) ),
( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
-
( field_name_pad("sdp_marker" ), "RW", 8, field_default(0) ),
( field_name_pad("sdp_version_id" ), "RW", 8, field_default(5) ),
-
( field_name_pad("sdp_observation_id" ), "RW", 32, field_default(0) ),
( field_name_pad("sdp_station_id" ), "RW", 16, field_default(0) ),
( field_name_pad("sdp_source_info_antenna_band_id" ), "RW", 1, field_default(0) ),
@@ -257,7 +269,6 @@ PACKAGE sdp_pkg is
( field_name_pad("sdp_source_info_subband_calibrated_flag" ), "RW", 1, field_default(0) ),
( field_name_pad("sdp_source_info_reserved" ), "RW", 3, field_default(0) ),
( field_name_pad("sdp_source_info_gn_id" ), "RW", 5, field_default(0) ),
-
( field_name_pad("sdp_reserved" ), "RW", 8, field_default(0) ),
( field_name_pad("sdp_integration_interval" ), "RW", 24, field_default(0) ),
( field_name_pad("sdp_data_id" ), "RW", 32, field_default(0) ),
@@ -265,9 +276,11 @@ PACKAGE sdp_pkg is
( field_name_pad("sdp_nof_bytes_per_statistics" ), "RW", 8, field_default(8) ),
( field_name_pad("sdp_nof_statistics_per_packet" ), "RW", 16, field_default(0) ),
( field_name_pad("sdp_block_period" ), "RW", 16, field_default(0) ),
-
( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
);
+ CONSTANT c_sdp_reg_stat_hdr_dat_addr_w : NATURAL := ceil_log2(field_nof_words(c_sdp_stat_hdr_field_arr, c_word_w));
+
+
END PACKAGE sdp_pkg;
PACKAGE BODY sdp_pkg IS
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index 582ed069d69311742e4a36aa452d2eef873a7c33..db4e7fcdedd96752fe4b8dcc3b35f06a780ee062 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -113,28 +113,31 @@ ARCHITECTURE str OF sdp_statistics_offload IS
CONSTANT c_beamlet_id : NATURAL := g_beamset_id * c_sdp_S_sub_bf;
TYPE t_reg IS RECORD
- block_count : NATURAL;
- start_address : NATURAL;
- start_pulse : STD_LOGIC;
- dp_header_info : STD_LOGIC_VECTOR(1023 DOWNTO 0);
- data_id : STD_LOGIC_VECTOR(31 DOWNTO 0);
- nof_cycles_dly : NATURAL;
- payload_err : STD_LOGIC;
- interval_cnt : NATURAL;
+ block_count : NATURAL;
+ start_address : NATURAL;
+ start_pulse : STD_LOGIC;
+ dp_header_info : STD_LOGIC_VECTOR(1023 DOWNTO 0);
+ data_id : STD_LOGIC_VECTOR(31 DOWNTO 0);
+ nof_cycles_dly : NATURAL;
+ payload_err : STD_LOGIC;
+ interval_cnt : NATURAL;
+ integration_interval : NATURAL;
END RECORD;
- CONSTANT c_reg_rst : t_reg := (0, 0, '0', (OTHERS => '0'), (OTHERS => '0'), 0, '0', 0);
+ CONSTANT c_reg_rst : t_reg := (0, 0, '0', (OTHERS => '0'), (OTHERS => '0'), 0, '0', 0, 0);
- SIGNAL r : t_reg;
- SIGNAL d : t_reg;
+ SIGNAL r : t_reg;
+ SIGNAL nxt_r : t_reg;
SIGNAL trigger : STD_LOGIC := '0';
SIGNAL mm_done : STD_LOGIC := '0';
SIGNAL dp_block_from_mm_src_out : t_dp_sosi;
SIGNAL dp_block_from_mm_src_in : t_dp_siso;
+ SIGNAL dp_offload_snk_in : t_dp_sosi;
+ SIGNAL dp_offload_snk_out : t_dp_siso;
+
SIGNAL dp_header_info : STD_LOGIC_VECTOR(1023 DOWNTO 0):= (OTHERS => '0');
- SIGNAL integration_interval : NATURAL := 0;
SIGNAL bsn_at_sync : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
--SIGNAL sdp_data_id : STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -163,7 +166,7 @@ BEGIN
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_reserved" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_reserved" )) <= (OTHERS => '0');
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_gn_id" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_gn_id" )) <= TO_UVEC(gn_index, 5);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_reserved" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_reserved" )) <= (OTHERS => '0');
- dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_integration_interval" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_integration_interval" )) <= TO_UVEC(integration_interval, 24);
+ dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_integration_interval" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_integration_interval" )) <= TO_UVEC(r.integration_interval, 24);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_data_id" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_data_id" )) <= r.data_id;
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_nof_signal_inputs" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_nof_signal_inputs" )) <= TO_UVEC(c_nof_signal_inputs, 8);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_nof_statistics_per_packet" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_nof_statistics_per_packet" )) <= TO_UVEC(c_nof_statistics_per_packet, 16);
@@ -175,69 +178,71 @@ BEGIN
IF dp_rst='1' THEN
r <= c_reg_rst;
ELSIF rising_edge(dp_clk) THEN
- r <= d;
+ r <= nxt_r;
END IF;
END PROCESS;
p_control_packet_offload : PROCESS(r, gn_index, in_sosi, trigger, mm_done, dp_header_info)
+ VARIABLE v: t_reg;
BEGIN
- d <= r;
- d.start_pulse <= '0';
- d.nof_cycles_dly <= gn_index * g_offload_time;
+ v := r;
+ v.start_pulse := '0';
+ v.nof_cycles_dly := gn_index * g_offload_time;
-- Count number of sop's in a sync interval and get payload errors and keep them till next sync.
IF in_sosi.sync = '1' THEN
- integration_interval <= r.interval_cnt;
- d.interval_cnt <= 0;
- d.payload_err <= '0';
+ v.integration_interval := r.interval_cnt;
+ v.interval_cnt := 0;
+ v.payload_err := '0';
ELSE
IF in_sosi.eop = '1' THEN
- d.payload_err <= r.payload_err OR in_sosi.err(0);
+ v.payload_err := r.payload_err OR in_sosi.err(0);
END IF;
IF in_sosi.sop = '1' THEN
- d.interval_cnt <= r.interval_cnt + 1;
+ v.interval_cnt := r.interval_cnt + 1;
END IF;
END IF;
-- assign sdp_data_id for different statistic types
IF g_statistics_type = "SST" THEN
- d.data_id <= x"000000" & TO_UVEC(r.block_count + c_sdp_S_pn * gn_index, 8);
+ v.data_id := x"000000" & TO_UVEC(r.block_count + c_sdp_S_pn * gn_index, 8);
ELSIF g_statistics_type = "BST" THEN
- d.data_id <= x"0000" & TO_UVEC(c_beamlet_id, 16);
+ v.data_id := x"0000" & TO_UVEC(c_beamlet_id, 16);
ELSIF g_statistics_type = "XST" THEN
- d.data_id <= x"00" & TO_UVEC(0, 8) & TO_UVEC(0, 8) & TO_UVEC(0, 8); -- TODO: fill in right values for XST.
+ v.data_id := x"00" & TO_UVEC(0, 8) & TO_UVEC(0, 8) & TO_UVEC(0, 8); -- TODO: fill in right values for XST.
ELSE
- d.data_id <= x"00000000";
+ v.data_id := x"00000000";
END IF;
-- Issue start_pulse per packet offload
IF trigger = '1' THEN
-- Use trigger to start first packet
- d.start_pulse <= '1';
- d.start_address <= 0;
- d.block_count <= 1;
+ v.start_pulse := '1';
+ v.start_address := 0;
+ v.block_count := 1;
ELSIF mm_done = '1' THEN
-- Use mm_done to start next packets
IF r.block_count < c_nof_packets THEN
IF r.block_count MOD c_nof_data_per_step = 0 THEN
- d.start_address <= r.start_address + c_data_size; -- step to next packet within block
+ v.start_address := r.start_address + c_data_size; -- step to next packet within block
ELSE
- d.start_address <= r.block_count / c_nof_data_per_step * c_block_size; -- jump to first packet in next block
+ v.start_address := r.block_count / c_nof_data_per_step * c_block_size; -- jump to first packet in next block
END IF;
- d.start_pulse <= '1';
- d.block_count <= r.block_count + 1;
+ v.start_pulse := '1';
+ v.block_count := r.block_count + 1;
ELSE
-- Prepare for next trigger interval.
- d.start_address <= 0;
- d.block_count <= 0;
+ v.start_address := 0;
+ v.block_count := 0;
END IF;
END IF;
-- Release header info per packet offload
IF trigger = '1' OR mm_done = '1' THEN
- d.dp_header_info <= dp_header_info;
+ v.dp_header_info := dp_header_info;
END IF;
+ nxt_r <= v;
END PROCESS;
u_mms_common_variable_delay : ENTITY common_lib.mms_common_variable_delay
@@ -274,6 +279,18 @@ BEGIN
out_siso => dp_block_from_mm_src_in
);
+ u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready
+ PORT MAP(
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => dp_block_from_mm_src_in,
+ snk_in => dp_block_from_mm_src_out,
+ -- ST source
+ src_in => dp_offload_snk_out,
+ src_out => dp_offload_snk_in
+ );
+
u_dp_offload_tx_v3: ENTITY dp_lib.dp_offload_tx_v3
GENERIC MAP (
g_nof_streams => c_nof_streams,
@@ -290,8 +307,8 @@ BEGIN
dp_clk => dp_clk,
reg_hdr_dat_mosi => reg_hdr_dat_mosi,
reg_hdr_dat_miso => reg_hdr_dat_miso,
- snk_in_arr(0) => dp_block_from_mm_src_out,
- snk_out_arr(0) => dp_block_from_mm_src_in,
+ snk_in_arr(0) => dp_offload_snk_in,
+ snk_out_arr(0) => dp_offload_snk_out,
src_out_arr(0) => out_sosi,
src_in_arr(0) => out_siso,
hdr_fields_in_arr(0) => r.dp_header_info
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
index f4048ce943ae6316fed63f8e36c872739867ecd5..fe03722c40bc586c45be832055c6648b1bc144fe 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
@@ -83,23 +83,25 @@ BEGIN
cnt <= 0;
v_Q_fft := 0;
v_N_sub := 0;
- ELSIF rising_edge(dp_clk) AND in_sosi_arr(0).valid = '1' THEN
- IF in_sosi_arr(0).eop = '1' THEN
- v_Q_fft := 0;
- v_N_sub := 0;
- ELSE
- IF v_Q_fft >= c_sdp_Q_fft-1 THEN
+ ELSIF rising_edge(dp_clk) THEN
+ IF in_sosi_arr(0).valid = '1' THEN
+ IF in_sosi_arr(0).eop = '1' THEN
v_Q_fft := 0;
- IF v_N_sub >= c_sdp_N_sub-1 THEN
- v_N_sub := 0;
+ v_N_sub := 0;
+ ELSE
+ IF v_Q_fft >= c_sdp_Q_fft-1 THEN
+ v_Q_fft := 0;
+ IF v_N_sub >= c_sdp_N_sub-1 THEN
+ v_N_sub := 0;
+ ELSE
+ v_N_sub := v_N_sub + 1;
+ END IF;
ELSE
- v_N_sub := v_N_sub + 1;
+ v_Q_fft := v_Q_fft + 1;
END IF;
- ELSE
- v_Q_fft := v_Q_fft + 1;
END IF;
+ cnt <= v_Q_fft * c_sdp_N_sub + v_N_sub;
END IF;
- cnt <= v_Q_fft * c_sdp_N_sub + v_N_sub;
END IF;
END PROCESS;
gains_rd_address <= TO_UVEC(cnt, c_gain_addr_w);
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml
index fbb717f3be92bedc7edc2edf2c8f484da390c21b..64ecbf278f19b1d721781f8656e88c3168a46dc2 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml
@@ -10,29 +10,29 @@ fpga_description: |
peripherals:
- peripheral_name: unb1_board/system
- slave_port_names:
+ mm_port_names:
- pio_system_info
lock_base_address: 0x0
- peripheral_name: unb1_board/rom_system
- slave_port_names:
+ mm_port_names:
- rom_system_info
lock_base_address: 0x1000
- peripheral_name: unb1_board/ctrl
- slave_port_names:
+ mm_port_names:
- pio_wdi
- peripheral_name: unb1_board/wdi
- slave_port_names:
+ mm_port_names:
- reg_wdi
- peripheral_name: eth/eth1g
- slave_port_names:
+ mm_port_names:
- avs_eth_0_tse
- avs_eth_0_reg
- avs_eth_0_ram
- peripheral_name: ppsh/ppsh
- slave_port_names:
+ mm_port_names:
- pio_pps
- peripheral_name: epcs/epcs
- slave_port_names:
+ mm_port_names:
- reg_epcs
- reg_dpmm_ctrl
- reg_dpmm_data
@@ -41,10 +41,10 @@ peripherals:
parameter_overrides:
- { name : g_sim_flash_model, value: FALSE }
- peripheral_name: remu/remu
- slave_port_names:
+ mm_port_names:
- reg_remu
- peripheral_name: unb1_board/sens
- slave_port_names:
+ mm_port_names:
- reg_unb_sens
parameter_overrides:
- { name : g_sim, value: FALSE }
diff --git a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
index eb6ec2e24c49510c75a88a64aa6432fbab490f5d..e85ac86d90071a13a312f2a805e5a9ac0be32bba 100644
--- a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
+++ b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
@@ -5,14 +5,14 @@ schema_type : peripheral
hdl_library_name : unb1_board
hdl_library_description: " This is the description for the unb1_board package "
-# <peripheral_group>_<peripheral_name>_<slave_name>_<slave_type>
+# <peripheral_group>_<peripheral_name>_<mm_port_name>_<mm_port_type>
peripherals:
- peripheral_name: rom_system
- slave_ports:
+ mm_ports:
# rom_system_info
- - slave_name : info
- slave_type : REG
+ - mm_port_name : info
+ mm_port_type : REG
fields:
- - field_name : info
access_mode : RO
@@ -20,16 +20,16 @@ peripherals:
number_of_fields: 1024
field_description: |
"address place for rom_system_info"
- slave_description: " rom_info "
+ mm_port_description: " rom_info "
peripheral_description: |
" settings for rom_system_info register "
- peripheral_name: system
- slave_ports:
+ mm_ports:
# reg_system_info
- - slave_name : info
- slave_type : REG
+ - mm_port_name : info
+ mm_port_type : REG
fields:
- - field_name : info
access_mode : RO
@@ -37,7 +37,7 @@ peripherals:
number_of_fields: 32
field_description: |
"address place for reg_system_info"
- slave_description: " reg_info "
+ mm_port_description: " reg_info "
peripheral_description: |
" settings for reg_system_info register "
@@ -45,10 +45,10 @@ peripherals:
# peripheral, unb1_board_wdi_reg
- peripheral_name: ctrl
- slave_ports:
+ mm_ports:
# actual hdl name: unb1_board_wdi_reg
- - slave_name : pio_wdi
- slave_type : REG
+ - mm_port_name : pio_wdi
+ mm_port_type : REG
fields:
- - field_name : nios_reset
width : 32
@@ -57,24 +57,24 @@ peripherals:
number_of_fields: 1
field_description: " Reset done by nios "
- slave_description: "Reset register, for nios "
+ mm_port_description: "Reset register, for nios "
peripheral_description: " "
# peripheral, unb1_board_wdi_reg
- peripheral_name: wdi
- slave_ports:
+ mm_ports:
# actual hdl name: unb1_board_wdi_reg
- - slave_name : wdi
- slave_type : REG
+ - mm_port_name : wdi
+ mm_port_type : REG
fields:
- - field_name : reset_word
access_mode : WO
address_offset: 0x0
field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset "
- slave_description: "Reset register, if the right value is provided the factory image will be reloaded "
+ mm_port_description: "Reset register, if the right value is provided the factory image will be reloaded "
peripheral_description: " "
@@ -86,10 +86,10 @@ peripherals:
- { name: g_clk_freq, value: c_unb1_board_mm_clk_freq_125M }
- { name: g_temp_high, value: 85 }
- slave_ports:
+ mm_ports:
# actual hdl name: reg_unb1_sens
- - slave_name : sens
- slave_type : REG
+ - mm_port_name : sens
+ mm_port_type : REG
fields:
- - field_name : sens_data
width : 8
@@ -117,7 +117,7 @@ peripherals:
software_value: g_temp_high
field_description: ""
- slave_description: " "
+ mm_port_description: " "
peripheral_description: |
"
diff --git a/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml b/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
index 2392b58d94d2c2a1da2907be7156ea136f19db8b..01243fd42502200dbbc1ec823b7c66f6cb3da100 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
+++ b/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
@@ -4,46 +4,56 @@ schema_type : fpga
hdl_library_name: unb2b_minimal
fpga_name : unb2b_minimal
-fpga_description: "unb2b_minimal system"
+fpga_description: "FPGA design unb2b_minimal"
peripherals:
- - peripheral_name: unb2b_board/unb2b
- slave_port_names:
- - rom_system_info
- - pio_system_info
- - pio_wdi
- - reg_wdi
- - reg_unb_sens
- - reg_unb_pmbus
- - reg_fpga_temp_sens
- - reg_fpga_voltage_sens
- - ram_scrap
- parameter_overrides:
- - { name : g_sim, value: FALSE }
- - { name : g_clk_freq, value: 125E6 }
- - { name : g_temp_high, value: 85 }
+ #############################################################################
+ # Factory / minimal (from ctrl_unb2b_board.vhd)
+ #############################################################################
+ - peripheral_name: unb2b_board/system_info
+ mm_port_names:
+ - ROM_SYSTEM_INFO
+ - PIO_SYSTEM_INFO
+ lock_base_address: 0x10000
- lock_base_address: 0x0
- lock_base_address: 0x4000
+ - peripheral_name: unb2b_board/wdi
+ mm_port_names:
+ - PIO_WDI
- - peripheral_name: eth/eth1g
- slave_port_names:
- - avs_eth_0_tse
- - avs_eth_0_reg
- - avs_eth_0_ram
+ - peripheral_name: unb2b_board/unb2_fpga_sens
+ mm_port_names:
+ - REG_FPGA_TEMP_SENS
+ - REG_FPGA_VOLTAGE_SENS
+
+ - peripheral_name: unb2b_board/ram_scrap
+ mm_port_names:
+ - RAM_SCRAP
+
+ - peripheral_name: eth/eth
+ mm_port_names:
+ - AVS_ETH_0_TSE
+ - AVS_ETH_0_REG
+ - AVS_ETH_0_RAM
+
- peripheral_name: ppsh/ppsh
- slave_port_names:
- - pio_pps
+ mm_port_names:
+ - PIO_PPS
+
- peripheral_name: epcs/epcs
- slave_port_names:
- - reg_epcs
- - reg_dpmm_ctrl
- - reg_dpmm_data
- - reg_mmdp_ctrl
- - reg_mmdp_data
- parameter_overrides:
- - { name : g_sim_flash_model, value: FALSE }
+ mm_port_names:
+ - REG_EPCS
+
+ - peripheral_name: dp/dpmm
+ mm_port_names:
+ - REG_DPMM_CTRL
+ - REG_DPMM_DATA
+
+ - peripheral_name: dp/mmdp
+ mm_port_names:
+ - REG_MMDP_CTRL
+ - REG_MMDP_DATA
+
- peripheral_name: remu/remu
- slave_port_names:
- - reg_remu
-
\ No newline at end of file
+ mm_port_names:
+ - REG_REMU
+
diff --git a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
index deb6b4075deda0f37549e77c642d34924f08ab42..254ac5e1c7e182c50a91e78df03f08789fb39790 100644
--- a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
+++ b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
@@ -3,122 +3,174 @@ schema_name: args
schema_version: 1.0
schema_type: peripheral
-hdl_library_name : unb2b_board
-hdl_library_description: " This is the description for the unb2b_board package "
-
-# <peripheral_group>_<peripheral_name>_<slave_name>_<slave_type>
+hdl_library_name: unb2b_board # ctrl_unb2b_board.vhd
+hdl_library_description: "Peripherals in unb2b_board."
peripherals:
-
- - peripheral_name: unb2b
- parameters:
- - { name: g_sim, value: FALSE }
- - { name: g_clk_freq, value: c_unb2b_board_mm_clk_freq_125M }
- - { name: g_temp_high, value: 85 }
-
- slave_ports:
- # rom_system_info
- - slave_name : rom_system
- slave_type : REG
+ - peripheral_name: ram_scrap # pi_ram_scrap.py
+ peripheral_description: ""
+ mm_ports:
+ # MM port for common_ram_r_w.vhd
+ - mm_port_name: RAM_SCRAP
+ mm_port_type: RAM
+ mm_port_description: "One memory mapped block RAM for MM access test purposes."
fields:
- - - field_name : info
- access_mode : RO
+ - - field_name: rw_data
+ field_description: "Void data"
+ access_mode: RW
address_offset: 0x0
- number_of_fields: 8192
- field_description: |
- "address place for rom_system_info"
- slave_description: " rom_info "
-
- # reg_system_info
- - slave_name : system
- slave_type : REG
+ number_of_fields: 512
+
+ - peripheral_name: system_info # pi_system_info.py
+ peripheral_description: ""
+ mm_ports:
+ # MM port for mms_unb2b_board_system_info.vhd / common_rom.vhd
+ - mm_port_name: ROM_SYSTEM_INFO # for c_rom_version = 1 in ctrl_unb2b_board.vhd
+ #- mm_port_name: ROM_SYSTEM_INFO_V2 # for c_rom_version = 2 in ctrl_unb2b_board.vhd
+ mm_port_type: RAM
+ mm_port_description: "Memory that stores the MM map system info of the mmap file."
fields:
- - - field_name : info
- access_mode : RO
+ - - field_name: ro_data
+ field_description: "FPGA info memory map data"
+ access_mode: RO
address_offset: 0x0
- number_of_fields: 32
- field_description: |
- "address place for reg_system_info"
- slave_description: " reg_info "
+ number_of_fields: 8192 # c_rom_addr_w in mms_unb2b_board_system_info
+ radix: char
- # actual hdl name: unb2b_board_wdi_reg
- - slave_name : ctrl
- slave_type : REG
+ # MM port for mms_unb2b_board_system_info.vhd / unb2b_board_system_info_reg.vhd
+ - mm_port_name: PIO_SYSTEM_INFO
+ mm_port_type: REG
+ mm_port_description: "FPGA design name, design note, version and location index info."
fields:
- - - field_name : nios_reset
- width : 32
- access_mode : WO
- address_offset : 0x0
- number_of_fields: 4
- field_description: " Reset done by nios "
-
- slave_description: "Reset register, for nios "
+ # All registers in one array
+ #- - field_name: info
+ # field_description: "FPGA info register, see pi_system_info.py for field details."
+ # access_mode: RO
+ # address_offset: 0x0
+ # number_of_fields: 32
- # actual hdl name: unb2b_board_wdi_reg
- - slave_name : wdi
- slave_type : REG
- fields:
- - - field_name : reset_word
- access_mode : WO
+ # Each field specified
+ - - field_name: info
+ field_description: "Info"
+ width: 32
+ bit_offset: 0
+ access_mode: RO
address_offset: 0x0
- field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset "
-
- slave_description: "Reset register, if the right value is provided the factory image will be reloaded "
-
- # actual hdl name: reg_unb2b_sens
- - slave_name : board_sens
- slave_type : REG
+ - "info": # field_group
+ - field_name: gn_index
+ field_description: "Global node index, unb2 FPGA id = gn_index % 4, unb2 backplane id = gn_index // 4"
+ width: 8
+ bit_offset: 0
+ access_mode: RO
+ address_offset: 0x0
+ - field_name: hw_version
+ field_description: "UniBoard2 hardware (HW) version."
+ width: 2
+ bit_offset: 8
+ access_mode: RO
+ address_offset: 0x0
+ - field_name: cs_sim
+ field_description: "0 when running on HW, 1 when running in simulation."
+ width: 1
+ bit_offset: 10
+ access_mode: RO
+ address_offset: 0x0
+ - field_name: fw_version_major
+ field_description: "FPGA Firmware (FW) version major number, not used use version stamp instead."
+ width: 4
+ bit_offset: 16
+ access_mode: RO
+ address_offset: 0x0
+ - field_name: fw_version_minor
+ field_description: "FPGA Firmware (FW) version minor number, not used use version stamp instead."
+ width: 4
+ bit_offset: 20
+ access_mode: RO
+ address_offset: 0x0
+ - field_name: rom_version
+ field_description: "Version of the mmap schema in ROM_SYSTEM_INFO."
+ width: 3
+ bit_offset: 24
+ access_mode: RO
+ address_offset: 0x0
+ - field_name: technology
+ field_description: "FPGA technology"
+ width: 5
+ bit_offset: 27
+ access_mode: RO
+ address_offset: 0x0
+ - - field_name: use_phy
+ field_description: "PHY interfaces that are active in the FPGA, not used."
+ width: 8
+ access_mode: RO
+ address_offset: 0x4
+ - - field_name: design_name
+ field_description: "FPGA FW design name string."
+ access_mode: RO
+ address_offset: 0x8
+ number_of_fields: 13
+ radix: char
+ radix_width: 8
+ - - field_name: stamp_date
+ field_description: "FPGA FW compile date string."
+ access_mode: RO
+ address_offset: 0x3C
+ number_of_fields: 1
+ - - field_name: stamp_time
+ field_description: "FPGA FW compile time string."
+ access_mode: RO
+ address_offset: 0x40
+ number_of_fields: 1
+ - - field_name: stamp_commit
+ field_description: "FPGA FW commit hash string."
+ access_mode: RO
+ address_offset: 0x44
+ number_of_fields: 3
+ radix: hexadecimal
+ - - field_name: design_note
+ field_description: "FPGA FW design note string."
+ access_mode: RO
+ address_offset: 0x50
+ number_of_fields: 13
+ radix: char
+ radix_width: 8
+
+ - peripheral_name: wdi # pi_wdi.py
+ peripheral_description: ""
+ mm_ports:
+ # MM port for unb2b_board_wdi_reg.vhd
+ - mm_port_name: REG_WDI
+ mm_port_type: REG
+ mm_port_description: "Reset register, if the right value is provided the factory image will be reloaded in the FPGA."
fields:
- - - field_name : sens
- width : 32
- access_mode : RO
- address_offset: 0x00
- number_of_fields: 41
- field_description: ""
- slave_description: " "
- - slave_name : board_pmbus
- slave_type : REG
- fields:
- - - field_name : pmbus
- width : 32
- access_mode : RO
- address_offset: 0x00
- number_of_fields: 43
- field_description: ""
- slave_description: " "
+ - - field_name: wdi_override
+ field_description: "Write value 0xB007FAC7 = 'Boot factory' to disable the watchdog interrupt (WDI), to cause an FPGA image reload."
+ access_mode: WO
+ address_offset: 0x0
- # actual hdl name: reg_unb2b_sens
- - slave_name : fpga_temp
- slave_type : REG
+ - peripheral_name: unb2_fpga_sens
+ peripheral_description: ""
+ mm_ports:
+ # MM ports for mms_unb2b_fpga_sens.vhd / unb2b_fpga_sens_reg.vhd
+ - mm_port_name: REG_FPGA_TEMP_SENS # pi_unb_fpga_sens.py
+ mm_port_type: REG
+ mm_port_description: |
+ "FPGA temperature = (AxC)/1024 - B (where A=708; B=273; C=adc value), see page 10 in
+ https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_alttemp_sense.pdf"
fields:
- - - field_name : temp
- width : 32
- access_mode : RO
- address_offset: 0x00
+ - - field_name: temp
+ field_description: "Raw data"
+ access_mode: RO
+ address_offset: 0x0
number_of_fields: 1
- field_description: ""
- slave_description: " "
- - slave_name : fpga_voltage
- slave_type : REG
- fields:
- - - field_name : voltage
- width : 32
- access_mode : RO
- address_offset: 0x00
- number_of_fields: 6
- field_description: ""
- slave_description: " "
-
- - slave_name : scrap_ram
- slave_type : RAM
+
+ - mm_port_name: REG_FPGA_VOLTAGE_SENS # pi_unb_fpga_voltagesens.py
+ mm_port_type: REG
+ mm_port_description: "Not used, FPGA voltages are monitored via DC-DC converter power supply volages"
fields:
- - - field_name: data
- width : 32
- access_mode: RW
- address_offset: 0x00
- number_of_fields: 128
- field_description: " "
- slave_description: " "
-
- peripheral_description: |
- ""
\ No newline at end of file
+ - - field_name: voltages
+ field_description: "Not used"
+ access_mode: RO
+ address_offset: 0x0
+ number_of_fields: 6
+
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index e7671f583dd855a8cf772464598ae3c1a087dd89..12cf2dacce1a83c871c0eb1679d3e35268145169 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -182,6 +182,8 @@ git add <dir>/<file> # add to stage area, set for commit. Cannot add empty
git add . # add all new and modified to stageing area
git diff # diff between file in working tree and staging area
git diff --staged # diff between file in staging area and history
+git difftool -t meld # GUI frontend for git diff, with --no-prompt to avoid Y/n prompt request to launch meld
+git difftool -t meld --no-prompt # e.g. define alias gitmeld
git rm <filename> # remove file from working tree and stage the delete
git checkout -- <filename> # revert a working tree change
git reset # clear stage area
@@ -373,72 +375,8 @@ for me it is an ok workaround,
* Markdown
*******************************************************************************
-Use e.g.:
-- Linux 'retext' as markdown editor and previewer.
-- https://typora.io, mooi maar waarscijnlijk te geavanceerd en daardoor niet
- compatible met andere viewers
-- Python3 --> import mdutil # markdown writer en reader
-
-Markdown is not well defined, so it is not always sure that the text will
-appear as expected in each viewer. For example retext and gitlab viewer differ.
-Therefore it is important to keep the markdown simple and to accept that
-readable text is good enough, rather than to strive for a specific layout.
-
-Text will wrap.
-
-Backslash is escape chararcter.
-
-# Heading 1
-## Heading 2
-### Heading 3
-#### Heading 4
-##### Heading 5
-###### Heading 6
-
-Horizontal rules three or more of ***, ___, ---
-
-*italic*
-_italic_
-**bold**
-__bold__
-**bold and _bolditalic_** combined
-`boxed`
-~~strike through~~
-
-```vhdl
-Text in ascii VHDL style for GitLab
-```
-
-Block quotes (alinea with an indent bar):
-> Block text will wrap
-
-Unordered list using *, -, +, indent >= 1 space
-* Main item 1
-* Main item 2
- * sub item 2a use 2 trailing spaces for return inside paragraph
- * sub item 2b
-
-Ordered list
-1. Main item 1
-2. Main item 2
- 2.1 sub item 2a
- 2.2 sub item 2b
-
-Images
-
-
-![Logo][image1]
-
-[image1]:web link to image file
-
-Links:
-[ASTRON]:https://www.astron.nl
-
-Table:
-|col1 | col2| Col3 | column titles
-|---|:---:|--:| >= 3 dashes, colon for left, center, right align
-| row text | row text | row text|
-| row text | row text | row text|
+See https://git.astron.nl/desp/args/Markdown/readme_markdown.txt
+
*******************************************************************************
* vi
@@ -481,6 +419,10 @@ bcksp |
Note: Windows NTSERVER65 has IP: 10.87.3.165
+* Login using ssh keys:
+
+https://www.digitalocean.com/community/tutorials/how-to-configure-ssh-key-based-authentication-on-a-linux-server
+
* For ssh access from home without manual hop via the kooistra@portal.astron.nl, put this in $HOME/.ssh/config:
Host *
@@ -705,8 +647,12 @@ Quartus version meeting minutes 13 may 2020 (RW, LH JH, EK):
* Linux
*******************************************************************************
+https://regexr.com/
+
https://linuxize.com/
+> passwd
+
# Linux update via
# - system updates available icon and notifications icon in toolbar
# - of via command line:
@@ -822,3 +768,6 @@ https://intranet.astron.nl/diensten/ict/manuals-and-documents/manuals-and-docume
pycharm
https://pypi.org/project/black/ # Python code formatter
+
+numpy tutorial:
+https://lwn.net/SubscriberLink/847039/3016fa7278000b77/
diff --git a/libraries/base/common/common.peripheral.yaml b/libraries/base/common/common.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..b9ad15bbbc80f89fafefa2a7b4e206061810d813
--- /dev/null
+++ b/libraries/base/common/common.peripheral.yaml
@@ -0,0 +1,26 @@
+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: common
+hdl_library_description: "Common peripherals for common logic and memory."
+
+peripherals:
+ - peripheral_name: common_variable_delay # pi_common_variable_delay.py ???
+ peripheral_description: |
+ "The common_variable_delay.vhd logic can delay an input pulse by a number of clock cycles.
+ The delay depends on an internal signal input, such that it the delay is not fixed, but
+ can be different for different instances.
+ The delay is not programmable, but delayed output pulse can be enabled when enable = 1
+ or disabled when enable = 0."
+ mm_ports:
+ # MM port for mms_common_variable_delay.vhd / mms_common_reg.vhd
+ - mm_port_name: REG_COMMON_VARIABLE_DELAY
+ mm_port_type: REG
+ mm_port_description: ""
+ fields:
+ - - field_name: enable
+ field_description: "When 1 pass on delayed pulse to the output, else disable the output pulse."
+ width: 1
+ access_mode: RW
+ address_offset: 0x0
diff --git a/libraries/base/common/src/vhdl/common_variable_delay.vhd b/libraries/base/common/src/vhdl/common_variable_delay.vhd
index 8d4c8f65e3be65b5320b083d4d8b57a76b60a48f..847bb54e531d2bc300783c1f2431f25fcef1b97f 100644
--- a/libraries/base/common/src/vhdl/common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_variable_delay.vhd
@@ -57,7 +57,7 @@ ARCHITECTURE rtl OF common_variable_delay IS
BEGIN
out_val <= i_out_val;
- p_delay: PROCESS(in_val, prev_in_val, delay, delay_cnt)
+ p_delay: PROCESS(enable, in_val, prev_in_val, delay, delay_cnt)
BEGIN
nxt_out_val <= '0';
nxt_delay_cnt <= 0;
diff --git a/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd b/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
index ed05567afea3e20e1cc29ab8bb00c9f48a765e50..50a10a41eb102ef7be497679191e7676cd9989bb 100644
--- a/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
@@ -58,7 +58,7 @@ ARCHITECTURE rtl OF mms_common_variable_delay IS
SIGNAL enable : STD_LOGIC := '0';
BEGIN
- enable <= sl(enable_reg);
+ enable <= sl(enable_reg);
-- device under test
u_dut : ENTITY work.common_variable_delay
diff --git a/libraries/base/diag/diag.peripheral.yaml b/libraries/base/diag/diag.peripheral.yaml
index 3f82d004c53a60e4f4eb608860ecb6ee5fa36cb7..c92c4a5823e36e62d9b5d26da9d022fb043b7b96 100644
--- a/libraries/base/diag/diag.peripheral.yaml
+++ b/libraries/base/diag/diag.peripheral.yaml
@@ -1,245 +1,97 @@
-schema_name : args
+schema_name: args
schema_version: 1.0
-schema_type : peripheral
+schema_type: peripheral
-hdl_library_name : diag
-hdl_library_description: " This is the description for the bf package "
+hdl_library_name: diag
+hdl_library_description: "Diagnostics (DIAG) peripherals data generation and data capturing."
peripherals:
- -
- peripheral_name: block_gen
-
+ - peripheral_name: diag_wg_wideband # pi_diag_wg_wideband.py
+ peripheral_description: "Waveform generator (WG), see diag_wg.vhd"
parameters:
+ # Parameters of mms_diag_wg_wideband_arr.vhd
- { name: g_nof_streams, value: 1 }
- - { name: g_buf_dat_w , value: 32 }
- - { name: g_buf_addr_w , value: 7 }
-
- slave_ports:
- # actual hdl name: reg_diag_bg
- - slave_name : ctrl
- slave_type : REG
+ mm_ports:
+ # MM port for diag_wg_wideband_reg.vhd
+ - mm_port_name: REG_DIAG_WG
+ mm_port_description: "Waveform control."
+ mm_port_type: REG
+ number_of_mm_ports: g_nof_streams
fields:
- - - field_name : Enable
- width : 2
+ - - field_name: nof_samples
+ field_description: "Number of samples in WG period."
+ width: 16
+ bit_offset: 16
address_offset: 0x0
+ - - field_name: mode
field_description: |
- "Bit 0: enable the block generator Bit 1: enable the blok generator on PPS"
-
- - - field_name : Samples_per_packet
- width : 16
+ "WG mode:
+ 0 = off
+ 1 = calc, uses WG buffer waveform to output sinus with ampl * sin(freq * t + phase
+ 2 = repeat, outputs WG buffer waveform repeatedly
+ 3 = single, outputs WG buffer waveform once"
+ width: 8
+ bit_offset: 0
+ address_offset: 0x0
+ - - field_name: phase
+ field_description: "Phase of WG sinus, phase = int('phase in degrees' * 2**width / 360)."
+ width: 16
+ bit_offset: 0
address_offset: 0x4
- reset_value : 256
- field_description: |
- "This REG specifies the number samples in a packet"
-
- - - field_name : Blocks_per_sync
- width : 16
+ - - field_name: freq
+ field_description: "Frequency of WG sinus, freq = int('frequency in range 0 to 1' * f_adc * 2**width), where f_adc is sample frequency in Hz."
+ width: 31
+ bit_offset: 0
address_offset: 0x8
- reset_value : 781250
- field_description: |
- "This REG specifies the number of packets in a sync period"
-
- - - field_name : Gapsize
- width : 16
- address_offset: 0xc
- reset_value : 80
- field_description: |
- "This REG specifies the gap in number of clock cycles between two consecutive packets"
-
- - - field_name : Mem_low_address
- width : 8
- address_offset: 0x10
- field_description: |
- "This REG specifies the starting address for reading from the waveform memory"
-
- - - field_name : Mem_high_address
- width : 8
- address_offset: 0x14
- field_description: |
- "This REG specifies the last address to be read when from the waveform memory"
-
- - - field_name : BSN_init_low
- address_offset: 0x18
- field_description: |
- "This REG specifies the lower(LSB) 32 bits [31:0] of the initialization BSN"
-
- - - field_name : BSN_init_high
- address_offset: 0x1c
- field_description: |
- "This REG specifies the higher(MSB) 32 bits [63:32] of the initialization BSN"
- slave_description: ""
-
- # actual hdl name: ram_diag_bg
- - slave_name : wave_data
- number_of_slaves: g_nof_streams
- slave_type : RAM
+ - - field_name: ampl
+ field_description: "Amplitude of WG sinus, ampl = int('amplitude in range 0 to 2' * 2**(width-1), where amplitude > 1 causes clipping."
+ width: 17
+ bit_offset: 0
+ address_offset: 0xC
+ # MM port for mms_diag_wg_wideband.vhd
+ - mm_port_name: RAM_DIAG_WG
+ mm_port_description: "Waveform buffer."
+ mm_port_type: RAM
+ number_of_mm_ports: g_nof_streams
fields:
- - - field_name: diag_bg
- width: g_buf_dat_w
- number_of_fields: 2**g_buf_addr_w
- field_description : |
- "Contains the Waveform data for the data-streams to be send"
- slave_description: ""
- peripheral_description: |
- "Block generator"
-
- - peripheral_name: data_buffer
+ - - field_name: data
+ field_description: "Waveform default is one sinus period (diag_sin_1024x18.hex)."
+ width: 18 # = c_wg_buf_dat_w in node_adc_input_and_timing.vhd
+ address_offset: 0x0
+ number_of_fields: 1024 # = 2**c_wg_buf_addr_w in node_adc_input_and_timing.vhd
+ - peripheral_name: diag_data_buffer # pi_diag_data_buffer.py
+ peripheral_description: "Data buffer (DB)"
parameters:
- - { name: g_nof_streams , value: 1 }
- - { name: g_data_w , value: 32 }
- - { name: g_buf_nof_data, value: 1024 }
-
- slave_ports:
- # actual hdl name: reg_diag_data_buffer
- - slave_name : status
- slave_type : REG
+ # Parameters of mms_diag_data_buffer.vhd
+ - { name: g_nof_streams, value: 1 }
+ - { name: g_data_w, value: 16 }
+ - { name: g_nof_data, value: 1024 }
+ - { name: g_use_in_sync, value: True }
+ mm_ports:
+ # MM port for mms_diag_data_buffer.vhd
+ - mm_port_name: REG_DIAG_DB
+ mm_port_description: "Data buffer status."
+ mm_port_type: REG
+ number_of_mm_ports: g_nof_streams
fields:
- - - field_name : Sync_cnt
- access_mode : RO
+ - - field_name: sync_cnt
+ field_description: "Number of times the DB has been written."
+ access_mode: RO
address_offset: 0x0
- field_description: |
- "Sync_cnt contains the nof times the buffer (ST) has received a sync pulse since the last MM read
- (cleared when the last data word from the buffer is read)"
-
- - - field_name : Word_cnt
- access_mode : RO
+ - - field_name: word_cnt
+ field_description: "Number data words in the DB."
+ access_mode: RO
address_offset: 0x4
- field_description: |
- "Word_cnt indicates the number of word currently (ST) written in the buffer. Cleared on (ST) re-write of buffer."
-
- - - field_name : Valid_cnt_arm_ena
- address_offset: 0x8
- field_description: |
- "Valid_cnt contains the number of valid cycles since the last sync pulse. Cleared on every sync pulse.
- Arm_enable: Write to this REG to arm the system.
- After the system is armed the next syn pulse will trigger the acquisition of data."
-
- - - field_name : Reg_sync_delay
- address_offset: 0xc
- field_description: |
- "Reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
- before the data is written to the databuffer."
-
- - - field_name : Version
- access_mode : RO
- address_offset: 0x1c
- field_description: |
- "Version contains the version number of the databuffer peripheral."
- slave_description: ""
- # actual hdl name: ram_diag_data_buffer
- - slave_name : data
- number_of_slaves: g_nof_streams
- slave_type : RAM
+ # MM port for mms_diag_data_buffer.vhd
+ - mm_port_name: RAM_DIAG_DB
+ mm_port_description: "Data buffer memory, gets filled after the sync when g_use_in_sync = True, else after the last word was read."
+ mm_port_type: RAM
+ number_of_mm_ports: g_nof_streams
fields:
- - - field_name : ram
- width : g_data_w
- number_of_fields: g_buf_nof_data
- field_description: |
- "Contains the data that is being captured."
- slave_description: ""
-
- peripheral_description: |
- "Peripheral diag_data_buffer
-
- Memory map RAM_DIAG_DATA_BUFFER
-
- If there is only one instance then the RAM name is RAM_DIAG_DATA_BUFFER, else it
- gets an instanceName as post fix so RAM_DIAG_DATA_BUFFER_<instanceName|.
-
- The diag_data_buffer can store multiple streams in parallel. For example
- 1024 data words for 16 streams the memory map becomes: 16
-
-
- streamNr = 0:
- +------------------------------------------------------------+
- | byte 3 | byte 2 | byte 1 | byte 0 | wi |
- |------------------------------------------------------------|
- | data_0[31:0] | 0 |
- | data_1[31:0] | 1 |
- | ... | .. |
- | data_1023[31:0] | 1023 |
- +------------------------------------------------------------+
-
-
- streamNr = 1:
- +------------------------------------------------------------+
- | byte 3 | byte 2 | byte 1 | byte 0 | wi |
- |------------------------------------------------------------|
- | data_0[31:0] | 1024 |
- | data_1[31:0] | 1025 |
- | ... | .. |
- | data_1023[31:0] | 2047 |
- +------------------------------------------------------------+
-
-
- streamNr = 15:
- +------------------------------------------------------------+
- | byte 3 | byte 2 | byte 1 | byte 0 | wi |
- |------------------------------------------------------------|
- | data_0[31:0] | 15360 |
- | data_1[31:0] | 15361 |
- | ... | .. |
- | data_1023[31:0] | 16383 |
- +------------------------------------------------------------+
-
-
- Remarks:
- - The data buffer stores valid data samples until it is full.
- - The data buffer fills again after an external sync pulse or after the
- last data word was read via the MM bus, dependend on whether the generic
- g_use_in_sync is TRUE or FALSE in diag_data_buffer.vhd.
- - The actual data width depends on the generic g_data_w in
- diag_data_buffer.vhd. The value of unused MSBits is undefined.
-
-
- Memory map REG_DIAG_DATA_BUFFER (one for each stream like the RAM above)
-
- +----------------------------------------------------------------------------+
- | byte 3 | byte 2 | byte 1 | byte 0 | wi |
- |----------------------------------------------------------------------------|
- | sync_cnt[31:0] | 0 RO (Version 0 and 1) |
- | word_cnt[31:0] | 1 RO (Version 0 and 1) |
- | R = valid_cnt[31:0] W = arm_enable | 2 RW (Version 1 only) |
- | reg_sync_delay[31:0] | 3 RW (Version 1 only) |
- | RESERVED | 4 (Version 1 only) |
- | RESERVED | 5 (Version 1 only) |
- | RESERVED | 6 (Version 1 only) |
- | version[31:0] | 7 RO (Version 1 only) |
- +----------------------------------------------------------------------------+
-
-
- There are 3 access_modes of operation of the data_buffer.
- Version 0 supports access_Mode 1 and access_Mode 2
- Version 1 supports access_Mode 1, access_Mode 2 and access_Mode 3
-
- (1) NON-SYNC access_MODE: g_use_in_sync = FALSE
- In this access_mode the first g_nof_data valid data input words are stored in the
- data buffer. A new set of data will be stored when the last word is read
- from the buffer via the MM interface.
-
- (2) SYNC-access_MODE: g_use_in_sync = TRUE and reg_sync_delay = 0
- On every received sync pulse a number of g_nof_data valid words are written
- to the databuffer. Data will be overwritten on every new sync pulse. It is
- up to the user to read out the data in time in between two sync pulses
-
- (3) ARM-access_MODE: g_use_in_sync = TRUE and reg_sync_delay | 0
- First the reg_sync_delay should be written with a desired delay value. Then
- the arm REG must be written. After being armed the databuffer will wait
- for the first sync pulse to arrive. When it has arrived it will wait for
- reg_sync_delay valid cycles before g_nof_data valid words are written to the
- databuffer. The data can then be read out through the MM interface. New data
- will only be written if the databuffer is being armed again.
-
- - Sync_cnt contains the nof times the buffer (ST) has received a sync pulse
- since the last MM read (cleared when the last data word from the buffer is
- read);
- - Word_cnt indicates the number of word currently (ST) written in the buffer.
- Cleared on (ST) re-write of buffer.
- - valid_cnt contains the number of valid cycles since the last sync pulse.
- Cleared on every sync pulse.
- - arm_enable. Write to this REG to arm the system. After the system is
- armed the next syn pulse will truigger the acquisition of data.
- - reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
- before the data is written to the databuffer.
- - version contains the version number of the databuffer peripheral."
+ - - field_name: data
+ field_description: ""
+ width: g_data_w
+ address_offset: 0x0
+ number_of_fields: g_nof_data
+
diff --git a/libraries/base/diag/src/vhdl/diag_pkg.vhd b/libraries/base/diag/src/vhdl/diag_pkg.vhd
index 3fcfd25e7a672339d7b64eadba90c940f9f2973d..7e86c097062f6904df20673a88b9cf38345ad566 100644
--- a/libraries/base/diag/src/vhdl/diag_pkg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_pkg.vhd
@@ -81,6 +81,9 @@ PACKAGE diag_pkg IS
CONSTANT c_diag_wg_gain_w : NATURAL := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
-- . use gain 2**0 = 1 to have fulle scale without clipping
-- . use gain 2**g_calc_gain_w > 1 to cause clipping
+ -- For c_diag_wg_gain_w = 1 there is clipping from [1 2> For normalized values >= 2**c_diag_wg_gain_w = 2
+ -- the behaviour becomes more or less undefined. Due to wrapping it appears that normalized values [2 3>
+ -- result in a sinus again. Therefore use normalized range [0 2**c_diag_wg_gain_w>.
CONSTANT c_diag_wg_ampl_unit : REAL := 2**REAL(c_diag_wg_ampl_w-c_diag_wg_gain_w)*c_diag_wg_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
CONSTANT c_diag_wg_freq_unit : REAL := 2**REAL(c_diag_wg_freq_w); -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
CONSTANT c_diag_wg_phase_unit : REAL := 2**REAL(c_diag_wg_phase_w)/ 360.0; -- ^= 1 degree
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index f015f5fcdb514a42c55bcf8e8bcd8ac4c0c5956d..2d2b0570c3c965e81927fb4b479bb79817c3d709 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -1,59 +1,370 @@
-schema_name : args
+schema_name: args
schema_version: 1.0
-schema_type : peripheral
+schema_type: peripheral
-hdl_library_name : dp
-hdl_library_description: " This is the description for the dp package "
+hdl_library_name: dp
+hdl_library_description: "Data path (DP) peripherals for streaming data."
peripherals:
- - peripheral_name: bsn
+ - peripheral_name: dpmm # pi_dpmm.py
+ peripheral_description: "DP to MM FIFO to provide memory mapped MM read access from Data Path (DP) streaming interface."
+ mm_ports:
+ # MM port for mms_dp_fifo_to_mm.vhd / dp_fifo_to_mm_reg.vhd
+ - mm_port_name: REG_DPMM_CTRL
+ mm_port_type: REG
+ mm_port_description: "DPMM = Monitor the DP to MM read FIFO."
+ fields:
+ - - field_name: rd_usedw
+ field_description: "Number of words that can be read from the FIFO."
+ access_mode: RO
+ address_offset: 0x0
+ # MM port for mms_dp_fifo_to_mm.vhd / dp_fifo_to_mm.vhd
+ - mm_port_name: REG_DPMM_DATA # Use REG_, instead of preferred FIFO_, to match mm_port_name in pi_dpmm.py
+ mm_port_type: FIFO
+ mm_port_description: "DPMM = read word from the DP to MM read FIFO"
+ fields:
+ - - field_name: rd_data
+ field_description: "Read data from the FIFO."
+ access_mode: RO
+ address_offset: 0x0
+
+
+ - peripheral_name: mmdp # pi_mmdp.py
+ peripheral_description: "MM to DP FIFO to provide memory mapped MM write access to Data Path (DP) streaming interface."
+ mm_ports:
+ # MM port for mms_dp_fifo_from_mm.vhd / dp_fifo_from_mm_reg.vhd
+ - mm_port_name: REG_MMDP_CTRL
+ mm_port_type: REG
+ mm_port_description: "MMDP = Monitor the MM to DP write FIFO."
+ fields:
+ - - field_name: wr_usedw
+ field_description: "Number of words that are in the write FIFO."
+ access_mode: RO
+ address_offset: 0x0
+
+ - - field_name: wr_availw
+ field_description: "Number of words that can be written to the write FIFO."
+ access_mode: RO
+ address_offset: 0x4
+ # MM port for mms_dp_fifo_from_mm.vhd / dp_fifo_from_mm.vhd
+ - mm_port_name: REG_MMDP_DATA # Use REG_, instead of preferred FIFO_, to match mm_port_name in pi_mmdp.py
+ mm_port_type: FIFO
+ mm_port_description: "MMDP = write word to the MM to DP write FIFO."
+ fields:
+ - - field_name: data
+ field_description: "Write data to the FIFO."
+ access_mode: WO
+ address_offset: 0x0
+
+
+ - peripheral_name: dp_xonoff # pi_dp_xonoff.py
+ peripheral_description: "Enable or disable a data path (DP) stream."
+ parameters:
+ # Parameters of mms_dp_xonoff.vhd
+ - { name: g_nof_streams, value: 1 }
+ - { name: g_combine_streams, value: False }
+ mm_ports:
+ # MM port for mms_dp_xonoff.vhd
+ - mm_port_name: REG_DP_XONOFF
+ mm_port_type: REG
+ mm_port_description: "When g_combine_streams = False then there is one enable bit per stream, else there is one enable bit for all streams."
+ fields:
+ - - field_name: enable_stream
+ field_description: |
+ "When enable_stream = 0 the data stream is stopped, else when 1 then the data stream is passed on.
+ Toggling the data stream on or off happens at block or packet boundaries."
+ width: 1
+ access_mode: RW
+ address_offset: 0x0
+ number_of_fields: 1 #g_nof_streams #sel_a_b(g_combine_streams, 1, g_nof_streams)
+
+ - peripheral_name: dp_shiftram # pi_dp_shiftram.py
+ peripheral_description: "Sample delay buffer with programmable delay for streaming data."
parameters:
- - { name: g_nof_input, value : 2 }
+ # Parameters of dp_shiftram.vhd
+ - { name: g_nof_streams, value: 1 }
+ - { name: g_nof_words, value: 1024 }
+ - { name: g_data_w, value: 16 }
+ mm_ports:
+ # MM port for dp_shiftram.vhd
+ - mm_port_name: REG_DP_SHIFTRAM
+ mm_port_type: REG
+ mm_port_description: ""
+ number_of_mm_ports: g_nof_streams
+ fields:
+ - - field_name: shift
+ field_description: "Fill level of the sample delay buffer in number of data samples."
+ width: ceil_log2(g_nof_words)
+ access_mode: RW
+ address_offset: 0x0
+
- slave_ports:
- # actual hdl name: reg_dp_bsn_align
- - slave_name : ALIGN
- number_of_slaves: g_nof_input
- slave_type : REG
+ - peripheral_name: dp_bsn_source # pi_dp_bsn_source.py
+ peripheral_description: "Block Sequence Number (BSN) source for timestamping blocks of data samples."
+ parameters:
+ # Parameters of dp_bsn_source_reg.vhd
+ - { name: g_nof_block_per_sync, value: 20 }
+ mm_ports:
+ # MM port for dp_bsn_source_reg.vhd
+ - mm_port_name: REG_DP_BSN_SOURCE
+ mm_port_type: REG
+ mm_port_description: ""
fields:
- - - field_name : Enable
- width : 1
- address_offset : 0x0
+ - - field_name: dp_on
field_description: |
- "Input enable register for input 0. If set to 0 the input is discarded from alignment.
- If set to 1 the corresopnding input is taken into account."
- slave_discription: " "
+ "When 1 then enable BSN source, else when 0 disable BSN source. If dp_on_pps is 0,
+ then dp_on = 1 enables the BSN source immediately. To enable the BSN source at
+ the next PPS, then first set dp_on_pps = 1. Clearing dp_on stops the BSN source."
+ width: 1
+ access_mode: RW
+ address_offset: 0x0
+ - - field_name: dp_on_pps
+ field_description: "When 1 and dp_on = 1 then enable BSN source at next PPS."
+ width: 1
+ bit_offset: 1
+ access_mode: RW
+ address_offset: 0x0
+ - - field_name: nof_block_per_sync
+ field_description: "Number of blocks per sync interval."
+ access_mode: RW
+ address_offset: 0x4
+ #- - field_name: bsn_lo
+ # field_description: "Initial BSN[31:0]"
+ # access_mode: RW
+ # address_offset: 0x8
+ #- - field_name: bsn_hi
+ # field_description: "Initial BSN[63:32]"
+ # access_mode: RW
+ # address_offset: 0xC
+ - - field_name: bsn
+ field_description: "Initial BSN"
+ access_mode: RW
+ address_offset: 0x8
+ radix_width: 64
- peripheral_description: "This is the BSN aligner"
- - peripheral_name: fifo
+ - peripheral_name: dp_bsn_source_v2 # pi_dp_bsn_source_v2.py
+ peripheral_description: "Block Sequence Number (BSN) source with block time offset, for timestamping blocks of data samples."
parameters:
- - { name : g_nof_streams, value: 3 }
-
- slave_ports:
- # actual hdl name: reg_dp_fifo_fill
- - slave_name : fill_status
- number_of_slaves: g_nof_streams
- slave_type : REG
- fields:
- - - field_name : fifo_used_words
- access_mode : RO
- address_offset : 0x0
- field_description: "Register reflects the currently used nof words on the fifo."
-
- - - field_name : fifo_status
- width : 2
- access_mode : RO
- address_offset : 0x4
- field_description: "Bit 0: fifo_read_empty Bit 1: fifo_wr_full."
-
- - - field_name : max_fifo_used_words
- access_mode : RO
- address_offset : 0x8
+ # Parameters of dp_bsn_source_reg_v2.vhd
+ - { name: g_nof_clk_per_sync, value: 200000000 }
+ - { name: g_block_size, value: 256 }
+ - { name: g_bsn_time_offset_w, value: 8 } # note: g_bsn_time_offset_w = ceil_log2(g_block_size)
+ mm_ports:
+ # MM port for dp_bsn_source_reg_v2.vhd
+ - mm_port_name: REG_DP_BSN_SOURCE_V2
+ mm_port_type: REG
+ mm_port_description: ""
+ fields:
+ - - field_name: dp_on
field_description: |
- "Register contains the maximum number of words that have been in the fifo.
- Will be cleared after it has been read."
- slave_discription: ""
+ "When 1 then enable BSN source, else when 0 disable BSN source. If dp_on_pps is 0,
+ then dp_on = 1 enables the BSN source immediately. To enable the BSN source at
+ the next PPS, then first set dp_on_pps = 1. Clearing dp_on stops the BSN source."
+ width: 1
+ access_mode: RW
+ address_offset: 0x0
+ - - field_name: dp_on_pps
+ field_description: "When 1 and dp_on = 1, then enable BSN source at next PPS."
+ width: 1
+ bit_offset: 1
+ access_mode: RW
+ address_offset: 0x0
+ - - field_name: nof_block_per_sync
+ field_description: "Number of clock cycles per sync interval."
+ access_mode: RW
+ address_offset: 0x4
+ #- - field_name: bsn_init_lo
+ # field_description: "Initial BSN[31:0]"
+ # access_mode: RW
+ # address_offset: 0x8
+ #- - field_name: bsn_init_hi
+ # field_description: "Initial BSN[63:32]"
+ # access_mode: RW
+ # address_offset: 0xC
+ - - field_name: bsn_init
+ field_description: "Initial BSN"
+ access_mode: RW
+ address_offset: 0x8
+ radix_width: 64
+ - - field_name: bsn_time_offset
+ field_description: "The BSN block time offset in number of clock cycles, with respect to the PPS."
+ width: g_bsn_time_offset_w
+ access_mode: RW
+ address_offset: 0x10
+
+
+ - peripheral_name: dp_bsn_scheduler # pi_dp_bsn_scheduler.py
+ peripheral_description: "Schedule a trigger at a certain Block Sequence Number (BSN) instant."
+ mm_ports:
+ # MM port for dp_bsn_scheduler_reg.vhd
+ - mm_port_name: REG_DP_BSN_SCHEDULER
+ mm_port_type: REG
+ mm_port_description: ""
+ fields:
+ #- - field_name: scheduled_bsn_lo
+ # field_description: "Write scheduled BSN lo, read current BSN lo. First access lo, then hi."
+ # access_mode: RW
+ # address_offset: 0x0
+ #- - field_name: scheduled_bsn_hi
+ # field_description: "Write scheduled BSN hi, read current BSN hi. First access lo, then hi."
+ # access_mode: RW
+ # address_offset: 0x4
+ - - field_name: scheduled_bsn
+ field_description: "Write scheduled BSN. First access lo, then hi."
+ access_mode: RW
+ address_offset: 0x0
+ radix_width: 64
+
+
+ - peripheral_name: dp_bsn_monitor # pi_dp_bsn_monitor.py
+ peripheral_description: "Monitor the Block Sequence Number (BSN) status of streaming data."
+ parameters:
+ # Parameters of mms_dp_bsn_monitor.vhd
+ - { name: g_nof_streams, value: 1 }
+ mm_ports:
+ # MM port for dp_bsn_monitor_reg.vhd
+ - mm_port_name: REG_DP_BSN_MONITOR
+ mm_port_type: REG
+ mm_port_description: ""
+ number_of_mm_ports: g_nof_streams
+ fields:
+ - - field_name: xon_stable
+ field_description: "Data block flow control xon signal was active and stable during last sync interval."
+ width: 1
+ bit_offset: 0
+ access_mode: RO
+ address_offset: 0x0
+ - - field_name: ready_stable
+ field_description: "Clock cycle flow control ready signal was active and stable during last sync interval."
+ width: 1
+ bit_offset: 1
+ access_mode: RO
+ address_offset: 0x0
+ - - field_name: sync_timeout
+ field_description: "Data stream sync did not occur during last sync interval."
+ width: 1
+ bit_offset: 2 # EK TODO: 2 is correct, but using 1 cause gen_doc.py to fail without clear error, because fields then overlap
+ access_mode: RO
+ address_offset: 0x0
+ #- - field_name: bsn_at_sync_lo
+ # field_description: "Data stream BSN lo at sync."
+ # access_mode: RO
+ # address_offset: 0x4
+ #- - field_name: bsn_at_sync_hi
+ # field_description: "Data stream BSN hi at sync."
+ # access_mode: RO
+ # address_offset: 0x8
+ - - field_name: bsn_at_sync
+ field_description: "Data stream BSN at sync."
+ access_mode: RO
+ address_offset: 0x4
+ radix_width: 64
+ - - field_name: nof_sop
+ field_description: "Number data blocks (sop = start of packet) during last sync interval."
+ access_mode: RO
+ address_offset: 0xC
+ - - field_name: nof_valid
+ field_description: "Number valid samples of the data blocks during last sync interval (= nof_sop * block size)."
+ access_mode: RO
+ address_offset: 0x10
+ - - field_name: nof_err
+ field_description: "Number data blocks with error indication during last sync interval."
+ access_mode: RO
+ address_offset: 0x14
+ #- - field_name: bsn_first_lo
+ # field_description: "First data stream BSN lo ever."
+ # access_mode: RO
+ # address_offset: 0x18
+ #- - field_name: bsn_first_hi
+ # field_description: "First data stream BSN hi ever."
+ # access_mode: RO
+ # address_offset: 0x1C
+ - - field_name: bsn_first
+ field_description: "First data stream BSN ever."
+ access_mode: RO
+ address_offset: 0x18
+ radix_width: 64
+ - - field_name: bsn_first_cycle_cnt
+ field_description: "Arrival latency of first data stream BSN ever, relative to local sync."
+ access_mode: RO
+ address_offset: 0x20
+
- peripheral_description: "This is the MM slave version of the dp_fifo_fill component."
+ - peripheral_name: dp_bsn_monitor_v2 # pi_dp_bsn_monitor_v2.py
+ peripheral_description: "Monitor the Block Sequence Number (BSN) status and latency of streaming data."
+ parameters:
+ # Parameters of mms_dp_bsn_monitor_v2.vhd
+ - { name: g_nof_streams, value: 1 }
+ mm_ports:
+ # MM port for dp_bsn_monitor_reg_v2.vhd
+ - mm_port_name: REG_DP_BSN_MONITOR_V2
+ mm_port_type: REG
+ mm_port_description: ""
+ number_of_mm_ports: g_nof_streams
+ fields:
+ - - field_name: xon_stable
+ field_description: "Data block flow control xon signal was active and stable during last sync interval."
+ width: 1
+ bit_offset: 0
+ access_mode: RO
+ address_offset: 0x0
+ - - field_name: ready_stable
+ field_description: "Clock cycle flow control ready signal was active and stable during last sync interval."
+ width: 1
+ bit_offset: 1
+ access_mode: RO
+ address_offset: 0x0
+ - - field_name: sync_timeout
+ field_description: "Data stream sync did not occur during last sync interval."
+ width: 1
+ bit_offset: 1
+ access_mode: RO
+ address_offset: 0x0
+ #- - field_name: bsn_at_sync_lo
+ # field_description: "Data stream BSN lo at sync."
+ # access_mode: RO
+ # address_offset: 0x4
+ #- - field_name: bsn_at_sync_hi
+ # field_description: "Data stream BSN hi at sync."
+ # access_mode: RO
+ # address_offset: 0x8
+ - - field_name: bsn_at_sync
+ field_description: "Data stream BSN at sync."
+ access_mode: RO
+ address_offset: 0x4
+ radix_width: 64
+ - - field_name: nof_sop
+ field_description: "Number data blocks (sop = start of packet) during last sync interval."
+ access_mode: RO
+ address_offset: 0xC
+ - - field_name: nof_valid
+ field_description: "Number valid samples of the data blocks during last sync interval (= nof_sop * block size)."
+ access_mode: RO
+ address_offset: 0x10
+ - - field_name: nof_err
+ field_description: "Number data blocks with error indication during last sync interval."
+ access_mode: RO
+ address_offset: 0x14
+ - - field_name: latency
+ field_description: "Arrival latency of data stream BSN at sync, relative to local sync."
+ access_mode: RO
+ address_offset: 0x20
+
+
+ - peripheral_name: dp_selector # pi_dp_selector.py
+ peripheral_description: "Select between two data streams or between two arrays of data streams."
+ mm_ports:
+ # MM port for dp_selector_arr.vhd
+ - mm_port_name: REG_DP_SELECTOR
+ mm_port_type: REG
+ mm_port_description: ""
+ fields:
+ - - field_name: input_select
+ field_description: |
+ "When input_select = 0 select the reference data stream(s), else when 1 select the other data stream(s).
+ The input_select is synchronsized to the start of a sync interval."
+ width: 1
+ access_mode: RW
+ address_offset: 0x0
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
index d3b8c961bbbb390ae5ec1ec9d44594e8de8c1a97..ca050afb700ddebdb067dbb9c34c3e5ca7a98c4e 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
@@ -66,8 +66,8 @@ ARCHITECTURE rtl OF dp_block_from_mm IS
CONSTANT c_reg_rst : t_reg := ('0', '0', '0', 0, 0);
- SIGNAL r : t_reg;
- SIGNAL d : t_reg;
+ SIGNAL r : t_reg;
+ SIGNAL nxt_r : t_reg;
SIGNAL mm_address : NATURAL := 0;
SIGNAL last_mm_address : NATURAL := 0;
BEGIN
@@ -77,10 +77,14 @@ BEGIN
mm_mosi.address <= TO_MEM_ADDRESS(mm_address);
- out_sosi.data <= RESIZE_DP_DATA(mm_miso.rddata(c_word_w-1 DOWNTO 0));
- out_sosi.valid <= mm_miso.rdval; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
- out_sosi.sop <= r.sop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop
- out_sosi.eop <= r.eop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop
+ u_sosi : PROCESS(r, mm_miso)
+ BEGIN
+ out_sosi <= c_dp_sosi_rst; -- To avoid Modelsim warnings on conversion to integer from unused fields.
+ out_sosi.data <= RESIZE_DP_DATA(mm_miso.rddata(c_word_w-1 DOWNTO 0));
+ out_sosi.valid <= mm_miso.rdval; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
+ out_sosi.sop <= r.sop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop
+ out_sosi.eop <= r.eop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop
+ END PROCESS;
mm_done <= r.eop;
@@ -89,45 +93,47 @@ BEGIN
IF rst='1' THEN
r <= c_reg_rst;
ELSIF rising_edge(clk) THEN
- r <= d;
+ r <= nxt_r;
END IF;
END PROCESS;
p_comb : PROCESS(r, start_pulse, out_siso, mm_address, last_mm_address)
+ VARIABLE v : t_reg;
BEGIN
- d <= r;
- d.sop <= '0';
- d.eop <= '0';
+ v := r;
+ v.sop := '0';
+ v.eop := '0';
mm_mosi.rd <= '0';
IF r.busy = '0' AND start_pulse = '1' THEN
-- initiate next block
- d.busy <= '1';
+ v.busy := '1';
ELSIF r.busy = '1' THEN
IF out_siso.ready = '1' THEN
-- continue with block
mm_mosi.rd <= '1';
IF r.word_index < g_data_size - 1 THEN
- d.word_index <= r.word_index + 1;
+ v.word_index := r.word_index + 1;
ELSE
- d.word_index <= 0;
- d.step_index <= r.step_index + g_step_size;
+ v.word_index := 0;
+ v.step_index := r.step_index + g_step_size;
END IF;
-- check start of block
IF r.word_index = 0 AND r.step_index = 0 THEN
- d.sop <= '1';
+ v.sop := '1';
END IF;
-- check end of block
IF mm_address >= last_mm_address THEN
- d.eop <= '1';
+ v.eop := '1';
-- prepare for next block
- d.busy <= '0';
- d.word_index <= 0;
- d.step_index <= 0;
+ v.busy := '0';
+ v.word_index := 0;
+ v.step_index := 0;
END IF;
END IF;
END IF;
+ nxt_r <= v;
END PROCESS;
END rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
index 08566621228bb4e41e719517306f6497d1c6e96e..0481f2ff99f2ea88456c65a93dc800f136537c9b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
@@ -42,7 +42,9 @@ USE common_lib.common_pkg.ALL;
USE common_lib.common_lfsr_sequences_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
USE work.dp_stream_pkg.ALL;
USE work.tb_dp_pkg.ALL;
@@ -84,7 +86,8 @@ ARCHITECTURE tb OF tb_dp_offload_tx_v3 IS
CONSTANT c_expected_pkt_len : NATURAL := g_pkt_len;
CONSTANT c_sync_period : NATURAL := 5;
CONSTANT c_sync_offset : NATURAL := 2;
-
+ CONSTANT c_bsn_init : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := TO_DP_BSN(0);
+
CONSTANT c_hdr_len : NATURAL := 7;
CONSTANT c_wait_last_evt : NATURAL := 100 + g_nof_repeat * c_hdr_len;
@@ -92,36 +95,96 @@ ARCHITECTURE tb OF tb_dp_offload_tx_v3 IS
-- Tx offload
-----------------------------------------------------------------------------
-- From apertif_udp_offload_pkg.vhd:
- CONSTANT c_udp_offload_nof_hdr_fields : NATURAL := 3+12+4+3; -- 448b; 7 64b words
- -- Notes:
+ CONSTANT c_udp_offload_nof_hdr_fields : NATURAL := 3+12+4+3; -- 22, 448b; 7 64b words
+ CONSTANT c_udp_offload_nof_hdr_words : NATURAL := 26; -- 23 single word + 3 double word = 26 32b words
+ -- Notes:
-- . pre-calculated ip_header_checksum is valid only for UNB0, FN0 targeting IP 10.10.10.10
-- . udp_total_length = 176 beamlets * 64b / 8b = 1408B + 14 DP bytes + 8 UDP bytes = 1430B
- CONSTANT c_udp_offload_hdr_field_arr : t_common_field_arr(c_udp_offload_nof_hdr_fields-1 DOWNTO 0) := (
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ),
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ),
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(29928) ),
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ),
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ),
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("dp_reserved" ), "RW", 47, field_default(0) ),
- ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
- ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) ) );
-
- -- From apertif_unb1_fn_beamformer_udp_offload.vhd:
- -- Override ('1') only the Ethernet fields so we can use MM defaults there.
+ CONSTANT c_udp_offload_hdr_field_arr : t_common_field_arr(c_udp_offload_nof_hdr_fields-1 DOWNTO 0) := ( -- index
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ), -- 21
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(x"0123456789AB") ), -- 20
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ), -- 19
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), -- 18
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ), -- 17
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ), -- 16
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ), -- 15
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ), -- 14
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ), -- 13
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ), -- 12
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ), -- 11
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ), -- 10
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(29928) ), -- 9
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ), -- 8
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ), -- 7
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ), -- 6
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- 5
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ), -- 4
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ), -- 3
+ ( field_name_pad("dp_reserved" ), "RW", 47, field_default(x"010203040506") ), -- 2
+ ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ), -- 1
+ ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) ) ); -- 0
+
+ -- TX: Corresponding storage of c_udp_offload_hdr_field_arr in MM register words
+ -- . Note: It appears that the tx_hdr_word read values are the MM write values, so read of value from logic fields (with MM override '0', e.g. dp_bsn, eth_src_mac) is not supported.
+ CONSTANT c_expected_tx_hdr_word_arr : t_slv_32_arr(0 TO c_udp_offload_nof_hdr_words-1) := ( -- word address
+ X"00000000", -- 0 = dp_bsn[31:0] -- readback is MM value, not the logic value
+ X"00000000", -- 1 = dp_bsn[63:32]
+ X"00000000", -- 2 = dp_sync
+ X"03040506", -- 3 = dp_reserved[31:0]
+ X"00000102", -- 4 = dp_reserved[47:32]
+ X"00000000", -- 5 = udp_checksum
+ X"00000596", -- 6 = udp_total_length
+ X"00000000", -- 7 = udp_dst_port
+ X"00000000", -- 8 = udp_src_port -- readback is MM value, not the logic value
+ X"C0A80001", -- 9 = ip_dst_addr
+ X"C0A80009", -- 10 = ip_src_addr
+ X"000074E8", -- 11 = ip_header_checksum
+ X"00000011", -- 12 = ip_protocol
+ X"0000007F", -- 13 = ip_time_to_live
+ X"00000000", -- 14 = ip_fragment_offset
+ X"00000002", -- 15 = ip_flags
+ X"00000000", -- 16 = ip_identification
+ X"000005AA", -- 17 = ip_total_length
+ X"00000000", -- 18 = ip_services
+ X"00000005", -- 19 = ip_header_length
+ X"00000004", -- 20 = ip_version
+ X"00000800", -- 21 = eth_type[15:0]
+ X"456789AB", -- 22 = eth_src_mac[31:0] -- readback is MM value, not the logic value
+ X"00000123", -- 23 = eth_src_mac[47:32]
+ X"214368AC", -- 24 = eth_dst_mac[31:0]
+ X"0000001B"); -- 25 = eth_dst_mac[47:32]
+
+ -- RX: Corresponding storage of c_udp_offload_hdr_field_arr in MM register words
+ CONSTANT c_expected_rx_hdr_word_arr : t_slv_32_arr(0 TO c_udp_offload_nof_hdr_words-1) := ( -- word address
+ X"0000000B", -- 0 = dp_bsn[31:0] -- dynamic value obtained from simulation
+ X"00000000", -- 1 = dp_bsn[63:32]
+ X"00000000", -- 2 = dp_sync -- dynamic value obtained from simulation
+ X"03040506", -- 3 = dp_reserved[31:0]
+ X"00000102", -- 4 = dp_reserved[47:32]
+ X"00000000", -- 5 = udp_checksum
+ X"00000596", -- 6 = udp_total_length
+ X"00000000", -- 7 = udp_dst_port
+ X"00000000", -- 8 = udp_src_port
+ X"C0A80001", -- 9 = ip_dst_addr
+ X"C0A80009", -- 10 = ip_src_addr
+ X"000074E8", -- 11 = ip_header_checksum
+ X"00000011", -- 12 = ip_protocol
+ X"0000007F", -- 13 = ip_time_to_live
+ X"00000000", -- 14 = ip_fragment_offset
+ X"00000002", -- 15 = ip_flags
+ X"00000000", -- 16 = ip_identification
+ X"000005AA", -- 17 = ip_total_length
+ X"00000000", -- 18 = ip_services
+ X"00000005", -- 19 = ip_header_length
+ X"00000004", -- 20 = ip_version
+ X"00000800", -- 21 = eth_type[15:0]
+ X"86080000", -- 22 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
+ X"00000022", -- 23 = eth_src_mac[47:32]
+ X"214368AC", -- 24 = eth_dst_mac[31:0]
+ X"0000001B"); -- 25 = eth_dst_mac[47:32]
+
+ -- From apertif_unb1_fn_beamformer_udp_offload.vhd: 221 111111111000 0000 000
+ -- Override ('1') only the Ethernet fields so we can use MM defaults there. 109 876543210987 6543 210
CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_udp_offload_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111111"&"1111"&"100";
CONSTANT c_NODE_ID : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(0, 8);
@@ -137,7 +200,10 @@ ARCHITECTURE tb OF tb_dp_offload_tx_v3 IS
SIGNAL tx_hdr_fields_in_arr : t_slv_1024_arr(0 DOWNTO 0);
SIGNAL tx_hdr_fields_out_arr : t_slv_1024_arr(0 DOWNTO 0);
-
+
+ SIGNAL tx_hdr_word : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL rx_hdr_word : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
@@ -210,6 +276,7 @@ BEGIN
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
+ g_bsn_init => c_bsn_init,
-- specific
g_in_dat_w => g_data_w,
g_nof_repeat => g_nof_repeat,
@@ -366,6 +433,29 @@ BEGIN
hdr_fields_out_arr => tx_hdr_fields_out_arr
);
+
+ p_rd_tx_hdr_words : PROCESS
+ VARIABLE v_word : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ BEGIN
+ proc_common_wait_until_hi_lo(dp_clk, tx_offload_sosi_arr(0).sync);
+ proc_common_wait_until_hi_lo(dp_clk, tx_offload_sosi_arr(0).sync);
+ print_str("");
+ FOR I IN 0 TO c_udp_offload_nof_hdr_words-1 LOOP
+ proc_mem_mm_bus_rd(I, mm_clk, reg_dp_offload_tx_hdr_dat_mosi);
+ proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
+ v_word := reg_dp_offload_tx_hdr_dat_miso.rddata(31 DOWNTO 0);
+ -- Log word in transcript window
+ print_str("tx_hdr_word(" & int_to_str(I) & ") = " & slv_to_hex(v_word));
+ -- View word in wave window
+ tx_hdr_word <= v_word;
+ -- Verify expected word
+ ASSERT c_expected_tx_hdr_word_arr(I) = v_word REPORT "Unexpected tx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_tx_hdr_word_arr(I)) SEVERITY ERROR;
+ END LOOP;
+ print_str("");
+ WAIT;
+ END PROCESS;
+
+
------------------------------------------------------------------------------
-- Link
------------------------------------------------------------------------------
@@ -424,7 +514,31 @@ BEGIN
dp_offload_rx_src_in_arr <= (OTHERS=>c_dp_siso_rdy);
dp_offload_rx_src_in_arr(0) <= verify_snk_out;
-
+
+
+ p_rd_rx_hdr_words : PROCESS
+ VARIABLE v_word : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ BEGIN
+ proc_common_wait_until_hi_lo(dp_clk, verify_snk_in.sync);
+ proc_common_wait_until_hi_lo(dp_clk, verify_snk_in.sync);
+ proc_common_wait_until_hi_lo(dp_clk, verify_snk_in.sync);
+ print_str("");
+ FOR I IN 0 TO c_udp_offload_nof_hdr_words-1 LOOP
+ proc_mem_mm_bus_rd(I, mm_clk, reg_dp_offload_rx_hdr_dat_mosi);
+ proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
+ v_word := reg_dp_offload_rx_hdr_dat_miso.rddata(31 DOWNTO 0);
+ -- Log word in transcript window
+ print_str("rx_hdr_word(" & int_to_str(I) & ") : " & slv_to_hex(v_word));
+ -- View word in wave window
+ rx_hdr_word <= v_word;
+ -- Verify expected word
+ ASSERT c_expected_rx_hdr_word_arr(I) = v_word REPORT "Unexpected rx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_rx_hdr_word_arr(I)) SEVERITY ERROR;
+ END LOOP;
+ print_str("");
+ WAIT;
+ END PROCESS;
+
+
------------------------------------------------------------------------------
-- Auxiliary
------------------------------------------------------------------------------
diff --git a/libraries/base/mm/src/vhdl/mm_master_mux.vhd b/libraries/base/mm/src/vhdl/mm_master_mux.vhd
index abac065ce676b536b61ea87e0d741c85253c3bd0..7ab34a45f22ad5d29561f64fb7970f68565417e5 100644
--- a/libraries/base/mm/src/vhdl/mm_master_mux.vhd
+++ b/libraries/base/mm/src/vhdl/mm_master_mux.vhd
@@ -122,7 +122,7 @@ BEGIN
mux_mosi <= master_mosi_arr(index);
-- Multiplex slave read response
- p_miso : PROCESS(mux_miso, index)
+ p_miso : PROCESS(mux_miso, index, index_hold)
BEGIN
master_miso_arr <= (OTHERS=>mux_miso); -- default assign to all, to avoid latches
FOR I IN 0 TO g_nof_masters-1 LOOP
diff --git a/libraries/base/reorder/reorder.peripheral.yaml b/libraries/base/reorder/reorder.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..d74d0333fecd7b8a8243da6ffa36e6847b71716a
--- /dev/null
+++ b/libraries/base/reorder/reorder.peripheral.yaml
@@ -0,0 +1,34 @@
+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: reorder
+hdl_library_description: "Reorder data within and between data streams."
+
+peripherals:
+ - peripheral_name: reorder_col_wide # pi_ss_ss_wide.py
+ peripheral_description: |
+ "Reorder the data serially per stream.
+ Each block of g_nof_ch_in input data gets stored, and then a block of g_nof_ch_sel
+ selected data is passed on. The index fields specify the order and the index of
+ the input data that is passed on.
+ There are g_wb_factor parallel data streams. All data streams can be reordered
+ independently."
+ parameters:
+ # Parameters of reorder_col_wide.vhd / reorder_col.vhd
+ - { name: g_wb_factor, value: 1 }
+ - { name: g_nof_ch_in, value: 256 }
+ - { name: g_nof_ch_sel, value: 192 } # g_nof_ch_sel < g_nof_ch_in
+ mm_ports:
+ # MM port for reorder_col_wide.vhd / reorder_col.vhd
+ - mm_port_name: RAM_SS_SS_WIDE
+ mm_port_description: ""
+ mm_port_type: RAM
+ number_of_mm_ports: g_wb_factor
+ fields:
+ - - field_name: index
+ field_description: ""
+ width: ceil_log2(g_nof_ch_in)
+ address_offset: 0x0
+ number_of_fields: g_nof_ch_sel
+
diff --git a/libraries/dsp/bf/bf.peripheral.yaml b/libraries/dsp/bf/bf.peripheral.yaml
index 85987668999582e19448a14b902807b067f9e30e..12c36e3e1a9c95371dbcca9f63b5a2f2d83604fb 100644
--- a/libraries/dsp/bf/bf.peripheral.yaml
+++ b/libraries/dsp/bf/bf.peripheral.yaml
@@ -16,11 +16,11 @@ peripherals:
- { name: g_bf.nof_input_streams , value: 16 }
- { name: c_nof_signal_paths_per_stream, value: g_bf.nof_signal_paths / g_bf.nof_input_streams }
- slave_ports:
+ mm_ports:
# ram_bf_weights
- - slave_name : WEIGHTS
- number_of_slaves: g_bf.nof_weights
- slave_type: RAM
+ - mm_port_name : WEIGHTS
+ number_of_mm_ports: g_bf.nof_weights
+ mm_port_type: RAM
fields:
- - field_name : bf_weights
width : g_bf.in_weights_w * c_nof_complex
@@ -29,26 +29,26 @@ peripherals:
field_description: |
"Contains the weights.
The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
- slave_discription: >
+ mm_port_description: >
" "
# ram_ss_ss_wide
- - slave_name : SS_SS_WIDE
- number_of_slaves: g_bf.nof_weights
- slave_type: RAM
+ - mm_port_name : SS_SS_WIDE
+ number_of_mm_ports: g_bf.nof_weights
+ mm_port_type: RAM
fields:
- - field_name : ss_ss_wide
width : 32
number_of_fields: g_bf.nof_subbands * g_bf.nof_input_streams * c_nof_signal_paths_per_stream # 16*4=64, nof_input_streams*nof_signal_paths_per_stream
field_description: |
"Contains the addresses to select from the stored subbands."
- slave_discription: >
+ mm_port_description: >
" "
# ram_st_sst_bf
- - slave_name : ST_SST
- number_of_slaves: g_bf.nof_weights
- slave_type: RAM
+ - mm_port_name : ST_SST
+ number_of_mm_ports: g_bf.nof_weights
+ mm_port_type: RAM
fields:
- - field_name : st_sst_bf
width : 56
@@ -57,13 +57,13 @@ peripherals:
field_description: |
"Contains the weights.
The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
- slave_discription: >
+ mm_port_description: >
" "
# reg_st_sst_bf
- - slave_name : treshold
- number_of_slaves: 1
- slave_type: REG
+ - mm_port_name : treshold
+ number_of_mm_ports: 1
+ mm_port_type: REG
fields:
- - field_name : treshold
address_offset: 0x0
@@ -72,7 +72,7 @@ peripherals:
In case the treshold register is set to a non-zero value, it allows to create a sample & hold function
for the a-input of the multiplier.
The a-input of the multiplier is updated every treshold clockcycle. Thereby cross statistics can be created."
- slave_discription: >
+ mm_port_description: >
" "
peripheral_description: |
diff --git a/libraries/dsp/filter/filter.peripheral.yaml b/libraries/dsp/filter/filter.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..af75840c8d526380dcf05aeb4acab04678f8e6de
--- /dev/null
+++ b/libraries/dsp/filter/filter.peripheral.yaml
@@ -0,0 +1,44 @@
+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: filter
+hdl_library_description: "Poly-phase filter (PPF) for a Wideband Poly-phase filterbank (WPFB)"
+
+peripherals:
+ - peripheral_name: fil_ppf_w # pi_fil_ppf_w.py
+ peripheral_description: |
+ "PPF FIR filter for wideband data streams, all data streams use the same FIR coefficients.
+ The PPF has g_nof_bands phases, where g_nof_bands is equal to the size of the FFT in the
+ PFB. The PPF has g_nof_taps FIR taps per phase. Hence the total number of FIR coefficients
+ is g_nof_taps * g_nof_bands.
+ The PPF can process a data stream that is clocked at a wideband factor g_wb_factor higher
+ data rate, by running g_wb_factor parts in parallel.
+ The FIR coefficients are real values."
+ parameters:
+ # Parameters of fil_ppf_wide.vhd
+ - { name: g_wb_factor, value: 1 }
+ - { name: g_nof_taps, value: 8 }
+ - { name: g_nof_bands, value: 256 }
+ - { name: g_coef_dat_w, value: 16 }
+ mm_ports:
+ # MM port for fil_ppf_wide.vhd / fil_ppf_single.vhd
+ - mm_port_name: RAM_FIL_COEFS
+ mm_port_description: |
+ "The FIR filter coefficients are stored in blocks of g_nof_bands/g_wb_factor real
+ coefficients:
+
+ (int16)coefs[g_wb_factor][g_nof_taps][g_nof_bands/g_wb_factor]
+
+ For g_wb_factor = 1 this reduces to g_nof_taps blocks of g_nof_bands/g_wb_factor
+ coefficients:
+
+ (int16)coefs[g_nof_taps][g_nof_bands]"
+ mm_port_type: RAM
+ number_of_mm_ports: g_wb_factor * g_nof_taps
+ fields:
+ - - field_name: coef
+ field_description: "Real FIR filter coefficient"
+ width: g_coef_dat_w
+ address_offset: 0x0
+ number_of_fields: g_nof_bands / g_wb_factor
diff --git a/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml b/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
index 04e707fbea28f020d5a47173567f77811cad3291..2872466d08baf491453e722ba3bd0403fb03ed53 100644
--- a/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
+++ b/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
@@ -13,28 +13,28 @@ peripherals:
- { name: g_fs_offset_w , value: 10 }
- { name: g_fs_step_w , value: 17 }
- slave_ports:
+ mm_ports:
# actual hdl name: ram_fringe_stop_step
- - slave_name : STEP
- slave_type : RAM
+ - mm_port_name : STEP
+ mm_port_type : RAM
fields:
- - field_name : fringe_stop_step
width: g_fs_step_w
number_of_fields: g_nof_channels
field_description: |
"Contains the step size for all nof_channels channels."
- slave_discription: " "
+ mm_port_description: " "
# actual hdl name: fringe_stop_offset
- - slave_name : STOP_OFFSET
- slave_type : RAM
+ - mm_port_name : STOP_OFFSET
+ mm_port_type : RAM
fields:
- - field_name: fringe_stop_offset
width: g_fs_offset_w
number_of_fields: g_nof_channels
field_description: |
"Contains the offset for all nof_channels channels."
- slave_discription: " "
+ mm_port_description: " "
peripheral_description: |
"The fringe stopping peripheral is based on piecewise linear coefficients. The coefficients are indicated as offset and step.
diff --git a/libraries/dsp/si/si.peripheral.yaml b/libraries/dsp/si/si.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..470bac8cdd0d81af50ff66cb9e581e19edb23db2
--- /dev/null
+++ b/libraries/dsp/si/si.peripheral.yaml
@@ -0,0 +1,20 @@
+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: si
+hdl_library_description: "Spectral Inversion (SI)"
+
+peripherals:
+ - peripheral_name: si # pi_si.py
+ peripheral_description: "Spectral Inversion control."
+ mm_ports:
+ # MM port for si_arr.vhd
+ - mm_port_name: REG_SI
+ mm_port_description: "In the even Nyquist zones the sampled spectrum gets flipped in frequency. This flip can be compensated for by enabling spectral inversion (SI)."
+ mm_port_type: REG
+ fields:
+ - - field_name: enable
+ field_description: "When 0 then pass on the array of input signals, when 1 then enable spectral inversion for all the input signals."
+ width: 1
+ address_offset: 0x0
diff --git a/libraries/dsp/st/st.peripheral.yaml b/libraries/dsp/st/st.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..c7c9f0c1f8718215ec467035485555bc0c4dac51
--- /dev/null
+++ b/libraries/dsp/st/st.peripheral.yaml
@@ -0,0 +1,99 @@
+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: st
+hdl_library_description: "Statistics (ST)"
+
+peripherals:
+ - peripheral_name: st_sst # pi_st_sst.py
+ peripheral_description: |
+ "Accumulate the signal power values during a sync interval:
+ . g_xst_enable = False : Auto power statistics for subbands (SST), beamlets (BST)
+ . g_xst_enable = True : Cross power statistics for subbands = crosslets (XST)."
+ parameters:
+ # Parameters of pi_st_sst.py
+ - { name: g_nof_instances, value: 1 }
+ # Parameters of st_sst.vhd
+ - { name: g_nof_stat, value: 512 } # nof accumulators
+ - { name: g_xst_enable, value: False } # False for auto powers, True for cross powers
+ - { name: g_stat_data_w, value: 64 } # statistics accumulator width in bits
+ - { name: g_stat_data_sz, value: 2 } # statistics accumulator width in 32b MM words
+ mm_ports:
+ # MM port for st_sst.vhd
+ - mm_port_name: RAM_ST_SST
+ mm_port_description: |
+ "The statistics are calculated for blocks of g_nof_stat time multiplexed data streams.
+ There are g_nof_instances parallel time multiplexed data streams.
+ The statistic power values have g_stat_data_w bits. The memory format is:
+ . g_xst_enable = False, for real powers : (uint32 * g_stat_data_sz)st[g_nof_instances]_[g_nof_stat]
+ . g_xst_enable = True, for complex powers : (cuint32 * g_stat_data_sz)st[g_nof_instances]_[g_nof_stat]"
+ mm_port_type: RAM
+ number_of_mm_ports: g_nof_instances
+ fields:
+ - - field_name: power
+ field_description: ""
+ width: g_stat_data_w
+ address_offset: 0x0
+ number_of_fields: g_nof_stat * g_stat_data_sz
+
+
+ - peripheral_name: st_sst_for_sdp # pi_st_sst.py
+ peripheral_description: |
+ "Accumulate the subband auto power values during a sync interval for the subband statistics (SST) in LOFAR2.0 SDP"
+ parameters:
+ # Parameters of pi_st_sst.py, fixed in node_sdp_filterbank.vhd / sdp_pkg.vhd
+ - { name: g_nof_instances, value: 6 }
+ # Parameters of st_sst.vhd, fixed in node_sdp_filterbank.vhd / sdp_pkg.vhd
+ - { name: g_nof_stat, value: 1024 } # nof accumulators: N_sub * Q_fft = 512 * 2 = 1024
+ - { name: g_stat_data_w, value: 54 } # statistics accumulator width in bits: W_statistic = 64
+ - { name: g_stat_data_sz, value: 2 } # statistics accumulator width in 32b MM words: W_statistic_sz = 2
+ mm_ports:
+ # MM port for st_sst.vhd
+ - mm_port_name: RAM_ST_SST
+ mm_port_description: |
+ "The subband statistics per PN are stored in g_nof_instances = P_pfb = S_pn / Q_fft = 6 blocks of
+ N_sub * Q_fft = 512 * 2 = 1024 real values as:
+
+ (uint64)SST[g_nof_instances]_[g_nof_stat] = (uint64)SST[S_pn/Q_fft]_[N_sub][Q_fft]
+
+ where S_pn = 12, Q_fft = 2 and N_sub = 512 are defined in sdp_pkg.vhd."
+ mm_port_type: RAM
+ number_of_mm_ports: g_nof_instances
+ fields:
+ - - field_name: power
+ field_description: ""
+ width: 32
+ address_offset: 0x0
+ number_of_fields: g_nof_stat * g_stat_data_sz
+ radix_width: g_stat_data_w
+
+
+ - peripheral_name: st_bst_for_sdp # pi_st_bst.py
+ peripheral_description: |
+ "Accumulate the beamlet auto power values during a sync interval for the beamlet statistics (BST) in LOFAR2.0 SDP"
+ parameters:
+ # Parameters of pi_st_bst.py, fixed in node_sdp_beamformer.vhd / sdp_pkg.vhd
+ - { name: g_nof_instances, value: 6 }
+ # Parameters of st_sst.vhd, fixed in node_sdp_filterbank.vhd / sdp_pkg.vhd
+ - { name: g_nof_stat, value: 976 } # nof accumulators: S_sub_bf * N_pol_bf = 488 * 2 = 976
+ - { name: g_stat_data_w, value: 54 } # statistics accumulator width in bits: W_statistic = 64
+ - { name: g_stat_data_sz, value: 2 } # statistics accumulator width in 32b MM words: W_statistic_sz = 2
+ mm_ports:
+ # MM port for st_sst.vhd
+ - mm_port_name: RAM_ST_SST
+ mm_port_description: |
+ "The beamlet statistics per PN are stored in 1 block of S_sub_bf * N_pol_bf = 488 * 2 = 976 real values as:
+
+ (uint64)BST[g_nof_stat] = (uint64)BST[S_sub_bf][N_pol_bf]
+
+ where N_pol_bf = 2 and S_sub_bf = 488 are defined in sdp_pkg.vhd."
+ mm_port_type: RAM
+ number_of_mm_ports: 1
+ fields:
+ - - field_name: power
+ field_description: ""
+ width: 32
+ address_offset: 0x0
+ number_of_fields: g_nof_stat * g_stat_data_sz
+ radix_width: g_stat_data_w
diff --git a/libraries/io/aduh/aduh.peripheral.yaml b/libraries/io/aduh/aduh.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..c364451f0f3de254af4406b59b016b9535923307
--- /dev/null
+++ b/libraries/io/aduh/aduh.peripheral.yaml
@@ -0,0 +1,59 @@
+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: aduh
+hdl_library_description: "ADC Unit Handler (ADUH) of APERTIF."
+
+peripherals:
+ - peripheral_name: aduh_mon_dc_power # pi_aduh_monitor.py
+ peripheral_description: "Determine mean sum and power sum of samples during a sync interval"
+ parameters:
+ # Parameters of mms_aduh_monitor_arr.vhd
+ - { name: g_nof_streams, value: 1 }
+ mm_ports:
+ # MM port for mms_aduh_monitor_arr.vhd / aduh_monitor_reg.vhd
+ - mm_port_name: REG_ADUH_MON
+ mm_port_type: REG
+ mm_port_description: "Sum of samples and sample powers during a sync interval."
+ number_of_mm_ports: g_nof_streams
+ fields:
+ - - field_name: mean_sum_lo
+ field_description: "Mean sum[31:0] of samples during a sync interval."
+ access_mode: RO
+ address_offset: 0x0
+ - - field_name: mean_sum_hi
+ field_description: "Mean sum[63:32] of samples during a sync interval."
+ access_mode: RO
+ address_offset: 0x4
+ - - field_name: power_sum_lo
+ field_description: "Power sum[31:0] of sample powers during a sync interval."
+ access_mode: RO
+ address_offset: 0x8
+ - - field_name: power_sum_hi
+ field_description: "Power sum[63:32] of sample powers during a sync interval."
+ access_mode: RO
+ address_offset: 0xC
+
+ - peripheral_name: aduh_mon_data_buffer # pi_aduh_monitor.py
+ peripheral_description: "Data buffer to capture samples (= diag_data_buffer)"
+ parameters:
+ # Parameters of mms_aduh_monitor_arr.vhd
+ - { name: g_nof_streams, value: 1 }
+ - { name: g_symbol_w, value: 16 }
+ - { name: g_nof_symbols_per_data, value: 1 }
+ - { name: g_buffer_nof_symbols, value: 512 }
+ - { name: g_buffer_use_sync, value: True }
+ mm_port_ports:
+ # MM port for mms_aduh_monitor_arr.vhd
+ - mm_port_name: RAM_ADUH_MON
+ mm_port_type: RAM
+ mm_port_description: "Data buffer memory, gets filled after the sync when g_buffer_use_sync = True, else after the last word was read."
+ number_of_mm_ports: g_nof_streams
+ fields:
+ - - field_name: data
+ field_description: ""
+ width: g_symbol_w * g_nof_symbols_per_data
+ address_offset: 0x0
+ number_of_fields: g_buffer_nof_symbols / g_nof_symbols_per_data
+
diff --git a/libraries/io/epcs/epcs.peripheral.yaml b/libraries/io/epcs/epcs.peripheral.yaml
index e69ab86a8259312385efa4dbfcc1a6d1a739167d..2026d2bdf28c1bf9ae67ec48f00edf13fb94b0f5 100644
--- a/libraries/io/epcs/epcs.peripheral.yaml
+++ b/libraries/io/epcs/epcs.peripheral.yaml
@@ -1,125 +1,71 @@
-schema_name : args
+schema_name: args
schema_version: 1.0
-schema_type : peripheral
+schema_type: peripheral
-hdl_library_name : epcs
-hdl_library_description: " This is the description for the epcs package "
+hdl_library_name: epcs
+hdl_library_description: "Serial Configuration (EPCS) Device"
peripherals:
-
- # epcs_reg
- -
- peripheral_name: epcs
-
+ - peripheral_name: epcs # pi_epcs.py
+ peripheral_description: |
+ "Provide write and read to the flash memory of the FPGA using the EPCS [1]. The write access goes
+ via a write FIFO (MM to DP) and the read access goes via a read FIFO (DP to MM). The FIFOs
+ convert between the memory mapped (MM) interface and the data path (DP) streaming interface of
+ the EPCS [2].
+
+ [1] https://git.astron.nl/desp/hdl/-/blob/master/libraries/io/epcs/src/vhdl/epcs_reg.vhd
+ [2] https://git.astron.nl/desp/upe_gear/-/blob/master/peripherals/util_epcs.py"
parameters:
- - {name: "g_sim_flash_model", value: TRUE}
+ # parameters of mms_epcs.vhd / epcs_reg.vhd
+ - {name: "g_epcs_addr_w", value: 24}
- slave_ports:
- # actual hdl name: epcs_reg
- - slave_name : EPCS
- slave_type : REG
+ mm_ports:
+ # MM port for epcs_reg.vhd
+ - mm_port_name: REG_EPCS # pi_epcs.py
+ mm_port_type: REG
+ mm_port_description: "Handle the read, erase and write of the flash memory chip."
fields:
- - - field_name : addr
- width : 24
- access_mode : WO
+ - - field_name: addr
+ field_description: "Address to write to or read from."
+ width: 24
+ access_mode: WO
address_offset: 0x0
- field_description: " address to write to or read from "
- - - field_name : rden
- width : 1
- access_mode : WO
+ - - field_name: rden
+ field_description: "Read enable bit."
+ width: 1
+ access_mode: WO
address_offset: 0x4
- field_description: " Read enable bit "
- - - field_name : read_bit
- width : 1
- access_mode : WO
- side_effect : PW
+ - - field_name: read_bit
+ field_description: "Read bit."
+ width: 1
+ access_mode: WO
+ side_effect: PW
address_offset: 0x8
- field_description: " Read bit "
- - - field_name : write_bit
- width : 1
- access_mode : WO
- side_effect : PW
+ - - field_name: write_bit
+ field_description: "Write bit."
+ width: 1
+ access_mode: WO
+ side_effect: PW
address_offset: 0xc
- field_description: " Write bit "
- - - field_name : sector_erase
- width : 1
- access_mode : WO
+ - - field_name: sector_erase
+ field_description: "Sector erase bit."
+ width: 1
+ access_mode: WO
address_offset: 0x10
- field_description: " Sector erase bit "
- - - field_name : busy
- width : 1
- access_mode : RO
+ - - field_name: busy
+ field_description: "Busy bit."
+ width: 1
+ access_mode: RO
address_offset: 0x14
- field_description: " busy "
- - - field_name : unprotect
- width : 32
- access_mode : WO
+ - - field_name: unprotect
+ field_description: "Use 0xBEDA221E (= Bedazzle) as password to unprotect address range."
+ width: 32
+ access_mode: WO
address_offset: 0x18
- field_description: " passphrase to unprotect address range "
-
-
- slave_description: " Read and write access to flash "
-
- # actual hdl name: mms_dp_fifo_to_mm
- - slave_name : DPMM_CTRL
- slave_type : REG
- fields:
- - - field_name : ctrl
- width : 32
- access_mode : RW
- address_offset: 0x0
- number_of_fields: 1
- field_description: " "
- slave_description: " "
-
- - slave_name : DPMM_DATA
- slave_type : FIFO
- fields:
- - - field_name : data
- width : 32
- access_mode : RO
- address_offset: 0x0
- number_of_fields: 1
- field_description: " "
- slave_description: " "
-
- # actual hdl name: mms_dp_fifo_from_mm
- - slave_name : MMDP_CTRL
- slave_type : REG
- fields:
- - - field_name : ctrl
- width : 32
- access_mode : RW
- address_offset: 0x0
- number_of_fields: 2
- field_description: " "
- slave_description: " "
-
- - slave_name : MMDP_DATA
- slave_type : FIFO
- fields:
- - - field_name : data
- width : 32
- access_mode : WO
- address_offset: 0x0
- number_of_fields: 2
- field_description: " "
- slave_description: " "
-
- peripheral_description: |
- "wi Bits SE R/W Name Default Description |REG_EPCS|
- =============================================================================
- 0 [23..0] WO addr 0x0 Address to write to/read from
- 1 [0] WO rden 0x0 Read enable
- 2 [0] PW WE read 0x0 Read
- 3 [0] PW WE write 0x0 Write
- 4 [0] WO sector_erase 0x0 Sector erase
- 5 [0] RO busy 0x0 Busy
- ============================================================================="
-
\ No newline at end of file
+
diff --git a/libraries/io/eth/eth.peripheral.yaml b/libraries/io/eth/eth.peripheral.yaml
index 52cdc9dc3d091fa3c8f4088069adf61a7c81bc7f..5593e60c884be463d06bf6bce75c1443c9f71e7c 100644
--- a/libraries/io/eth/eth.peripheral.yaml
+++ b/libraries/io/eth/eth.peripheral.yaml
@@ -1,55 +1,52 @@
-schema_name : args
+schema_name: args
schema_version: 1.0
-schema_type : peripheral
+schema_type: peripheral
-hdl_library_name : eth
-hdl_library_description: " This is the description for the eth package "
+hdl_library_name: eth
+hdl_library_description: "Triple Speed Ethernet (TSE) peripheral for 1GbE."
peripherals:
- -
- peripheral_name: eth1g
-
- parameters:
- - { name: c_eth_ram_nof_words, value: 1024 }
- #g_technology: c_tech_select_default
- #g_ETH_PHY : "LVDS"
-
- slave_ports:
- # actual hdl name: reg_tse
- - slave_name : TSE
- slave_type : REG
+ - peripheral_name: eth # pi_eth.py
+ peripheral_description: |
+ "The ETH module connects the 1GbE TSE [1] to the microprocessor and to streaming UDP ports [2]. The
+ packets for the streaming channels are directed based on the UDP port number and all other packets
+ are transfered to the default control channel and handled by the microprocessor.
+
+ [1] https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf
+ [2] https://git.astron.nl/desp/hdl/-/blob/master/libraries/io/eth/doc/ASTRON_RP_396_eth_1gb_module.pdf"
+ mm_ports:
+ # MM port for registers in the TSE IP [1]
+ - mm_port_name: AVS_ETH_0_TSE
+ mm_port_type: REG
+ mm_port_description: "Registers in the TSE IP [1], handled by the microprocessor."
fields:
- - - field_name : status
- access_mode : RO
- address_offset : 0x0
- number_of_fields: 1024
- field_description: "reg tse"
- slave_description: " "
+ - - field_name: status
+ field_description: ""
+ access_mode: RO
+ address_offset: 0x0
+ number_of_fields: 1024 # = c_tech_tse_byte_addr_w in tech_tse_pkg.vhd
- # actual hdl name: reg
- - slave_name : ETH
- slave_type : REG
+ # MM port for registers in eth_mm_registers.vhd in the ETH module [2]
+ - mm_port_name: AVS_ETH_0_REG
+ mm_port_type: REG
+ mm_port_description: "Registers in the ETH module [2], handled by the microprocessor."
fields:
- - - field_name : status
- access_mode : RO
- address_offset : 0x0
- number_of_fields: 12
- field_description: "reg registers"
- slave_description: " "
+ - - field_name: status
+ field_description: ""
+ access_mode: RO
+ address_offset: 0x0
+ number_of_fields: 12 # = c_eth_reg_nof_words in eth_pkg.vhd
- # actual hdl name: ram
- - slave_name : ETH
- slave_type : RAM
+ # MM port for ETH packet packet buffers in eth.vhd
+ - mm_port_name: AVS_ETH_0_RAM
+ mm_port_type: RAM
+ mm_port_description: |
+ "Buffer RAM for request packets (Rx) and response packets (Tx) via 1GbE, used by the microprocessor
+ to receive and transmit packets via the ETH module."
fields:
- - - field_name : ram
- number_of_fields: c_eth_ram_nof_words
- field_description: |
- "Contains the Waveform data for the data-streams to be send"
- slave_description: " "
-
- peripheral_description: |
- "
- Connect the 1GbE TSE to the microprocessor and to streaming UDP ports. The
- packets for the streaming channels are directed based on the UDP port
- number and all other packets are transfered to the default control channel."
+ - - field_name: data
+ field_description: "Data 32b-word."
+ number_of_fields: 1024 # = c_eth_ram_nof_words in eth_pkg.vhd
+
+
diff --git a/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml b/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..c70b59c3b9abca3930868c04f33f630373978632
--- /dev/null
+++ b/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
@@ -0,0 +1,179 @@
+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: nw_10GbE
+hdl_library_description: "Network peripherals for 10GbE."
+
+peripherals:
+ - peripheral_name: nw_10GbE_unb2legacy # pi_nw_10GbE_unb2legacy.py / pi_tr_10GbE.py / pi_tr_10GbE_unb2.py
+ peripheral_description: |
+ "M&C of Intel Low Latency (LL) 10GbE MAC control status register (CSR) see [1]
+
+ The LL 10GbE MAC is used with the legacy address map option of the old 10GbE MAC, see [2], this implies:
+ . Some registers have a different address offset in [1] and [2]
+ . The 36 bit registers are stored at word 0 = [31:0] and word 1 = [3:0] = [35:32] in [1], but in [2]
+ they are stored with their 4 most significant bits first and their 32 least significant bits last, so
+ with word 0 = [3:0] = [35:32] and word 1 = [31:0].
+ Here the address map and 36 bit word order from [2] are used.
+
+ [1] LL 10GbE MAC, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_32b_10g_ethernet_mac.pdf
+ [2] Legacy 10GbE MAC, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/10gbps_mac.pdf
+ "
+ parameters:
+ # Parameters of nw_10GbE.vhd / tr_10GbE.vhd
+ - { name: g_nof_macs, value: 1 }
+ mm_ports:
+ # MM port for reg_mac_mosi = mac_mosi in ip_arria10_e1sg_eth_10g.vhd
+ # Use nw_10GbE_word_to_byte_address.py to derive the byte addresses from the word addresses
+ - mm_port_name: REG_NW_10GBE_MAC
+ mm_port_type: REG
+ mm_port_description: "MAC registers"
+ number_of_mm_ports: g_nof_macs
+ fields:
+ - - {field_name: rx_transfer_control, width: 1, access_mode: RW, address_offset: 0x0000 } # = 0x0000
+ - - {field_name: rx_transfer_status, width: 1, access_mode: RO, address_offset: 0x0004 } # = 0x0001
+ - - {field_name: rx_padcrc_control, width: 2, access_mode: RW, address_offset: 0x0100 } # = 0x0040
+ - - {field_name: rx_crccheck_control, width: 2, access_mode: RW, address_offset: 0x0200 } # = 0x0080
+ - - {field_name: rx_pktovrflow_error, width: 32, access_mode: RO, address_offset: 0x0300, radix_width: 36 } # = 0x00C0
+ - - {field_name: rx_pktovrflow_etherStatsDropEvents, width: 32, access_mode: RO, address_offset: 0x0308, radix_width: 36 } # = 0x00C2
+ - - {field_name: rx_lane_decoder_preamble_control, width: 1, access_mode: RW, address_offset: 0x0400 } # = 0x0100
+ - - {field_name: rx_preamble_inserter_control, width: 1, access_mode: RW, address_offset: 0x0500 } # = 0x0140
+ - - {field_name: rx_frame_control, width: 20, access_mode: RW, address_offset: 0x2000 } # = 0x0800
+ - - {field_name: rx_frame_maxlength, width: 16, access_mode: RW, address_offset: 0x2004 } # = 0x0801
+ - - {field_name: rx_frame_addr0, width: 16, access_mode: RW, address_offset: 0x2008 } # = 0x0802
+ - - {field_name: rx_frame_addr1, width: 16, access_mode: RW, address_offset: 0x200c } # = 0x0803
+ - - {field_name: rx_frame_spaddr0_0, width: 16, access_mode: RW, address_offset: 0x2010 } # = 0x0804
+ - - {field_name: rx_frame_spaddr0_1, width: 16, access_mode: RW, address_offset: 0x2014 } # = 0x0805
+ - - {field_name: rx_frame_spaddr1_0, width: 16, access_mode: RW, address_offset: 0x2018 } # = 0x0806
+ - - {field_name: rx_frame_spaddr1_1, width: 16, access_mode: RW, address_offset: 0x201c } # = 0x0807
+ - - {field_name: rx_frame_spaddr2_0, width: 16, access_mode: RW, address_offset: 0x2020 } # = 0x0808
+ - - {field_name: rx_frame_spaddr2_1, width: 16, access_mode: RW, address_offset: 0x2024 } # = 0x0809
+ - - {field_name: rx_frame_spaddr3_0, width: 16, access_mode: RW, address_offset: 0x2028 } # = 0x080A
+ - - {field_name: rx_frame_spaddr3_1, width: 16, access_mode: RW, address_offset: 0x202c } # = 0x080B
+ - - {field_name: rx_pfc_control, width: 17, access_mode: RW, address_offset: 0x2060 } # = 0x0818
+ - - {field_name: tx_transfer_control, width: 1, access_mode: RW, address_offset: 0x4000 } # = 0x1000
+ - - {field_name: tx_transfer_status, width: 1, access_mode: RO, address_offset: 0x4004 } # = 0x1001
+ - - {field_name: tx_padins_control, width: 1, access_mode: RW, address_offset: 0x4100 } # = 0x1040
+ - - {field_name: tx_crcins_control, width: 2, access_mode: RW, address_offset: 0x4200 } # = 0x1080
+ - - {field_name: tx_pktunderflow_error, width: 32, access_mode: RO, address_offset: 0x4300, radix_width: 36 } # = 0x10C0
+ - - {field_name: tx_preamble_control, width: 1, access_mode: RW, address_offset: 0x4400 } # = 0x1100
+ - - {field_name: tx_pauseframe_control, width: 2, access_mode: RW, address_offset: 0x4500 } # = 0x1140
+ - - {field_name: tx_pauseframe_quanta, width: 16, access_mode: RW, address_offset: 0x4504 } # = 0x1141
+ - - {field_name: tx_pauseframe_enable, width: 1, access_mode: RW, address_offset: 0x4508 } # = 0x1142
+ # Altera is unclear about the width of the quanta registers. Assuming 32 bits, where bits 16:31 are reserved:
+ - - {field_name: pfc_pause_quanta_0, width: 32, access_mode: RW, address_offset: 0x4600 } # = 0x1180
+ - - {field_name: pfc_pause_quanta_1, width: 32, access_mode: RW, address_offset: 0x4604 } # = 0x1181
+ - - {field_name: pfc_pause_quanta_2, width: 32, access_mode: RW, address_offset: 0x4608 } # = 0x1182
+ - - {field_name: pfc_pause_quanta_3, width: 32, access_mode: RW, address_offset: 0x460c } # = 0x1183
+ - - {field_name: pfc_pause_quanta_4, width: 32, access_mode: RW, address_offset: 0x4610 } # = 0x1184
+ - - {field_name: pfc_pause_quanta_5, width: 32, access_mode: RW, address_offset: 0x4614 } # = 0x1185
+ - - {field_name: pfc_pause_quanta_6, width: 32, access_mode: RW, address_offset: 0x4618 } # = 0x1186
+ - - {field_name: pfc_pause_quanta_7, width: 32, access_mode: RW, address_offset: 0x461c } # = 0x1187
+ - - {field_name: pfc_holdoff_quanta_0, width: 32, access_mode: RW, address_offset: 0x4640 } # = 0x1190
+ - - {field_name: pfc_holdoff_quanta_1, width: 32, access_mode: RW, address_offset: 0x4644 } # = 0x1191
+ - - {field_name: pfc_holdoff_quanta_2, width: 32, access_mode: RW, address_offset: 0x4648 } # = 0x1192
+ - - {field_name: pfc_holdoff_quanta_3, width: 32, access_mode: RW, address_offset: 0x464c } # = 0x1193
+ - - {field_name: pfc_holdoff_quanta_4, width: 32, access_mode: RW, address_offset: 0x4650 } # = 0x1194
+ - - {field_name: pfc_holdoff_quanta_5, width: 32, access_mode: RW, address_offset: 0x4654 } # = 0x1195
+ - - {field_name: pfc_holdoff_quanta_6, width: 32, access_mode: RW, address_offset: 0x4658 } # = 0x1196
+ - - {field_name: pfc_holdoff_quanta_7, width: 32, access_mode: RW, address_offset: 0x465c } # = 0x1197
+ - - {field_name: tx_pfc_priority_enable, width: 8, access_mode: RW, address_offset: 0x4680 } # = 0x11A0
+ - - {field_name: tx_addrins_control, width: 1, access_mode: RW, address_offset: 0x4800 } # = 0x1200
+ - - {field_name: tx_addrins_macaddr0, width: 32, access_mode: RW, address_offset: 0x4804 } # = 0x1201
+ - - {field_name: tx_addrins_macaddr1, width: 16, access_mode: RW, address_offset: 0x4808 } # = 0x1202
+ - - {field_name: tx_frame_maxlength, width: 16, access_mode: RW, address_offset: 0x6004 } # = 0x1801
+ - - {field_name: rx_stats_clr, width: 1, access_mode: RW, address_offset: 0x3000 } # = 0x0C00
+ - - {field_name: tx_stats_clr, width: 1, access_mode: RW, address_offset: 0x7000 } # = 0x1C00
+ - - {field_name: rx_stats_framesOK, width: 32, access_mode: RO, address_offset: 0x3008, radix_width: 36 } # = 0x0C02
+ - - {field_name: tx_stats_framesOK, width: 32, access_mode: RO, address_offset: 0x7008, radix_width: 36 } # = 0x1C02
+ - - {field_name: rx_stats_framesErr, width: 32, access_mode: RO, address_offset: 0x3010, radix_width: 36 } # = 0x0C04
+ - - {field_name: tx_stats_framesErr, width: 32, access_mode: RO, address_offset: 0x7010, radix_width: 36 } # = 0x1C04
+ - - {field_name: rx_stats_framesCRCErr, width: 32, access_mode: RO, address_offset: 0x3018, radix_width: 36 } # = 0x0C06
+ - - {field_name: tx_stats_framesCRCErr, width: 32, access_mode: RO, address_offset: 0x7018, radix_width: 36 } # = 0x1C06
+ - - {field_name: rx_stats_octetsOK, width: 32, access_mode: RO, address_offset: 0x3020, radix_width: 36 } # = 0x0C08
+ - - {field_name: tx_stats_octetsOK, width: 32, access_mode: RO, address_offset: 0x7020, radix_width: 36 } # = 0x1C08
+ - - {field_name: rx_stats_pauseMACCtrl_Frames, width: 32, access_mode: RO, address_offset: 0x3028, radix_width: 36 } # = 0x0C0A
+ - - {field_name: tx_stats_pauseMACCtrl_Frames, width: 32, access_mode: RO, address_offset: 0x7028, radix_width: 36 } # = 0x1C0A
+ - - {field_name: rx_stats_ifErrors, width: 32, access_mode: RO, address_offset: 0x3030, radix_width: 36 } # = 0x0C0C
+ - - {field_name: tx_stats_ifErrors, width: 32, access_mode: RO, address_offset: 0x7030, radix_width: 36 } # = 0x1C0C
+ - - {field_name: rx_stats_unicast_FramesOK, width: 32, access_mode: RO, address_offset: 0x3038, radix_width: 36 } # = 0x0C0E
+ - - {field_name: tx_stats_unicast_FramesOK, width: 32, access_mode: RO, address_offset: 0x7038, radix_width: 36 } # = 0x1C0E
+ - - {field_name: rx_stats_unicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x3040, radix_width: 36 } # = 0x0C10
+ - - {field_name: tx_stats_unicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x7040, radix_width: 36 } # = 0x1C10
+ - - {field_name: rx_stats_multicastFramesOK, width: 32, access_mode: RO, address_offset: 0x3048, radix_width: 36 } # = 0x0C12
+ - - {field_name: tx_stats_multicastFramesOK, width: 32, access_mode: RO, address_offset: 0x7048, radix_width: 36 } # = 0x1C12
+ - - {field_name: rx_stats_multicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x3050, radix_width: 36 } # = 0x0C14
+ - - {field_name: tx_stats_multicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x7050, radix_width: 36 } # = 0x1C14
+ - - {field_name: rx_stats_broadcastFramesOK, width: 32, access_mode: RO, address_offset: 0x3058, radix_width: 36 } # = 0x0C16
+ - - {field_name: tx_stats_broadcastFramesOK, width: 32, access_mode: RO, address_offset: 0x7058, radix_width: 36 } # = 0x1C16
+ - - {field_name: rx_stats_broadcast_FramesErr, width: 32, access_mode: RO, address_offset: 0x3060, radix_width: 36 } # = 0x0C18
+ - - {field_name: tx_stats_broadcast_FramesErr, width: 32, access_mode: RO, address_offset: 0x7060, radix_width: 36 } # = 0x1C18
+ - - {field_name: rx_stats_etherStatsOctets, width: 32, access_mode: RO, address_offset: 0x3068, radix_width: 36 } # = 0x0C1A
+ - - {field_name: tx_stats_etherStatsOctets, width: 32, access_mode: RO, address_offset: 0x7068, radix_width: 36 } # = 0x1C1A
+ - - {field_name: rx_stats_etherStatsPkts, width: 32, access_mode: RO, address_offset: 0x3070, radix_width: 36 } # = 0x0C1C
+ - - {field_name: tx_stats_etherStatsPkts, width: 32, access_mode: RO, address_offset: 0x7070, radix_width: 36 } # = 0x1C1C
+ - - {field_name: rx_stats_etherStats_UndersizePkts, width: 32, access_mode: RO, address_offset: 0x3078, radix_width: 36 } # = 0x0C1E
+ - - {field_name: tx_stats_etherStats_UndersizePkts, width: 32, access_mode: RO, address_offset: 0x7078, radix_width: 36 } # = 0x1C1E
+ - - {field_name: rx_stats_etherStats_OversizePkts, width: 32, access_mode: RO, address_offset: 0x3080, radix_width: 36 } # = 0x0C20
+ - - {field_name: tx_stats_etherStats_OversizePkts, width: 32, access_mode: RO, address_offset: 0x7080, radix_width: 36 } # = 0x1C20
+ - - {field_name: rx_stats_etherStats_Pkts64Octets, width: 32, access_mode: RO, address_offset: 0x3088, radix_width: 36 } # = 0x0C22
+ - - {field_name: tx_stats_etherStats_Pkts64Octets, width: 32, access_mode: RO, address_offset: 0x7088, radix_width: 36 } # = 0x1C22
+ - - {field_name: rx_stats_etherStats_Pkts65to127Octets, width: 32, access_mode: RO, address_offset: 0x3090, radix_width: 36 } # = 0x0C24
+ - - {field_name: tx_stats_etherStats_Pkts65to127Octets, width: 32, access_mode: RO, address_offset: 0x7090, radix_width: 36 } # = 0x1C24
+ - - {field_name: rx_stats_etherStats_Pkts128to255Octets, width: 32, access_mode: RO, address_offset: 0x3098, radix_width: 36 } # = 0x0C26
+ - - {field_name: tx_stats_etherStats_Pkts128to255Octets, width: 32, access_mode: RO, address_offset: 0x7098, radix_width: 36 } # = 0x1C26
+ - - {field_name: rx_stats_etherStats_Pkts256to511Octets, width: 32, access_mode: RO, address_offset: 0x30a0, radix_width: 36 } # = 0x0C28
+ - - {field_name: tx_stats_etherStats_Pkts256to511Octets, width: 32, access_mode: RO, address_offset: 0x70a0, radix_width: 36 } # = 0x1C28
+ - - {field_name: rx_stats_etherStats_Pkts512to1023Octets, width: 32, access_mode: RO, address_offset: 0x30a8, radix_width: 36 } # = 0x0C2A
+ - - {field_name: tx_stats_etherStats_Pkts512to1023Octets, width: 32, access_mode: RO, address_offset: 0x70a8, radix_width: 36 } # = 0x1C2A
+ - - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, width: 32, access_mode: RO, address_offset: 0x30b0, radix_width: 36 } # = 0x0C2C
+ - - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, width: 32, access_mode: RO, address_offset: 0x70b0, radix_width: 36 } # = 0x1C2C
+ - - {field_name: rx_stats_etherStats_Pkts1519toXOctets, width: 32, access_mode: RO, address_offset: 0x30b8, radix_width: 36 } # = 0x0C2E
+ - - {field_name: tx_stats_etherStats_Pkts1519toXOctets, width: 32, access_mode: RO, address_offset: 0x70b8, radix_width: 36 } # = 0x1C2E
+ - - {field_name: rx_stats_etherStats_Fragments, width: 32, access_mode: RO, address_offset: 0x30c0, radix_width: 36 } # = 0x0C30
+ - - {field_name: tx_stats_etherStats_Fragments, width: 32, access_mode: RO, address_offset: 0x70c0, radix_width: 36 } # = 0x1C30
+ - - {field_name: rx_stats_etherStats_Jabbers, width: 32, access_mode: RO, address_offset: 0x30c8, radix_width: 36 } # = 0x0C32
+ - - {field_name: tx_stats_etherStats_Jabbers, width: 32, access_mode: RO, address_offset: 0x70c8, radix_width: 36 } # = 0x1C32
+ - - {field_name: rx_stats_etherStatsCRCErr, width: 32, access_mode: RO, address_offset: 0x30d0, radix_width: 36 } # = 0x0C34
+ - - {field_name: tx_stats_etherStatsCRCErr, width: 32, access_mode: RO, address_offset: 0x70d0, radix_width: 36 } # = 0x1C34
+ - - {field_name: rx_stats_unicastMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x30d8, radix_width: 36 } # = 0x0C36
+ - - {field_name: tx_stats_unicastMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x70d8, radix_width: 36 } # = 0x1C36
+ - - {field_name: rx_stats_multicastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x30e0, radix_width: 36 } # = 0x0C38
+ - - {field_name: tx_stats_multicastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x70e0, radix_width: 36 } # = 0x1C38
+ - - {field_name: rx_stats_broadcastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x30e8, radix_width: 36 } # = 0x0C3A
+ - - {field_name: tx_stats_broadcastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x70e8, radix_width: 36 } # = 0x1C3A
+ - - {field_name: rx_stats_PFCMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x30f0, radix_width: 36 } # = 0x0C3C
+ - - {field_name: tx_stats_PFCMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x70f0, radix_width: 36 } # = 0x1C3C
+
+
+ - peripheral_name: nw_10GbE_eth10g # pi_nw_10GbE_eth10g.py / pi_10GbE.py
+ peripheral_description: "10GbE link status register"
+ parameters:
+ # Parameters of nw_10GbE.vhd / tr_10GbE.vhd
+ - { name: g_nof_macs, value: 1 }
+ mm_ports:
+ # MM port for reg_eth10g_mosi in ip_arria10_e1sg_eth_10g.vhd / common_reg_r_w_dc.vhd
+ - mm_port_name: REG_NW_10GBE_ETH10G
+ mm_port_type: REG
+ mm_port_description: ""
+ number_of_mm_ports: g_nof_macs
+ fields:
+ - - field_name: tx_snk_out_xon
+ field_description: ""
+ width: 1
+ bit_offset: 0
+ access_mode: RO
+ address_offset: 0x0
+ - - field_name: xgmii_tx_ready
+ field_description: ""
+ width: 1
+ bit_offset: 1
+ access_mode: RO
+ address_offset: 0x0
+ - - field_name: xgmii_link_status
+ field_description: ""
+ width: 2
+ bit_offset: 2
+ access_mode: RO
+ address_offset: 0x0
diff --git a/libraries/io/nw_10GbE/nw_10GbE_word_to_byte_address.py b/libraries/io/nw_10GbE/nw_10GbE_word_to_byte_address.py
new file mode 100644
index 0000000000000000000000000000000000000000..49a6ab205d6a9c84eb75a35c25f21d8831d07546
--- /dev/null
+++ b/libraries/io/nw_10GbE/nw_10GbE_word_to_byte_address.py
@@ -0,0 +1,120 @@
+wo = [0x0000,
+ 0x0001,
+ 0x0040,
+ 0x0080,
+ 0x00C0,
+ 0x00C2,
+ 0x0100,
+ 0x0140,
+ 0x0800,
+ 0x0801,
+ 0x0802,
+ 0x0803,
+ 0x0804,
+ 0x0805,
+ 0x0806,
+ 0x0807,
+ 0x0808,
+ 0x0809,
+ 0x080A,
+ 0x080B,
+ 0x0818,
+ 0x1000,
+ 0x1001,
+ 0x1040,
+ 0x1080,
+ 0x10C0,
+ 0x1100,
+ 0x1140,
+ 0x1141,
+ 0x1142,
+
+ 0x1180,
+ 0x1181,
+ 0x1182,
+ 0x1183,
+ 0x1184,
+ 0x1185,
+ 0x1186,
+ 0x1187,
+ 0x1190,
+ 0x1191,
+ 0x1192,
+ 0x1193,
+ 0x1194,
+ 0x1195,
+ 0x1196,
+ 0x1197,
+
+ 0x11A0,
+ 0x1200,
+ 0x1201,
+ 0x1202,
+ 0x1801,
+ 0x0C00,
+ 0x1C00,
+ 0x0C02,
+ 0x1C02,
+ 0x0C04,
+ 0x1C04,
+ 0x0C06,
+ 0x1C06,
+ 0x0C08,
+ 0x1C08,
+ 0x0C0A,
+ 0x1C0A,
+ 0x0C0C,
+ 0x1C0C,
+ 0x0C0E,
+ 0x1C0E,
+ 0x0C10,
+ 0x1C10,
+ 0x0C12,
+ 0x1C12,
+ 0x0C14,
+ 0x1C14,
+ 0x0C16,
+ 0x1C16,
+ 0x0C18,
+ 0x1C18,
+ 0x0C1A,
+ 0x1C1A,
+ 0x0C1C,
+ 0x1C1C,
+ 0x0C1E,
+ 0x1C1E,
+ 0x0C20,
+ 0x1C20,
+ 0x0C22,
+ 0x1C22,
+ 0x0C24,
+ 0x1C24,
+ 0x0C26,
+ 0x1C26,
+ 0x0C28,
+ 0x1C28,
+ 0x0C2A,
+ 0x1C2A,
+ 0x0C2C,
+ 0x1C2C,
+ 0x0C2E,
+ 0x1C2E,
+ 0x0C30,
+ 0x1C30,
+ 0x0C32,
+ 0x1C32,
+ 0x0C34,
+ 0x1C34,
+ 0x0C36,
+ 0x1C36,
+ 0x0C38,
+ 0x1C38,
+ 0x0C3A,
+ 0x1C3A,
+ 0x0C3C,
+ 0x1C3C]
+
+for a in wo:
+ #print '%x' % (a*4) # python v2
+ print('0x{:04x}'.format(a*4)) # python3
+
diff --git a/libraries/io/ppsh/ppsh.peripheral.yaml b/libraries/io/ppsh/ppsh.peripheral.yaml
index f3b7cd60ae05e8705cd514d890b861324aea573c..e732647b7504398f8be33e9bb3c96763b2d1396b 100644
--- a/libraries/io/ppsh/ppsh.peripheral.yaml
+++ b/libraries/io/ppsh/ppsh.peripheral.yaml
@@ -1,47 +1,68 @@
-schema_name : args
+schema_name: args
schema_version: 1.0
-schema_type : peripheral
+schema_type: peripheral
-hdl_library_name : ppsh
-hdl_library_description: " This is the description for the finppshge_stop library "
+hdl_library_name: ppsh
+hdl_library_description: "Pulse Per Second Handler"
peripherals:
- -
- peripheral_name: ppsh
+ - peripheral_name: ppsh # pi_ppsh.py
+ peripheral_description: |
+ "Capture PPS input signal and monitor its period. See description in [1, 2] and usage in [3].
+
+ [1] https://git.astron.nl/desp/hdl/-/blob/master/libraries/io/ppsh/doc/ASTRON_RP_1374_ppsh_module_description.pdf
+ [2] https://git.astron.nl/desp/hdl/-/blob/master/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
+ [3] https://git.astron.nl/desp/upe_gear/-/blob/master/peripherals/util_ppsh.py"
parameters:
+ # parameters of ppsh_reg.vhd
- { name: g_cross_clock_domain, value: TRUE }
- { name: g_st_clk_freq, value: 200 * 10**6 }
- slave_ports:
- # actual hdl name: reg_ppsh
- - slave_name : PPSH
- slave_type : REG
+ mm_ports:
+ # MM port for ppsh_reg.vhd
+ - mm_port_name: PIO_PPS # pi_ppsh.py and in QSYS system.h
+ mm_port_type: REG
+ mm_port_description: "Monitor and control PPS input."
+ dual_clock: g_cross_clock_domain
fields:
- - - field_name : status
- access_mode : RO
+ - - field_name: capture_cnt
+ field_description: "Measured number of clock cycles between captured PPS pulses."
+ width: 30
+ bit_offset: 0
+ access_mode: RO
+ address_offset: 0x0
+
+ - - field_name: stable
+ field_description: "PPS is stable (1) when capture_cnt = expected_cnt for all PPS periods since last time status was read, else PPS is not stable (0)."
+ width: 1
+ bit_offset: 30
+ access_mode: RO
+ address_offset: 0x0
+
+ - - field_name: toggle
+ field_description: "Level bit that toggles after every PPS."
+ width: 1
+ bit_offset: 31
+ access_mode: RO
address_offset: 0x0
- field_description: " ppsh status "
- - - field_name : control
+ - - field_name: expected_cnt
+ field_description: "Expected number of clock cycles between captured PPS pulses."
+ width: ceil_log2(g_st_clk_freq)
+ bit_offset: 0
+ access_mode: RW
+ address_offset: 0x4
+
+ - - field_name: edge
+ field_description: "When 0 then clock PPS in on rising edge of clock, else when 1 use falling edge of clock."
+ width: 1
+ bit_offset: 31
+ access_mode: RW
address_offset: 0x4
- field_description: " ppsh control "
- - - field_name : offset
+
+ - - field_name: offset_cnt
+ field_description: "Number of clock cycles at read access, that has passed since last PPS."
address_offset: 0x8
- field_description: " ppsh offset count "
- slave_discription: " "
-
- peripheral_description: |
- "
- . Report PPS toggle, stable and period capture count
- . Set dp_clk capture edge for PPS
- Set expected period capture count for PPS stable
- +----------------------------------------------------------------------------+
- |31 (byte3) 24|23 (byte2) 16|15 (byte1) 8|7 (byte0) 0| wi |
- |-----------------------------------------------------------------------|----|
- |toggle[31], stable[30] xxx capture_cnt = [29:0]| 0 |
- |-----------------------------------------------------------------------|----|
- |edge[31], xxx expected_cnt = [29:0]| 1 |
- |-----------------------------------------------------------------------|----|
- | xxx offset_cnt = [29:0]| 2 |
- +----------------------------------------------------------------------------+"
-
+ width: ceil_log2(g_st_clk_freq)
+ access_mode: RO
+
diff --git a/libraries/io/remu/remu.peripheral.yaml b/libraries/io/remu/remu.peripheral.yaml
index 34bcce2aab6ba0d5eab44eefc655261965f4e288..eb13be5b392fb259f245e132111fe583b06b5837 100644
--- a/libraries/io/remu/remu.peripheral.yaml
+++ b/libraries/io/remu/remu.peripheral.yaml
@@ -1,79 +1,68 @@
-schema_name : args
+schema_name: args
schema_version: 1.0
-schema_type : peripheral
+schema_type: peripheral
-hdl_library_name : remu
-hdl_library_description: " This is the description for the remu package "
+hdl_library_name: remu
+hdl_library_description: "Remote Update (REMU)"
peripherals:
-
- # peripheral, remu_reg
- - peripheral_name: remu
-
+ - peripheral_name: remu # pi_remu.py
+ peripheral_description: |
+ "Remote update to load the factory image or the user from flash into the the FPGA. See description in [1] and usage in [2].
+
+ [1] https://git.astron.nl/desp/hdl/-/blob/master/libraries/io/remu/src/vhdl/remu_reg.vhd
+ [2] https://git.astron.nl/desp/upe_gear/-/blob/master/peripherals/util_remu.py"
parameters:
+ # parameters of remu_reg.vhd
- { name: g_data_w, value: 24 }
- slave_ports:
- # actual hdl name: reg_remu
- - slave_name : REMU
- slave_type : REG
+ mm_ports:
+ # MM port for remu_reg.vhd
+ - mm_port_name: REG_REMU # pi_remu.py and in QSYS system.h
+ mm_port_type: REG
+ mm_port_description: "Remote update."
fields:
- - - field_name : reconfigure_key
- width : c_word_w
- access_mode : WO
+ - - field_name: reconfigure
+ field_description: "Use 0xB007FAC7 (= boot factory) as password to reconfigure."
+ width: c_word_w
+ access_mode: WO
address_offset: 0x0
- field_description: " reconfigure key for safety "
- - - field_name : param
- width : 3
- access_mode : WO
+ - - field_name: param
+ field_description: "param"
+ width: 3
+ access_mode: WO
address_offset: 0x4
- radix : unsigned
- field_description: " "
- - - field_name : read_param
- width : 1
- access_mode : WO
- side_effect : PW
+ - - field_name: read_param
+ field_description: "read_param"
+ width: 1
+ access_mode: WO
+ side_effect: PW
address_offset: 0x8
- field_description: " read_param "
- - - field_name : write_param
- width : 1
- access_mode : WO
- side_effect : PW
+ - - field_name: write_param
+ field_description: "write_param"
+ width: 1
+ access_mode: WO
+ side_effect: PW
address_offset: 0xc
- field_description: " write_param "
- - - field_name : data_out
- width : g_data_w
- access_mode : RO
+ - - field_name: data_out
+ field_description: "data_out"
+ width: g_data_w
+ access_mode: RO
address_offset: 0x10
- field_description: " data_out "
- - - field_name : data_in
- width : g_data_w
- access_mode : WO
+ - - field_name: data_in
+ field_description: "data_in"
+ width: g_data_w
+ access_mode: WO
address_offset: 0x14
- field_description: " data_in "
- - - field_name : busy
- width : 1
- access_mode : RO
+ - - field_name: busy
+ field_description: "busy"
+ width: 1
+ access_mode: RO
address_offset: 0x18
- field_description: " busy "
-
- slave_description: " Remote Upgrade "
- peripheral_description: |
- "wi Bits R/W SE Name Default Description |REG_EPCS|
- =============================================================================
- 0 [31..0] WO reconfigure_key 0x0
- 1 [2..0] WO param
- 2 [0] WO PW read_param
- 3 [0] WO PW write_param
- 4 [23..0] RO data_out
- 5 [23..0] WO data_in
- 6 [0] RO busy
- =============================================================================
- "
diff --git a/libraries/technology/ip_arria10_e1sg/generate-all-ip.sh b/libraries/technology/ip_arria10_e1sg/generate-all-ip.sh
deleted file mode 100755
index c35c6f1060310afcc7e7171bd10195cc48abcdb7..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/generate-all-ip.sh
+++ /dev/null
@@ -1,21 +0,0 @@
-#!/bin/bash
-
-files=`find $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg -name 'generate_ip.sh' `
-
-echo -e "About to generate the following IP blocks:\n$files\n"
-
-for f in $files ; do
- cd `dirname $f`
-
- echo
- echo -n "Entering directory: "
- pwd
- echo
-
- rm -rf generated
- ./`basename $f`
-
- cd -
-done
-
-echo "Done"
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index d57dddde374e5dcca8eaab2f35dd22a9b6b50e68..105a6387e99a03de89c336edede0fb71ffca64d4 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -117,8 +117,6 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL jesd204b_sysref_2 : STD_LOGIC;
SIGNAL jesd204b_sysref_frameclk_1 : STD_LOGIC;
SIGNAL jesd204b_sysref_frameclk_2 : STD_LOGIC;
- SIGNAL jesd204b_sysref_linkclk_1 : STD_LOGIC;
- SIGNAL jesd204b_sysref_linkclk_2 : STD_LOGIC;
-- Data path
SIGNAL jesd204b_rx_link_data_arr : STD_LOGIC_VECTOR(c_jesd204b_rx_data_w*g_nof_streams-1 DOWNTO 0);
@@ -176,7 +174,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
rxphy_clk : out std_logic_vector(0 downto 0); -- export
sof : out std_logic_vector(3 downto 0); -- export
somf : out std_logic_vector(c_jesd204b_rx_somf_w-1 downto 0); -- export
@@ -399,7 +397,6 @@ BEGIN
END IF;
END PROCESS;
-
-----------------------------------------------------------------------------
-- Move sysref from rxlink_clk to rxframe_clk
-----------------------------------------------------------------------------
@@ -412,7 +409,7 @@ BEGIN
ELSE
IF rising_edge(rxframe_clk) THEN
jesd204b_sysref_frameclk_1 <= jesd204b_sysref_2; -- sysref from rxlink_clk domain
- jesd204b_sysref_frameclk_2 <= jesd204b_sysref_linkclk_1;
+ jesd204b_sysref_frameclk_2 <= jesd204b_sysref_frameclk_1;
IF jesd204b_sysref_frameclk_1 = '1' and jesd204b_sysref_frameclk_2 = '0' THEN
rx_sysref <= '1';
ELSE
diff --git a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..4c748e535c27266b3077edf9f05275364aedd2d1
--- /dev/null
+++ b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
@@ -0,0 +1,66 @@
+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: tech_jesd204b
+hdl_library_description: "JESD204b peripherals for ADC interface."
+
+peripherals:
+ - peripheral_name: jesd_ctrl # pi_jesd_ctrl.py
+ peripheral_description: "Reset JESD, and enable/disable individual JESD inputs"
+ mm_ports:
+ # MM port for node_adc_input_and_timing.vhd
+ - mm_port_name: PIO_JESD_CTRL
+ mm_port_type: REG
+ mm_port_description: ""
+ fields:
+ - - field_name: reset
+ field_description: "Write 1 to reset the full JESD interface for all JESD signal inputs."
+ width: 1
+ bit_offset: 31
+ access_mode: RW
+ address_offset: 0x0
+ - - field_name: enable
+ field_description: "Enable JESD signal input i by setting bit i = 1, disable by clearing bit i = 0."
+ width: 31
+ bit_offset: 0
+ access_mode: RW
+ address_offset: 0x0
+
+ - peripheral_name: jesd204b_arria10 # pi_jesd204b_unb2.py
+ peripheral_description: |
+ "M&C of Intel Arria10 JESD204B ADC interface IP, see https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf"
+ mm_ports:
+ # MM port for tech_jesd204b.vhd
+ - mm_port_name: REG_JESD204B
+ mm_port_type: REG
+ mm_port_description: ""
+ fields:
+ - - {field_name: rx_dll_ctrl, width: 17, bit_offset: 0, access_mode: RW, address_offset: 0x50}
+ - - {field_name: rx_syncn_sysref_ctrl, width: 25, bit_offset: 0, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_lmfc_offset, width: 8, bit_offset: 12, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_rbd_offset, width: 8, bit_offset: 3, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_sysref_always_on, width: 1, bit_offset: 1, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_err0, width: 9, bit_offset: 0, access_mode: RW, address_offset: 0x60}
+ - - {field_name: rx_err1, width: 10, bit_offset: 0, access_mode: RW, address_offset: 0x64}
+ - - {field_name: csr_rbd_count, width: 8, bit_offset: 3, access_mode: RO, address_offset: 0x80}
+ - - {field_name: csr_dev_syncn, width: 1, bit_offset: 0, access_mode: RO, address_offset: 0x80}
+ - - {field_name: rx_status1, width: 24, bit_offset: 0, access_mode: RW, address_offset: 0x84}
+ - - {field_name: rx_status2, width: 24, bit_offset: 0, access_mode: RW, address_offset: 0x88}
+ - - {field_name: rx_status3, width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x8C}
+ - - {field_name: rx_ilas_csr_m, width: 8, bit_offset: 24, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_k, width: 5, bit_offset: 16, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_f, width: 8, bit_offset: 8, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_l, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_hd, width: 1, bit_offset: 31, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_cf, width: 5, bit_offset: 24, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_jesdv, width: 3, bit_offset: 21, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_s, width: 5, bit_offset: 16, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_subclassv, width: 3, bit_offset: 13, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_np, width: 5, bit_offset: 8, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_cs, width: 2, bit_offset: 6, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_n, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_status4, width: 16, bit_offset: 0, access_mode: RW, address_offset: 0xF0}
+ - - {field_name: rx_status5, width: 16, bit_offset: 0, access_mode: RW, address_offset: 0xF4}
+ - - {field_name: rx_status6, width: 24, bit_offset: 0, access_mode: RW, address_offset: 0xF8}
+ - - {field_name: rx_status7, width: 32, bit_offset: 0, access_mode: RO, address_offset: 0xFC}