diff --git a/boards/uniboard2/designs/unb2_test/build/quartus/unb2_test.qsf b/boards/uniboard2/designs/unb2_test/build/quartus/unb2_test.qsf
deleted file mode 100644
index 20fb5335f2e322ad9d51c094257bf77256c34f4d..0000000000000000000000000000000000000000
--- a/boards/uniboard2/designs/unb2_test/build/quartus/unb2_test.qsf
+++ /dev/null
@@ -1,1675 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1a10.0 Build 346 11/13/2013 SJ Full Version
-# Date created = 08:55:45  March 13, 2014
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		unb2_test_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.8 V"
-set_global_assignment -name FAMILY "Arria 10"
-set_global_assignment -name TOP_LEVEL_ENTITY unb2_test
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:55:45  MARCH 13, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION 14.0
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
-set_global_assignment -name USER_START_UP_CLOCK ON
-
-# IO Location Assignments from Gijs
-#
-
-# rx pins modified from chip planner
-# # tx pins as per Gijs
-#
-
-set_location_assignment PIN_AJ38 -to QSFP_0_RX[0]
-set_location_assignment PIN_AJ37 -to "QSFP_0_RX[0](n)"
-set_location_assignment PIN_AK40 -to QSFP_0_RX[1]
-set_location_assignment PIN_AK39 -to "QSFP_0_RX[1](n)"
-set_location_assignment PIN_AM40 -to QSFP_0_RX[2]
-set_location_assignment PIN_AM39 -to "QSFP_0_RX[2](n)"
-set_location_assignment PIN_AN38 -to QSFP_0_RX[3]
-set_location_assignment PIN_AN37 -to "QSFP_0_RX[3](n)"
-set_location_assignment PIN_AJ42 -to QSFP_0_TX[0]
-set_location_assignment PIN_AJ41 -to "QSFP_0_TX[0](n)"
-set_location_assignment PIN_AK44 -to QSFP_0_TX[1]
-set_location_assignment PIN_AK43 -to "QSFP_0_TX[1](n)"
-set_location_assignment PIN_AM44 -to QSFP_0_TX[2]
-set_location_assignment PIN_AM43 -to "QSFP_0_TX[2](n)"
-set_location_assignment PIN_AN42 -to QSFP_0_TX[3]
-set_location_assignment PIN_AN41 -to "QSFP_0_TX[3](n)"
-set_location_assignment PIN_AC38 -to QSFP_1_RX[0]
-set_location_assignment PIN_AC37 -to "QSFP_1_RX[0](n)"
-set_location_assignment PIN_AD40 -to QSFP_1_RX[1]
-set_location_assignment PIN_AD39 -to "QSFP_1_RX[1](n)"
-set_location_assignment PIN_AF40 -to QSFP_1_RX[2]
-set_location_assignment PIN_AF39 -to "QSFP_1_RX[2](n)"
-set_location_assignment PIN_AG38 -to QSFP_1_RX[3]
-set_location_assignment PIN_AG37 -to "QSFP_1_RX[3](n)"
-set_location_assignment PIN_AC42 -to QSFP_1_TX[0]
-set_location_assignment PIN_AC41 -to "QSFP_1_TX[0](n)"
-set_location_assignment PIN_AD44 -to QSFP_1_TX[1]
-set_location_assignment PIN_AD43 -to "QSFP_1_TX[1](n)"
-set_location_assignment PIN_AF44 -to QSFP_1_TX[2]
-set_location_assignment PIN_AF43 -to "QSFP_1_TX[2](n)"
-set_location_assignment PIN_AG42 -to QSFP_1_TX[3]
-set_location_assignment PIN_AG41 -to "QSFP_1_TX[3](n)"
-set_location_assignment PIN_AB40 -to QSFP_2_RX[0]
-set_location_assignment PIN_AB39 -to "QSFP_2_RX[0](n)"
-set_location_assignment PIN_AE38 -to QSFP_2_RX[1]
-set_location_assignment PIN_AE37 -to "QSFP_2_RX[1](n)"
-set_location_assignment PIN_AH40 -to QSFP_2_RX[2]
-set_location_assignment PIN_AH39 -to "QSFP_2_RX[2](n)"
-set_location_assignment PIN_AL38 -to QSFP_2_RX[3]
-set_location_assignment PIN_AL37 -to "QSFP_2_RX[3](n)"
-set_location_assignment PIN_AB44 -to QSFP_2_TX[0]
-set_location_assignment PIN_AB43 -to "QSFP_2_TX[0](n)"
-set_location_assignment PIN_AE42 -to QSFP_2_TX[1]
-set_location_assignment PIN_AE41 -to "QSFP_2_TX[1](n)"
-set_location_assignment PIN_AH44 -to QSFP_2_TX[2]
-set_location_assignment PIN_AH43 -to "QSFP_2_TX[2](n)"
-set_location_assignment PIN_AL42 -to QSFP_2_TX[3]
-set_location_assignment PIN_AL41 -to "QSFP_2_TX[3](n)"
-set_location_assignment PIN_W38 -to QSFP_3_RX[0]
-set_location_assignment PIN_W37 -to "QSFP_3_RX[0](n)"
-set_location_assignment PIN_T40 -to QSFP_3_RX[1]
-set_location_assignment PIN_T39 -to "QSFP_3_RX[1](n)"
-set_location_assignment PIN_N38 -to QSFP_3_RX[2]
-set_location_assignment PIN_N37 -to "QSFP_3_RX[2](n)"
-set_location_assignment PIN_K40 -to QSFP_3_RX[3]
-set_location_assignment PIN_K39 -to "QSFP_3_RX[3](n)"
-set_location_assignment PIN_W42 -to QSFP_3_TX[0]
-set_location_assignment PIN_W41 -to "QSFP_3_TX[0](n)"
-set_location_assignment PIN_T44 -to QSFP_3_TX[1]
-set_location_assignment PIN_T43 -to "QSFP_3_TX[1](n)"
-set_location_assignment PIN_N42 -to QSFP_3_TX[2]
-set_location_assignment PIN_N41 -to "QSFP_3_TX[2](n)"
-set_location_assignment PIN_K44 -to QSFP_3_TX[3]
-set_location_assignment PIN_K43 -to "QSFP_3_TX[3](n)"
-set_location_assignment PIN_U38 -to QSFP_4_RX[0]
-set_location_assignment PIN_U37 -to "QSFP_4_RX[0](n)"
-set_location_assignment PIN_V40 -to QSFP_4_RX[1]
-set_location_assignment PIN_V39 -to "QSFP_4_RX[1](n)"
-set_location_assignment PIN_Y40 -to QSFP_4_RX[2]
-set_location_assignment PIN_Y39 -to "QSFP_4_RX[2](n)"
-set_location_assignment PIN_AA38 -to QSFP_4_RX[3]
-set_location_assignment PIN_AA37 -to "QSFP_4_RX[3](n)"
-set_location_assignment PIN_U42 -to QSFP_4_TX[0]
-set_location_assignment PIN_U41 -to "QSFP_4_TX[0](n)"
-set_location_assignment PIN_V44 -to QSFP_4_TX[1]
-set_location_assignment PIN_V43 -to "QSFP_4_TX[1](n)"
-set_location_assignment PIN_Y44 -to QSFP_4_TX[2]
-set_location_assignment PIN_Y43 -to "QSFP_4_TX[2](n)"
-set_location_assignment PIN_AA42 -to QSFP_4_TX[3]
-set_location_assignment PIN_AA41 -to "QSFP_4_TX[3](n)"
-set_location_assignment PIN_L38 -to QSFP_5_RX[0]
-set_location_assignment PIN_L37 -to "QSFP_5_RX[0](n)"
-set_location_assignment PIN_M40 -to QSFP_5_RX[1]
-set_location_assignment PIN_M39 -to "QSFP_5_RX[1](n)"
-set_location_assignment PIN_P40 -to QSFP_5_RX[2]
-set_location_assignment PIN_P39 -to "QSFP_5_RX[2](n)"
-set_location_assignment PIN_R38 -to QSFP_5_RX[3]
-set_location_assignment PIN_R37 -to "QSFP_5_RX[3](n)"
-set_location_assignment PIN_L42 -to QSFP_5_TX[0]
-set_location_assignment PIN_L41 -to "QSFP_5_TX[0](n)"
-set_location_assignment PIN_M44 -to QSFP_5_TX[1]
-set_location_assignment PIN_M43 -to "QSFP_5_TX[1](n)"
-set_location_assignment PIN_P44 -to QSFP_5_TX[2]
-set_location_assignment PIN_P43 -to "QSFP_5_TX[2](n)"
-set_location_assignment PIN_R42 -to QSFP_5_TX[3]
-set_location_assignment PIN_R41 -to "QSFP_5_TX[3](n)"
-#
-#
-set_location_assignment PIN_K15 -to CLK
-set_location_assignment PIN_J15 -to "CLK(n)"
-set_location_assignment PIN_N12 -to ETH_CLK
-set_location_assignment PIN_K14 -to PPS
-set_location_assignment PIN_J14 -to "PPS(n)"
-set_location_assignment PIN_Y36 -to SA_CLK
-set_location_assignment PIN_Y35 -to "SA_CLK(n)"
-set_location_assignment PIN_AH9 -to SB_CLK
-set_location_assignment PIN_AH10 -to "SB_CLK(n)"
-# eth sgin (1) located by quartus
-
-
-#set_location_assignment PIN_AT33 -to CFG_DATA[0]
-#set_location_assignment PIN_AT32 -to CFG_DATA[1]
-#set_location_assignment PIN_BB33 -to CFG_DATA[2]
-#set_location_assignment PIN_BA33 -to CFG_DATA[3]
-
-
-
-# Memory pins read back from quartus chip planner
-set_location_assignment PIN_AP20 -to MB_I_A[0]
-set_location_assignment PIN_AR20 -to MB_I_A[1]
-set_location_assignment PIN_AP19 -to MB_I_A[2]
-set_location_assignment PIN_AR19 -to MB_I_A[3]
-set_location_assignment PIN_AR18 -to MB_I_A[4]
-set_location_assignment PIN_AT17 -to MB_I_A[5]
-set_location_assignment PIN_AU19 -to MB_I_A[6]
-set_location_assignment PIN_AT18 -to MB_I_A[7]
-set_location_assignment PIN_AL17 -to MB_I_A[8]
-set_location_assignment PIN_AM18 -to MB_I_A[9]
-set_location_assignment PIN_AM19 -to MB_I_A[10]
-set_location_assignment PIN_AN19 -to MB_I_A[11]
-set_location_assignment PIN_BA17 -to MB_I_A[12]
-set_location_assignment PIN_BD17 -to MB_I_A[13]
-set_location_assignment PIN_AY18 -to MB_I_ACT_N[0]
-set_location_assignment PIN_AV29 -to MB_I_ALERT_N[0]
-set_location_assignment PIN_BB16 -to MB_I_BA[0]
-set_location_assignment PIN_BD16 -to MB_I_BA[1]
-set_location_assignment PIN_BC16 -to MB_I_BG[0]
-set_location_assignment PIN_AW19 -to MB_I_BG[1]
-set_location_assignment PIN_BA15 -to MB_I_CAS_A15
-set_location_assignment PIN_BC21 -to MB_I_CB[0]
-set_location_assignment PIN_BA22 -to MB_I_CB[1]
-set_location_assignment PIN_BD21 -to MB_I_CB[2]
-set_location_assignment PIN_BB20 -to MB_I_CB[3]
-set_location_assignment PIN_BA20 -to MB_I_CB[4]
-set_location_assignment PIN_BD20 -to MB_I_CB[5]
-set_location_assignment PIN_AY20 -to MB_I_CB[6]
-set_location_assignment PIN_AY22 -to MB_I_CB[7]
-set_location_assignment PIN_AU18 -to MB_I_CK[0]
-set_location_assignment PIN_AV18 -to MB_I_CK_n[0]
-set_location_assignment PIN_AT16 -to MB_I_CK[1]
-set_location_assignment PIN_AU16 -to MB_I_CK_n[1]
-set_location_assignment PIN_BB19 -to MB_I_CKE[0]
-set_location_assignment PIN_AP16 -to MB_I_CKE[1]
-set_location_assignment PIN_AY19 -to MB_I_CS[0]
-set_location_assignment PIN_AN16 -to MB_I_CS[1]
-set_location_assignment PIN_BC29 -to MB_I_DM[0]
-set_location_assignment PIN_AR27 -to MB_I_DM[1]
-set_location_assignment PIN_BD24 -to MB_I_DM[2]
-set_location_assignment PIN_AM23 -to MB_I_DM[3]
-set_location_assignment PIN_AU12 -to MB_I_DM[4]
-set_location_assignment PIN_AU13 -to MB_I_DM[5]
-set_location_assignment PIN_AM14 -to MB_I_DM[6]
-set_location_assignment PIN_AM16 -to MB_I_DM[7]
-set_location_assignment PIN_BA21 -to MB_I_DM[8]
-set_location_assignment PIN_BA28 -to MB_I_DQS[0]
-set_location_assignment PIN_AM28 -to MB_I_DQS[1]
-set_location_assignment PIN_AV24 -to MB_I_DQS[2]
-set_location_assignment PIN_AN24 -to MB_I_DQS[3]
-set_location_assignment PIN_BC14 -to MB_I_DQS[4]
-set_location_assignment PIN_AW14 -to MB_I_DQS[5]
-set_location_assignment PIN_AN12 -to MB_I_DQS[6]
-set_location_assignment PIN_AK15 -to MB_I_DQS[7]
-set_location_assignment PIN_BC22 -to MB_I_DQS[8]
-
-set_location_assignment PIN_BD19 -to MB_I_ODT[0]
-set_location_assignment PIN_AR17 -to MB_I_ODT[1]
-set_location_assignment PIN_BC18 -to MB_I_PARITY[0]
-set_location_assignment PIN_BB15 -to MB_I_RAS_A16
-set_location_assignment PIN_BB21 -to MB_I_REF_CLK
-set_location_assignment PIN_AV19 -to MB_I_RESET_N[0]
-set_location_assignment PIN_AY17 -to MB_I_RZQ
-set_location_assignment PIN_BC17 -to MB_I_WE_A14
-set_location_assignment PIN_A29 -to MB_II_A[0]
-set_location_assignment PIN_B29 -to MB_II_A[1]
-set_location_assignment PIN_H29 -to MB_II_A[2]
-set_location_assignment PIN_G29 -to MB_II_A[3]
-set_location_assignment PIN_D29 -to MB_II_A[4]
-set_location_assignment PIN_E29 -to MB_II_A[5]
-set_location_assignment PIN_C29 -to MB_II_A[6]
-set_location_assignment PIN_C28 -to MB_II_A[7]
-set_location_assignment PIN_E30 -to MB_II_A[8]
-set_location_assignment PIN_D30 -to MB_II_A[9]
-set_location_assignment PIN_B28 -to MB_II_A[10]
-set_location_assignment PIN_A28 -to MB_II_A[11]
-set_location_assignment PIN_H27 -to MB_II_A[12]
-set_location_assignment PIN_E28 -to MB_II_A[13]
-set_location_assignment PIN_K28 -to MB_II_ACT_N[0]
-set_location_assignment PIN_C16 -to MB_II_ALERT_N[0]
-set_location_assignment PIN_C27 -to MB_II_BA[0]
-set_location_assignment PIN_A27 -to MB_II_BA[1]
-set_location_assignment PIN_B26 -to MB_II_BG[0]
-set_location_assignment PIN_L27 -to MB_II_BG[1]
-set_location_assignment PIN_F28 -to MB_II_CAS_A15
-set_location_assignment PIN_E24 -to MB_II_CB[0]
-set_location_assignment PIN_J25 -to MB_II_CB[1]
-set_location_assignment PIN_A25 -to MB_II_CB[2]
-set_location_assignment PIN_G25 -to MB_II_CB[3]
-set_location_assignment PIN_D25 -to MB_II_CB[4]
-set_location_assignment PIN_K25 -to MB_II_CB[5]
-set_location_assignment PIN_D24 -to MB_II_CB[6]
-set_location_assignment PIN_F25 -to MB_II_CB[7]
-set_location_assignment PIN_N27 -to MB_II_CK[0]
-set_location_assignment PIN_M28 -to MB_II_CK_n[0]
-set_location_assignment PIN_K27 -to MB_II_CK[1]
-set_location_assignment PIN_J26 -to MB_II_CK_n[1]
-set_location_assignment PIN_N28 -to MB_II_CKE[0]
-set_location_assignment PIN_P26 -to MB_II_CKE[1]
-set_location_assignment PIN_K29 -to MB_II_CS[0]
-set_location_assignment PIN_H26 -to MB_II_CS[1]
-set_location_assignment PIN_A16 -to MB_II_DM[0]
-set_location_assignment PIN_M21 -to MB_II_DM[1]
-set_location_assignment PIN_K22 -to MB_II_DM[2]
-set_location_assignment PIN_D19 -to MB_II_DM[3]
-set_location_assignment PIN_G30 -to MB_II_DM[4]
-set_location_assignment PIN_R32 -to MB_II_DM[5]
-set_location_assignment PIN_G32 -to MB_II_DM[6]
-set_location_assignment PIN_AC32 -to MB_II_DM[7]
-set_location_assignment PIN_E25 -to MB_II_DM[8]
-set_location_assignment PIN_F17 -to MB_II_DQS[0]
-set_location_assignment PIN_L20 -to MB_II_DQS[1]
-set_location_assignment PIN_J22 -to MB_II_DQS[2]
-set_location_assignment PIN_B19 -to MB_II_DQS[3]
-set_location_assignment PIN_L31 -to MB_II_DQS[4]
-set_location_assignment PIN_P31 -to MB_II_DQS[5]
-set_location_assignment PIN_N33 -to MB_II_DQS[6]
-set_location_assignment PIN_T33 -to MB_II_DQS[7]
-set_location_assignment PIN_A26 -to MB_II_DQS[8]
-
-set_location_assignment PIN_K30 -to MB_II_ODT[0]
-set_location_assignment PIN_R27 -to MB_II_ODT[1]
-set_location_assignment PIN_R28 -to MB_II_PARITY[0]
-set_location_assignment PIN_G28 -to MB_II_RAS_A16
-set_location_assignment PIN_G31 -to MB_II_REF_CLK
-set_location_assignment PIN_L28 -to MB_II_RESET_N[0]
-set_location_assignment PIN_P20 -to MB_II_RZQ
-set_location_assignment PIN_F27 -to MB_II_WE_A14
-
-# IO Standard Assignments from Gijs (excluding memory)
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_CLK
-set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[0]
-set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[0](n)"
-set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[1]
-set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[1](n)"
-set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGOUT[0]
-set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGOUT[0](n)"
-set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGOUT[1]
-set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGOUT[1](n)"
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[2]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[3]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[4]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[5]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[6]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[7]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to INTA
-set_instance_assignment -name IO_STANDARD "1.8 V" -to INTB
-set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SC
-set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SD
-set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_ALERT
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_RX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_RX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_RX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_RX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_RX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_RX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_RX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_RX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_TX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_TX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_TX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_TX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_TX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_TX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_0_TX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_0_TX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_RX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_RX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_RX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_RX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_RX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_RX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_RX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_RX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_TX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_TX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_TX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_TX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_TX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_TX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_1_TX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_1_TX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_RX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_RX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_RX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_RX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_RX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_RX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_RX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_RX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_TX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_TX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_TX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_TX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_TX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_TX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_2_TX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_2_TX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_RX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_RX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_RX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_RX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_RX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_RX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_RX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_RX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_TX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_TX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_TX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_TX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_TX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_TX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_3_TX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_3_TX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_RX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_RX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_RX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_RX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_RX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_RX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_RX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_RX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_TX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_TX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_TX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_TX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_TX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_TX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_4_TX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_4_TX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_RX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_RX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_RX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_RX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_RX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_RX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_RX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_RX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_TX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_TX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_TX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_TX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_TX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_TX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFP_5_TX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "QSFP_5_TX[3](n)"
-set_instance_assignment -name IO_STANDARD LVDS -to SA_CLK
-set_instance_assignment -name IO_STANDARD LVDS -to "SA_CLK(n)"
-set_instance_assignment -name IO_STANDARD LVDS -to SB_CLK
-set_instance_assignment -name IO_STANDARD LVDS -to "SB_CLK(n)"
-set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
-set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
-set_instance_assignment -name IO_STANDARD "1.8 V" -to SENS_SC
-set_instance_assignment -name IO_STANDARD "1.8 V" -to SENS_SD
-set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[2]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[3]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[4]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[5]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[6]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[7]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to VERSION[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to VERSION[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to WDI
-set_location_assignment PIN_U12 -to ID[0]
-set_location_assignment PIN_V12 -to ID[1]
-set_location_assignment PIN_Y12 -to ID[2]
-set_location_assignment PIN_U14 -to ID[3]
-set_location_assignment PIN_U13 -to ID[4]
-set_location_assignment PIN_Y13 -to ID[5]
-set_location_assignment PIN_AA12 -to ID[6]
-set_location_assignment PIN_T13 -to ID[7]
-set_location_assignment PIN_AU31 -to INTA
-set_location_assignment PIN_AR30 -to INTB
-set_location_assignment PIN_BA25 -to PMBUS_SC
-set_location_assignment PIN_BD25 -to PMBUS_SD
-set_location_assignment PIN_BD26 -to PMBUS_ALERT
-set_location_assignment PIN_BC31 -to SENS_SC
-set_location_assignment PIN_BB31 -to SENS_SD
-set_location_assignment PIN_AN32 -to TESTIO[0]
-set_location_assignment PIN_AP32 -to TESTIO[1]
-set_location_assignment PIN_AP30 -to TESTIO[2]
-set_location_assignment PIN_AP31 -to TESTIO[3]
-set_location_assignment PIN_AU30 -to TESTIO[4]
-set_location_assignment PIN_BD30 -to TESTIO[5]
-set_location_assignment PIN_AT30 -to TESTIO[6]
-set_location_assignment PIN_BD31 -to TESTIO[7]
-set_location_assignment PIN_AB12 -to VERSION[0]
-set_location_assignment PIN_AB13 -to VERSION[1]
-set_location_assignment PIN_BB30 -to WDI
-set_location_assignment PIN_N16 -to MB_SCL
-set_location_assignment PIN_P16 -to MB_SDA
-set_location_assignment PIN_N14 -to BCK_SCL[0]
-set_location_assignment PIN_P14 -to BCK_SCL[1]
-set_location_assignment PIN_R14 -to BCK_SCL[2]
-set_location_assignment PIN_R13 -to BCK_SDA[0]
-set_location_assignment PIN_P15 -to BCK_SDA[1]
-set_location_assignment PIN_T12 -to BCK_SDA[2]
-set_location_assignment PIN_AT31 -to QSFP_RST
-set_location_assignment PIN_AK33 -to QSFP_SCL[0]
-set_location_assignment PIN_AM33 -to QSFP_SCL[1]
-set_location_assignment PIN_AH32 -to QSFP_SCL[2]
-set_location_assignment PIN_AN31 -to QSFP_SCL[3]
-set_location_assignment PIN_AN33 -to QSFP_SCL[4]
-set_location_assignment PIN_AP33 -to QSFP_SCL[5]
-set_location_assignment PIN_AY30 -to QSFP_SDA[0]
-set_location_assignment PIN_AY32 -to QSFP_SDA[1]
-set_location_assignment PIN_AY33 -to QSFP_SDA[2]
-set_location_assignment PIN_AK32 -to QSFP_SDA[3]
-set_location_assignment PIN_BA31 -to QSFP_SDA[4]
-set_location_assignment PIN_BA32 -to QSFP_SDA[5]
-set_location_assignment PIN_K13 -to BCK_ERR[0]
-set_location_assignment PIN_L13 -to BCK_ERR[1]
-set_location_assignment PIN_M13 -to BCK_ERR[2]
-
-
-set_location_assignment PIN_H13 -to ETH_SGIN[0]
-set_location_assignment PIN_H12 -to "ETH_SGIN[0](n)"
-set_location_assignment PIN_AF33 -to ETH_SGIN[1]
-set_location_assignment PIN_AE33 -to "ETH_SGIN[1](n)"
-set_location_assignment PIN_K12 -to ETH_SGOUT[0]
-set_location_assignment PIN_J12 -to "ETH_SGOUT[0](n)"
-set_location_assignment PIN_AW31 -to ETH_SGOUT[1]
-set_location_assignment PIN_AV31 -to "ETH_SGOUT[1](n)"
-set_instance_assignment -name IO_STANDARD LVDS -to PPS
-set_instance_assignment -name IO_STANDARD LVDS -to "PPS(n)"
-set_instance_assignment -name IO_STANDARD LVDS -to CLK
-set_instance_assignment -name IO_STANDARD LVDS -to "CLK(n)"
-set_location_assignment PIN_AP40 -to RING_0_RX[0]
-set_location_assignment PIN_AR38 -to RING_0_RX[1]
-set_location_assignment PIN_AT40 -to RING_0_RX[2]
-set_location_assignment PIN_AU38 -to RING_0_RX[3]
-set_location_assignment PIN_AP44 -to RING_0_TX[0]
-set_location_assignment PIN_AR42 -to RING_0_TX[1]
-set_location_assignment PIN_AT44 -to RING_0_TX[2]
-set_location_assignment PIN_AU42 -to RING_0_TX[3]
-set_location_assignment PIN_J38 -to RING_1_RX[0]
-set_location_assignment PIN_H40 -to RING_1_RX[1]
-set_location_assignment PIN_G38 -to RING_1_RX[2]
-set_location_assignment PIN_F40 -to RING_1_RX[3]
-set_location_assignment PIN_J42 -to RING_1_TX[0]
-set_location_assignment PIN_H44 -to RING_1_TX[1]
-set_location_assignment PIN_F44 -to RING_1_TX[2]
-set_location_assignment PIN_G42 -to RING_1_TX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[3](n)"
-set_location_assignment PIN_C11 -to BCK_RX[0]
-set_location_assignment PIN_C12 -to "BCK_RX[0](n)"
-set_location_assignment PIN_E11 -to BCK_RX[1]
-set_location_assignment PIN_E12 -to "BCK_RX[1](n)"
-set_location_assignment PIN_D9 -to BCK_RX[2]
-set_location_assignment PIN_D10 -to "BCK_RX[2](n)"
-set_location_assignment PIN_C7 -to BCK_RX[3]
-set_location_assignment PIN_C8 -to "BCK_RX[3](n)"
-set_location_assignment PIN_D5 -to BCK_RX[4]
-set_location_assignment PIN_D6 -to "BCK_RX[4](n)"
-set_location_assignment PIN_F9 -to BCK_RX[5]
-set_location_assignment PIN_F10 -to "BCK_RX[5](n)"
-set_location_assignment PIN_E7 -to BCK_RX[6]
-set_location_assignment PIN_E8 -to "BCK_RX[6](n)"
-set_location_assignment PIN_B9 -to BCK_RX[7]
-set_location_assignment PIN_B10 -to "BCK_RX[7](n)"
-set_location_assignment PIN_F5 -to BCK_RX[8]
-set_location_assignment PIN_F6 -to "BCK_RX[8](n)"
-set_location_assignment PIN_G7 -to BCK_RX[9]
-set_location_assignment PIN_G8 -to "BCK_RX[9](n)"
-set_location_assignment PIN_H5 -to BCK_RX[10]
-set_location_assignment PIN_H6 -to "BCK_RX[10](n)"
-set_location_assignment PIN_J7 -to BCK_RX[11]
-set_location_assignment PIN_J8 -to "BCK_RX[11](n)"
-set_location_assignment PIN_K5 -to BCK_RX[12]
-set_location_assignment PIN_K6 -to "BCK_RX[12](n)"
-set_location_assignment PIN_L7 -to BCK_RX[13]
-set_location_assignment PIN_L8 -to "BCK_RX[13](n)"
-set_location_assignment PIN_M5 -to BCK_RX[14]
-set_location_assignment PIN_M6 -to "BCK_RX[14](n)"
-set_location_assignment PIN_N7 -to BCK_RX[15]
-set_location_assignment PIN_N8 -to "BCK_RX[15](n)"
-set_location_assignment PIN_P5 -to BCK_RX[16]
-set_location_assignment PIN_P6 -to "BCK_RX[16](n)"
-set_location_assignment PIN_R7 -to BCK_RX[17]
-set_location_assignment PIN_R8 -to "BCK_RX[17](n)"
-set_location_assignment PIN_T5 -to BCK_RX[18]
-set_location_assignment PIN_T6 -to "BCK_RX[18](n)"
-set_location_assignment PIN_U7 -to BCK_RX[19]
-set_location_assignment PIN_U8 -to "BCK_RX[19](n)"
-set_location_assignment PIN_V5 -to BCK_RX[20]
-set_location_assignment PIN_V6 -to "BCK_RX[20](n)"
-set_location_assignment PIN_W7 -to BCK_RX[21]
-set_location_assignment PIN_W8 -to "BCK_RX[21](n)"
-set_location_assignment PIN_Y5 -to BCK_RX[22]
-set_location_assignment PIN_Y6 -to "BCK_RX[22](n)"
-set_location_assignment PIN_AA7 -to BCK_RX[23]
-set_location_assignment PIN_AA8 -to "BCK_RX[23](n)"
-set_location_assignment PIN_AB5 -to BCK_RX[24]
-set_location_assignment PIN_AB6 -to "BCK_RX[24](n)"
-set_location_assignment PIN_AC7 -to BCK_RX[25]
-set_location_assignment PIN_AC8 -to "BCK_RX[25](n)"
-set_location_assignment PIN_AD5 -to BCK_RX[26]
-set_location_assignment PIN_AD6 -to "BCK_RX[26](n)"
-set_location_assignment PIN_AE7 -to BCK_RX[27]
-set_location_assignment PIN_AE8 -to "BCK_RX[27](n)"
-set_location_assignment PIN_AF5 -to BCK_RX[28]
-set_location_assignment PIN_AF6 -to "BCK_RX[28](n)"
-set_location_assignment PIN_AG7 -to BCK_RX[29]
-set_location_assignment PIN_AG8 -to "BCK_RX[29](n)"
-set_location_assignment PIN_AH5 -to BCK_RX[30]
-set_location_assignment PIN_AH6 -to "BCK_RX[30](n)"
-set_location_assignment PIN_AJ7 -to BCK_RX[31]
-set_location_assignment PIN_AJ8 -to "BCK_RX[31](n)"
-set_location_assignment PIN_AK5 -to BCK_RX[32]
-set_location_assignment PIN_AK6 -to "BCK_RX[32](n)"
-set_location_assignment PIN_AL7 -to BCK_RX[33]
-set_location_assignment PIN_AL8 -to "BCK_RX[33](n)"
-set_location_assignment PIN_AM5 -to BCK_RX[34]
-set_location_assignment PIN_AM6 -to "BCK_RX[34](n)"
-set_location_assignment PIN_AN7 -to BCK_RX[35]
-set_location_assignment PIN_AN8 -to "BCK_RX[35](n)"
-set_location_assignment PIN_AP5 -to BCK_RX[36]
-set_location_assignment PIN_AP6 -to "BCK_RX[36](n)"
-set_location_assignment PIN_AR7 -to BCK_RX[37]
-set_location_assignment PIN_AR8 -to "BCK_RX[37](n)"
-set_location_assignment PIN_AT5 -to BCK_RX[38]
-set_location_assignment PIN_AT6 -to "BCK_RX[38](n)"
-set_location_assignment PIN_AU7 -to BCK_RX[39]
-set_location_assignment PIN_AU8 -to "BCK_RX[39](n)"
-set_location_assignment PIN_AV5 -to BCK_RX[40]
-set_location_assignment PIN_AV6 -to "BCK_RX[40](n)"
-set_location_assignment PIN_AW7 -to BCK_RX[41]
-set_location_assignment PIN_AW8 -to "BCK_RX[41](n)"
-set_location_assignment PIN_AY5 -to BCK_RX[42]
-set_location_assignment PIN_AY6 -to "BCK_RX[42](n)"
-set_location_assignment PIN_AY9 -to BCK_RX[43]
-set_location_assignment PIN_AY10 -to "BCK_RX[43](n)"
-set_location_assignment PIN_BA7 -to BCK_RX[44]
-set_location_assignment PIN_BA8 -to "BCK_RX[44](n)"
-set_location_assignment PIN_BB5 -to BCK_RX[45]
-set_location_assignment PIN_BB6 -to "BCK_RX[45](n)"
-set_location_assignment PIN_BB9 -to BCK_RX[46]
-set_location_assignment PIN_BB10 -to "BCK_RX[46](n)"
-set_location_assignment PIN_BC7 -to BCK_RX[47]
-set_location_assignment PIN_BC8 -to "BCK_RX[47](n)"
-set_location_assignment PIN_A11 -to BCK_TX[0]
-set_location_assignment PIN_A7 -to BCK_TX[1]
-set_location_assignment PIN_A3 -to BCK_TX[2]
-set_location_assignment PIN_C3 -to BCK_TX[3]
-set_location_assignment PIN_E3 -to BCK_TX[4]
-set_location_assignment PIN_B1 -to BCK_TX[5]
-set_location_assignment PIN_D1 -to BCK_TX[6]
-set_location_assignment PIN_B5 -to BCK_TX[7]
-set_location_assignment PIN_G3 -to BCK_TX[8]
-set_location_assignment PIN_F1 -to BCK_TX[9]
-set_location_assignment PIN_H1 -to BCK_TX[10]
-set_location_assignment PIN_J3 -to BCK_TX[11]
-set_location_assignment PIN_K1 -to BCK_TX[12]
-set_location_assignment PIN_L3 -to BCK_TX[13]
-set_location_assignment PIN_M1 -to BCK_TX[14]
-set_location_assignment PIN_N3 -to BCK_TX[15]
-set_location_assignment PIN_P1 -to BCK_TX[16]
-set_location_assignment PIN_R3 -to BCK_TX[17]
-set_location_assignment PIN_T1 -to BCK_TX[18]
-set_location_assignment PIN_U3 -to BCK_TX[19]
-set_location_assignment PIN_V1 -to BCK_TX[20]
-set_location_assignment PIN_W3 -to BCK_TX[21]
-set_location_assignment PIN_Y1 -to BCK_TX[22]
-set_location_assignment PIN_AA3 -to BCK_TX[23]
-set_location_assignment PIN_AB1 -to BCK_TX[24]
-set_location_assignment PIN_AC3 -to BCK_TX[25]
-set_location_assignment PIN_AD1 -to BCK_TX[26]
-set_location_assignment PIN_AE3 -to BCK_TX[27]
-set_location_assignment PIN_AF1 -to BCK_TX[28]
-set_location_assignment PIN_AG3 -to BCK_TX[29]
-set_location_assignment PIN_AH1 -to BCK_TX[30]
-set_location_assignment PIN_AJ3 -to BCK_TX[31]
-set_location_assignment PIN_AK1 -to BCK_TX[32]
-set_location_assignment PIN_AL3 -to BCK_TX[33]
-set_location_assignment PIN_AM1 -to BCK_TX[34]
-set_location_assignment PIN_AN3 -to BCK_TX[35]
-set_location_assignment PIN_AP1 -to BCK_TX[36]
-set_location_assignment PIN_AR3 -to BCK_TX[37]
-set_location_assignment PIN_AT1 -to BCK_TX[38]
-set_location_assignment PIN_AU3 -to BCK_TX[39]
-set_location_assignment PIN_AV1 -to BCK_TX[40]
-set_location_assignment PIN_AW3 -to BCK_TX[41]
-set_location_assignment PIN_AY1 -to BCK_TX[42]
-set_location_assignment PIN_BC3 -to BCK_TX[43]
-set_location_assignment PIN_BB1 -to BCK_TX[44]
-set_location_assignment PIN_BA3 -to BCK_TX[45]
-set_location_assignment PIN_BD9 -to BCK_TX[46]
-set_location_assignment PIN_BD5 -to BCK_TX[47]
-set_location_assignment PIN_AV40 -to RING_0_RX[4]
-set_location_assignment PIN_AW38 -to RING_0_RX[5]
-set_location_assignment PIN_AY40 -to RING_0_RX[6]
-set_location_assignment PIN_AY36 -to RING_0_RX[7]
-set_location_assignment PIN_BA38 -to RING_0_RX[8]
-set_location_assignment PIN_BB40 -to RING_0_RX[9]
-set_location_assignment PIN_BB36 -to RING_0_RX[10]
-set_location_assignment PIN_BC38 -to RING_0_RX[11]
-set_location_assignment PIN_AV44 -to RING_0_TX[4]
-set_location_assignment PIN_AW42 -to RING_0_TX[5]
-set_location_assignment PIN_AY44 -to RING_0_TX[6]
-set_location_assignment PIN_BC42 -to RING_0_TX[7]
-set_location_assignment PIN_BB44 -to RING_0_TX[8]
-set_location_assignment PIN_BA42 -to RING_0_TX[9]
-set_location_assignment PIN_BD36 -to RING_0_TX[10]
-set_location_assignment PIN_BD40 -to RING_0_TX[11]
-set_location_assignment PIN_F36 -to RING_1_RX[4]
-set_location_assignment PIN_E38 -to RING_1_RX[5]
-set_location_assignment PIN_E34 -to RING_1_RX[6]
-set_location_assignment PIN_D40 -to RING_1_RX[7]
-set_location_assignment PIN_D36 -to RING_1_RX[8]
-set_location_assignment PIN_C38 -to RING_1_RX[9]
-set_location_assignment PIN_C34 -to RING_1_RX[10]
-set_location_assignment PIN_B36 -to RING_1_RX[11]
-set_location_assignment PIN_B44 -to RING_1_TX[4]
-set_location_assignment PIN_D44 -to RING_1_TX[5]
-set_location_assignment PIN_A38 -to RING_1_TX[6]
-set_location_assignment PIN_E42 -to RING_1_TX[7]
-set_location_assignment PIN_A42 -to RING_1_TX[8]
-set_location_assignment PIN_C42 -to RING_1_TX[9]
-set_location_assignment PIN_A34 -to RING_1_TX[10]
-set_location_assignment PIN_B40 -to RING_1_TX[11]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[4]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[4](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[5]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[5](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[6]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[6](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[7]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[7](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[8]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[8](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[9]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[9](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[10]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[10](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[11]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[11](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[12]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[12](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[13]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[13](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[14]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[14](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[15]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[15](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[16]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[16](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[17]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[17](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[18]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[18](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[19]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[19](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[20]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[20](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[21]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[21](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[22]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[22](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[23]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[23](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[24]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[24](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[25]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[25](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[26]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[26](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[27]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[27](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[28]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[28](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[29]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[29](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[30]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[30](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[31]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[31](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[32]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[32](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[33]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[33](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[34]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[34](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[35]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[35](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[36]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[36](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[37]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[37](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[38]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[38](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[39]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[39](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[40]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[40](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[41]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[41](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[42]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[42](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[43]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[43](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[44]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[44](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[45]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[45](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[46]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[46](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[47]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[47](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[0]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[0](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[1]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[1](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[2]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[2](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[3]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[3](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[4]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[4](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[5]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[5](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[6]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[6](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[7]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[7](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[8]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[8](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[9]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[9](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[10]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[10](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[11]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[11](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[12]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[12](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[13]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[13](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[14]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[14](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[15]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[15](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[16]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[16](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[17]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[17](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[18]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[18](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[19]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[19](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[20]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[20](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[21]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[21](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[22]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[22](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[23]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[23](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[24]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[24](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[25]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[25](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[26]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[26](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[27]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[27](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[28]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[28](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[29]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[29](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[30]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[30](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[31]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[31](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[32]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[32](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[33]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[33](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[34]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[34](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[35]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[35](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[36]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[36](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[37]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[37](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[38]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[38](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[39]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[39](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[40]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[40](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[41]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[41](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[42]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[42](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[43]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[43](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[44]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[44](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[45]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[45](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[46]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[46](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_TX[47]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_TX[47](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[4]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[4](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[5]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[5](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[6]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[6](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[7]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[7](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[8]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[8](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[9]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[9](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[10]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[10](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_RX[11]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_RX[11](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[4]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[4](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[5]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[5](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[6]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[6](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[7]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[7](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[8]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[8](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[9]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[9](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[10]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[10](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_0_TX[11]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_0_TX[11](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[4]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[4](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[5]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[5](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[6]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[6](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[7]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[7](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[8]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[8](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[9]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[9](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[10]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[10](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_RX[11]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_RX[11](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[4]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[4](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[5]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[5](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[6]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[6](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[7]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[7](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[8]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[8](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[9]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[9](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[10]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[10](n)"
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to RING_1_TX[11]
-set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RING_1_TX[11](n)"
-set_location_assignment PIN_V9 -to BCK_REF_CLK
-set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
-set_location_assignment PIN_AL32 -to CLKUSR
-
-
-
-
-set_global_assignment -name DEVICE 10AX115U3F45I2LG
-#set_global_assignment -name DEVICE 10AX115U4F45I3SG
-
-
-
-
-
-
-
-
-
-
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_A[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_A[1]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_A[2]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_A[3]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_A[4]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_A[5]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_A[6]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_A[7]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_A[8]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_A[9]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_A[10]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_A[11]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_A[12]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_A[13]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_ACT_N[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_BA[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_BA[1]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_BG[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_BG[1]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_CAS_A15
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_I_CK[0]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_I_CK[1]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_I_CK_n[0]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_I_CK_n[1]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_CKE[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_CKE[1]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_CS[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_CS[1]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_ODT[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_ODT[1]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_PARITY[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_RAS_A16
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_WE_A14
-set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_RESET_N[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_A[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_A[1]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_A[2]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_A[3]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_A[4]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_A[5]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_A[6]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_A[7]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_A[8]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_A[9]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_A[10]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_A[11]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_A[12]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_A[13]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_ACT_N[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_BA[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_BA[1]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_BG[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_BG[1]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_CAS_A15
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_II_CK[0]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_II_CK[1]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_II_CK_n[0]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_II_CK_n[1]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_CKE[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_CKE[1]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_CS[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_CS[1]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_ODT[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_ODT[1]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_PARITY[0]
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_RAS_A16
-set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_WE_A14
-set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_II_RESET_N[0]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_CB[0]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_CB[1]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_CB[2]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_CB[3]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_CB[4]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_CB[5]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_CB[6]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_CB[7]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DM[0]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DM[1]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DM[2]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DM[3]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DM[4]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DM[5]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DM[6]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DM[7]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DM[8]
-set_location_assignment PIN_AU29 -to MB_I_DQ[0]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[0]
-set_location_assignment PIN_BC28 -to MB_I_DQ[1]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[1]
-set_location_assignment PIN_AY29 -to MB_I_DQ[2]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[2]
-set_location_assignment PIN_BB28 -to MB_I_DQ[3]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[3]
-set_location_assignment PIN_BB29 -to MB_I_DQ[4]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[4]
-set_location_assignment PIN_AW29 -to MB_I_DQ[5]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[5]
-set_location_assignment PIN_BC27 -to MB_I_DQ[6]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[6]
-set_location_assignment PIN_BD29 -to MB_I_DQ[7]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[7]
-set_location_assignment PIN_AR28 -to MB_I_DQ[8]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[8]
-set_location_assignment PIN_AR29 -to MB_I_DQ[9]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[9]
-set_location_assignment PIN_AV27 -to MB_I_DQ[10]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[10]
-set_location_assignment PIN_AU28 -to MB_I_DQ[11]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[11]
-set_location_assignment PIN_AW27 -to MB_I_DQ[12]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[12]
-set_location_assignment PIN_AT28 -to MB_I_DQ[13]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[13]
-set_location_assignment PIN_AV28 -to MB_I_DQ[14]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[14]
-set_location_assignment PIN_AP27 -to MB_I_DQ[15]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[15]
-set_location_assignment PIN_BC24 -to MB_I_DQ[16]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[16]
-set_location_assignment PIN_BB24 -to MB_I_DQ[17]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[17]
-set_location_assignment PIN_BB23 -to MB_I_DQ[18]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[18]
-set_location_assignment PIN_AW22 -to MB_I_DQ[19]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[19]
-set_location_assignment PIN_BA23 -to MB_I_DQ[20]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[20]
-set_location_assignment PIN_BC23 -to MB_I_DQ[21]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[21]
-set_location_assignment PIN_AY23 -to MB_I_DQ[22]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[22]
-set_location_assignment PIN_AY24 -to MB_I_DQ[23]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[23]
-set_location_assignment PIN_AP22 -to MB_I_DQ[24]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[24]
-set_location_assignment PIN_AN23 -to MB_I_DQ[25]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[25]
-set_location_assignment PIN_AR23 -to MB_I_DQ[26]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[26]
-set_location_assignment PIN_AT23 -to MB_I_DQ[27]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[27]
-set_location_assignment PIN_AU23 -to MB_I_DQ[28]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[28]
-set_location_assignment PIN_AV23 -to MB_I_DQ[29]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[29]
-set_location_assignment PIN_AR24 -to MB_I_DQ[30]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[30]
-set_location_assignment PIN_AP24 -to MB_I_DQ[31]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[31]
-set_location_assignment PIN_AV12 -to MB_I_DQ[32]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[32]
-set_location_assignment PIN_AY13 -to MB_I_DQ[33]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[33]
-set_location_assignment PIN_BD14 -to MB_I_DQ[34]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[34]
-set_location_assignment PIN_AY12 -to MB_I_DQ[35]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[35]
-set_location_assignment PIN_BA13 -to MB_I_DQ[36]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[36]
-set_location_assignment PIN_BA12 -to MB_I_DQ[37]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[37]
-set_location_assignment PIN_AW12 -to MB_I_DQ[38]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[38]
-set_location_assignment PIN_BB13 -to MB_I_DQ[39]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[39]
-set_location_assignment PIN_AV13 -to MB_I_DQ[40]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[40]
-set_location_assignment PIN_AR13 -to MB_I_DQ[41]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[41]
-set_location_assignment PIN_AR15 -to MB_I_DQ[42]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[42]
-set_location_assignment PIN_AP15 -to MB_I_DQ[43]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[43]
-set_location_assignment PIN_AT15 -to MB_I_DQ[44]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[44]
-set_location_assignment PIN_AU14 -to MB_I_DQ[45]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[45]
-set_location_assignment PIN_AU15 -to MB_I_DQ[46]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[46]
-set_location_assignment PIN_AV14 -to MB_I_DQ[47]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[47]
-set_location_assignment PIN_AM13 -to MB_I_DQ[48]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[48]
-set_location_assignment PIN_AT13 -to MB_I_DQ[49]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[49]
-set_location_assignment PIN_AT12 -to MB_I_DQ[50]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[50]
-set_location_assignment PIN_AP14 -to MB_I_DQ[51]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[51]
-set_location_assignment PIN_AN13 -to MB_I_DQ[52]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[52]
-set_location_assignment PIN_AK13 -to MB_I_DQ[53]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[53]
-set_location_assignment PIN_AM12 -to MB_I_DQ[54]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[54]
-set_location_assignment PIN_AL13 -to MB_I_DQ[55]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[55]
-set_location_assignment PIN_AH13 -to MB_I_DQ[56]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[56]
-set_location_assignment PIN_AL15 -to MB_I_DQ[57]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[57]
-set_location_assignment PIN_AM15 -to MB_I_DQ[58]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[58]
-set_location_assignment PIN_AJ14 -to MB_I_DQ[59]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[59]
-set_location_assignment PIN_AJ12 -to MB_I_DQ[60]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[60]
-set_location_assignment PIN_AL16 -to MB_I_DQ[61]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[61]
-set_location_assignment PIN_AK12 -to MB_I_DQ[62]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[62]
-set_location_assignment PIN_AH14 -to MB_I_DQ[63]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_DQ[63]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS[0]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS[1]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS[2]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS[3]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS[4]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS[5]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS[6]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS[7]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS[8]
-set_location_assignment PIN_AY28 -to MB_I_DQS_n[0]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS_n[0]
-set_location_assignment PIN_AN28 -to MB_I_DQS_n[1]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS_n[1]
-set_location_assignment PIN_AU24 -to MB_I_DQS_n[2]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS_n[2]
-set_location_assignment PIN_AM24 -to MB_I_DQS_n[3]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS_n[3]
-set_location_assignment PIN_BB14 -to MB_I_DQS_n[4]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS_n[4]
-set_location_assignment PIN_AY14 -to MB_I_DQS_n[5]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS_n[5]
-set_location_assignment PIN_AP12 -to MB_I_DQS_n[6]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS_n[6]
-set_location_assignment PIN_AK14 -to MB_I_DQS_n[7]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS_n[7]
-set_location_assignment PIN_BD22 -to MB_I_DQS_n[8]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_DQS_n[8]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_SCL
-set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_SDA
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_CB[0]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_CB[1]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_CB[2]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_CB[3]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_CB[4]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_CB[5]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_CB[6]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_CB[7]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DM[0]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DM[1]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DM[2]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DM[3]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DM[4]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DM[5]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DM[6]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DM[7]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DM[8]
-set_location_assignment PIN_A17 -to MB_II_DQ[0]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[0]
-set_location_assignment PIN_B16 -to MB_II_DQ[1]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[1]
-set_location_assignment PIN_D16 -to MB_II_DQ[2]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[2]
-set_location_assignment PIN_A18 -to MB_II_DQ[3]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[3]
-set_location_assignment PIN_B18 -to MB_II_DQ[4]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[4]
-set_location_assignment PIN_C17 -to MB_II_DQ[5]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[5]
-set_location_assignment PIN_E18 -to MB_II_DQ[6]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[6]
-set_location_assignment PIN_F18 -to MB_II_DQ[7]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[7]
-set_location_assignment PIN_R22 -to MB_II_DQ[8]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[8]
-set_location_assignment PIN_J20 -to MB_II_DQ[9]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[9]
-set_location_assignment PIN_L21 -to MB_II_DQ[10]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[10]
-set_location_assignment PIN_M20 -to MB_II_DQ[11]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[11]
-set_location_assignment PIN_J21 -to MB_II_DQ[12]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[12]
-set_location_assignment PIN_P21 -to MB_II_DQ[13]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[13]
-set_location_assignment PIN_R20 -to MB_II_DQ[14]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[14]
-set_location_assignment PIN_N21 -to MB_II_DQ[15]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[15]
-set_location_assignment PIN_L22 -to MB_II_DQ[16]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[16]
-set_location_assignment PIN_G20 -to MB_II_DQ[17]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[17]
-set_location_assignment PIN_H21 -to MB_II_DQ[18]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[18]
-set_location_assignment PIN_N22 -to MB_II_DQ[19]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[19]
-set_location_assignment PIN_P22 -to MB_II_DQ[20]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[20]
-set_location_assignment PIN_F20 -to MB_II_DQ[21]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[21]
-set_location_assignment PIN_G21 -to MB_II_DQ[22]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[22]
-set_location_assignment PIN_F21 -to MB_II_DQ[23]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[23]
-set_location_assignment PIN_E19 -to MB_II_DQ[24]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[24]
-set_location_assignment PIN_B20 -to MB_II_DQ[25]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[25]
-set_location_assignment PIN_A20 -to MB_II_DQ[26]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[26]
-set_location_assignment PIN_G19 -to MB_II_DQ[27]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[27]
-set_location_assignment PIN_D20 -to MB_II_DQ[28]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[28]
-set_location_assignment PIN_E20 -to MB_II_DQ[29]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[29]
-set_location_assignment PIN_D17 -to MB_II_DQ[30]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[30]
-set_location_assignment PIN_C18 -to MB_II_DQ[31]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[31]
-set_location_assignment PIN_F30 -to MB_II_DQ[32]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[32]
-set_location_assignment PIN_L30 -to MB_II_DQ[33]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[33]
-set_location_assignment PIN_M30 -to MB_II_DQ[34]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[34]
-set_location_assignment PIN_C31 -to MB_II_DQ[35]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[35]
-set_location_assignment PIN_D31 -to MB_II_DQ[36]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[36]
-set_location_assignment PIN_H31 -to MB_II_DQ[37]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[37]
-set_location_assignment PIN_J31 -to MB_II_DQ[38]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[38]
-set_location_assignment PIN_F31 -to MB_II_DQ[39]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[39]
-set_location_assignment PIN_P32 -to MB_II_DQ[40]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[40]
-set_location_assignment PIN_R30 -to MB_II_DQ[41]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[41]
-set_location_assignment PIN_U31 -to MB_II_DQ[42]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[42]
-set_location_assignment PIN_W31 -to MB_II_DQ[43]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[43]
-set_location_assignment PIN_P29 -to MB_II_DQ[44]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[44]
-set_location_assignment PIN_P30 -to MB_II_DQ[45]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[45]
-set_location_assignment PIN_V31 -to MB_II_DQ[46]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[46]
-set_location_assignment PIN_R29 -to MB_II_DQ[47]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[47]
-set_location_assignment PIN_M33 -to MB_II_DQ[48]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[48]
-set_location_assignment PIN_J33 -to MB_II_DQ[49]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[49]
-set_location_assignment PIN_H33 -to MB_II_DQ[50]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[50]
-set_location_assignment PIN_H32 -to MB_II_DQ[51]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[51]
-set_location_assignment PIN_J32 -to MB_II_DQ[52]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[52]
-set_location_assignment PIN_K33 -to MB_II_DQ[53]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[53]
-set_location_assignment PIN_K32 -to MB_II_DQ[54]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[54]
-set_location_assignment PIN_L32 -to MB_II_DQ[55]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[55]
-set_location_assignment PIN_AB33 -to MB_II_DQ[56]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[56]
-set_location_assignment PIN_AA32 -to MB_II_DQ[57]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[57]
-set_location_assignment PIN_W32 -to MB_II_DQ[58]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[58]
-set_location_assignment PIN_U33 -to MB_II_DQ[59]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[59]
-set_location_assignment PIN_Y33 -to MB_II_DQ[60]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[60]
-set_location_assignment PIN_AA33 -to MB_II_DQ[61]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[61]
-set_location_assignment PIN_V33 -to MB_II_DQ[62]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[62]
-set_location_assignment PIN_Y32 -to MB_II_DQ[63]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_DQ[63]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS[0]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS[1]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS[2]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS[3]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS[4]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS[5]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS[6]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS[7]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS[8]
-set_location_assignment PIN_E17 -to MB_II_DQS_n[0]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS_n[0]
-set_location_assignment PIN_K20 -to MB_II_DQS_n[1]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS_n[1]
-set_location_assignment PIN_H22 -to MB_II_DQS_n[2]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS_n[2]
-set_location_assignment PIN_C19 -to MB_II_DQS_n[3]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS_n[3]
-set_location_assignment PIN_M31 -to MB_II_DQS_n[4]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS_n[4]
-set_location_assignment PIN_N31 -to MB_II_DQS_n[5]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS_n[5]
-set_location_assignment PIN_P33 -to MB_II_DQS_n[6]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS_n[6]
-set_location_assignment PIN_T32 -to MB_II_DQS_n[7]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS_n[7]
-set_location_assignment PIN_B25 -to MB_II_DQS_n[8]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_DQS_n[8]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[5]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[5]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[2]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[2]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[2]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[3]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[4]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[2]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[3]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[4]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST
-set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[2]
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_ALERT_N[0]
-set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_RZQ
-set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_ALERT_N[0]
-set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_II_RZQ
-set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_REF_CLK
-set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_II_REF_CLK
-set_location_assignment PIN_AG31 -to altera_reserved_tms
-set_location_assignment PIN_AJ31 -to altera_reserved_tck
-set_location_assignment PIN_AK18 -to altera_reserved_tdi
-set_location_assignment PIN_AH31 -to altera_reserved_ntrst
-set_location_assignment PIN_AM29 -to altera_reserved_tdo
-set_location_assignment PIN_AV33 -to ~ALTERA_DATA0~
-set_location_assignment PIN_A12 -to "BCK_TX[0](n)"
-set_location_assignment PIN_A8 -to "BCK_TX[1](n)"
-set_location_assignment PIN_A4 -to "BCK_TX[2](n)"
-set_location_assignment PIN_C4 -to "BCK_TX[3](n)"
-set_location_assignment PIN_E4 -to "BCK_TX[4](n)"
-set_location_assignment PIN_B2 -to "BCK_TX[5](n)"
-set_location_assignment PIN_D2 -to "BCK_TX[6](n)"
-set_location_assignment PIN_B6 -to "BCK_TX[7](n)"
-set_location_assignment PIN_G4 -to "BCK_TX[8](n)"
-set_location_assignment PIN_F2 -to "BCK_TX[9](n)"
-set_location_assignment PIN_H2 -to "BCK_TX[10](n)"
-set_location_assignment PIN_J4 -to "BCK_TX[11](n)"
-set_location_assignment PIN_K2 -to "BCK_TX[12](n)"
-set_location_assignment PIN_L4 -to "BCK_TX[13](n)"
-set_location_assignment PIN_M2 -to "BCK_TX[14](n)"
-set_location_assignment PIN_N4 -to "BCK_TX[15](n)"
-set_location_assignment PIN_P2 -to "BCK_TX[16](n)"
-set_location_assignment PIN_R4 -to "BCK_TX[17](n)"
-set_location_assignment PIN_T2 -to "BCK_TX[18](n)"
-set_location_assignment PIN_U4 -to "BCK_TX[19](n)"
-set_location_assignment PIN_V2 -to "BCK_TX[20](n)"
-set_location_assignment PIN_W4 -to "BCK_TX[21](n)"
-set_location_assignment PIN_Y2 -to "BCK_TX[22](n)"
-set_location_assignment PIN_AA4 -to "BCK_TX[23](n)"
-set_location_assignment PIN_AB2 -to "BCK_TX[24](n)"
-set_location_assignment PIN_AC4 -to "BCK_TX[25](n)"
-set_location_assignment PIN_AD2 -to "BCK_TX[26](n)"
-set_location_assignment PIN_AE4 -to "BCK_TX[27](n)"
-set_location_assignment PIN_AF2 -to "BCK_TX[28](n)"
-set_location_assignment PIN_AG4 -to "BCK_TX[29](n)"
-set_location_assignment PIN_AH2 -to "BCK_TX[30](n)"
-set_location_assignment PIN_AJ4 -to "BCK_TX[31](n)"
-set_location_assignment PIN_AK2 -to "BCK_TX[32](n)"
-set_location_assignment PIN_AL4 -to "BCK_TX[33](n)"
-set_location_assignment PIN_AM2 -to "BCK_TX[34](n)"
-set_location_assignment PIN_AN4 -to "BCK_TX[35](n)"
-set_location_assignment PIN_AP2 -to "BCK_TX[36](n)"
-set_location_assignment PIN_AR4 -to "BCK_TX[37](n)"
-set_location_assignment PIN_AT2 -to "BCK_TX[38](n)"
-set_location_assignment PIN_AU4 -to "BCK_TX[39](n)"
-set_location_assignment PIN_AV2 -to "BCK_TX[40](n)"
-set_location_assignment PIN_AW4 -to "BCK_TX[41](n)"
-set_location_assignment PIN_AY2 -to "BCK_TX[42](n)"
-set_location_assignment PIN_BC4 -to "BCK_TX[43](n)"
-set_location_assignment PIN_BB2 -to "BCK_TX[44](n)"
-set_location_assignment PIN_BA4 -to "BCK_TX[45](n)"
-set_location_assignment PIN_BD10 -to "BCK_TX[46](n)"
-set_location_assignment PIN_BD6 -to "BCK_TX[47](n)"
-set_location_assignment PIN_AY43 -to "RING_0_TX[6](n)"
-set_location_assignment PIN_BC41 -to "RING_0_TX[7](n)"
-set_location_assignment PIN_BB43 -to "RING_0_TX[8](n)"
-set_location_assignment PIN_BA41 -to "RING_0_TX[9](n)"
-set_location_assignment PIN_BD35 -to "RING_0_TX[10](n)"
-set_location_assignment PIN_BD39 -to "RING_0_TX[11](n)"
-set_location_assignment PIN_AP43 -to "RING_0_TX[0](n)"
-set_location_assignment PIN_AR41 -to "RING_0_TX[1](n)"
-set_location_assignment PIN_AT43 -to "RING_0_TX[2](n)"
-set_location_assignment PIN_AU41 -to "RING_0_TX[3](n)"
-set_location_assignment PIN_AV43 -to "RING_0_TX[4](n)"
-set_location_assignment PIN_AW41 -to "RING_0_TX[5](n)"
-set_location_assignment PIN_C41 -to "RING_1_TX[9](n)"
-set_location_assignment PIN_A33 -to "RING_1_TX[10](n)"
-set_location_assignment PIN_B39 -to "RING_1_TX[11](n)"
-set_location_assignment PIN_H43 -to "RING_1_TX[1](n)"
-set_location_assignment PIN_F43 -to "RING_1_TX[2](n)"
-set_location_assignment PIN_G41 -to "RING_1_TX[3](n)"
-set_location_assignment PIN_B43 -to "RING_1_TX[4](n)"
-set_location_assignment PIN_D43 -to "RING_1_TX[5](n)"
-set_location_assignment PIN_A37 -to "RING_1_TX[6](n)"
-set_location_assignment PIN_E41 -to "RING_1_TX[7](n)"
-set_location_assignment PIN_A41 -to "RING_1_TX[8](n)"
-set_location_assignment PIN_J41 -to "RING_1_TX[0](n)"
-set_location_assignment PIN_AY39 -to "RING_0_RX[6](n)"
-set_location_assignment PIN_AY35 -to "RING_0_RX[7](n)"
-set_location_assignment PIN_BA37 -to "RING_0_RX[8](n)"
-set_location_assignment PIN_BB39 -to "RING_0_RX[9](n)"
-set_location_assignment PIN_BB35 -to "RING_0_RX[10](n)"
-set_location_assignment PIN_BC37 -to "RING_0_RX[11](n)"
-set_location_assignment PIN_AP39 -to "RING_0_RX[0](n)"
-set_location_assignment PIN_AR37 -to "RING_0_RX[1](n)"
-set_location_assignment PIN_AT39 -to "RING_0_RX[2](n)"
-set_location_assignment PIN_AU37 -to "RING_0_RX[3](n)"
-set_location_assignment PIN_AV39 -to "RING_0_RX[4](n)"
-set_location_assignment PIN_AW37 -to "RING_0_RX[5](n)"
-set_location_assignment PIN_C37 -to "RING_1_RX[9](n)"
-set_location_assignment PIN_C33 -to "RING_1_RX[10](n)"
-set_location_assignment PIN_B35 -to "RING_1_RX[11](n)"
-set_location_assignment PIN_H39 -to "RING_1_RX[1](n)"
-set_location_assignment PIN_G37 -to "RING_1_RX[2](n)"
-set_location_assignment PIN_F39 -to "RING_1_RX[3](n)"
-set_location_assignment PIN_F35 -to "RING_1_RX[4](n)"
-set_location_assignment PIN_E37 -to "RING_1_RX[5](n)"
-set_location_assignment PIN_E33 -to "RING_1_RX[6](n)"
-set_location_assignment PIN_D39 -to "RING_1_RX[7](n)"
-set_location_assignment PIN_D35 -to "RING_1_RX[8](n)"
-set_location_assignment PIN_J37 -to "RING_1_RX[0](n)"
-
-
-set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932
-
-
-set_global_assignment -name VHDL_FILE ../../../../../../libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
-set_global_assignment -name QSYS_FILE ../../../../../../libraries/technology/ip_arria10/transceiver_pll/transceiver_pll.qsys
-set_global_assignment -name QSYS_FILE ../../../../../../libraries/technology/ip_arria10/transceiver_reset_controller_48/transceiver_reset_controller_48.qsys
-set_global_assignment -name QSYS_FILE ../../../../../../libraries/technology/ip_arria10/transceiver_phy_48/transceiver_phy_48.qsys
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_mem_mux.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/MegaWizard/fifo_sc/fifo_sc.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_fifo_sc_a_stratix4.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/MegaWizard/mem/ram_crwk_crw.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_crw_crw_ratio_a_stratix4.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_crw_crw_ratio.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_cr_cw_ratio_a_str.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/MegaWizard/fifo_dc/fifo_dc.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_fifo_dc_a_stratix4.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_xonoff.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_pipeline.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_shiftreg.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_tail_remove.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_ram_to_mm.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_hdr_remove.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_frame_remove.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_pad_insert.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_nonbonded/tb/vhdl/deserializer.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_nonbonded/tb/vhdl/serializer.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_fifo_sc.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_fifo_sc.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_fifo_fill.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_ready.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_split.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_pad_remove.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_hold_ctrl.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_hold_input.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_concat.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_ram_from_mm_reg.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_cr_cw_ratio.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_ram_from_mm.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/mms_dp_ram_from_mm.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_hdr_insert.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_fifo_dc.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_fifo_dc.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../libraries/technology/transceiver/tech_transceiver_arria10_48.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_spulse.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_reg_cross_domain.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/Lofar/diag/src/vhdl/diag_pkg.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/diagnostics/src/vhdl/diagnostics_reg.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_mon.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/Lofar/diag/src/vhdl/diag_rx_seq.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/Lofar/diag/src/vhdl/diag_tx_seq.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_block_gen.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_latency_increase.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_latency_adapter.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/diagnostics/src/vhdl/diagnostics.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_lfsr_sequences_pkg.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/diagnostics/src/vhdl/mms_diagnostics.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/tr_xaui/src/vhdl/tr_xaui_pkg.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../libraries/technology/technology_select_pkg.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../libraries/technology/technology_pkg.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/MegaWizard/mem/ram_cr_cw.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/MegaWizard/mem/ram_crw_crw.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_crw_crw_a_stratix4.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_crw_crw.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_rw_rw_a_str.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_evt.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_pulser.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_async.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_areset.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_counter.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_pulse_extend.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_rw_rw.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_pipeline.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_reg_r_w.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_switch.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_request.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_mem_pkg.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_pkg.vhd
-set_global_assignment -name SIP_FILE ../../src/ip/system_pll.sip
-set_global_assignment -name QSYS_FILE ../../src/ip/system_pll.qsys
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/designs/unb_common/src/vhdl/unb_common_pkg.vhd
-set_global_assignment -name QSYS_FILE unb2_test_qsys.qsys
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_stream_pkg.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/designs/unb_common/src/vhdl/unb_node_ctrl.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/designs/unb_common/src/vhdl/unb_clk_rst.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/designs/unb_common/src/vhdl/unb_pulser.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/designs/unb_common/src/vhdl/unb_system_info.vhd
-set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/designs/unb_common/src/vhdl/unb_wdi_extend.vhd
-set_global_assignment -name QSYS_FILE ../../src/ip/ddr4.qsys
-set_global_assignment -name SIP_FILE ../../src/ip/ddr4.sip
-set_global_assignment -name VHDL_FILE ../../src/vhdl/unb2_test.vhd
-set_global_assignment -name SOURCE_FILE db/unb2_test.cmp.rdb
-set_global_assignment -name QSYS_FILE ../../../../../../libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g.qsys
-set_global_assignment -name SDC_FILE ../../src/sdc/unb2_test.sdc
-set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "IBIS (Signal Integrity)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT IBIS -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_IBIS_MODEL_SELECTOR ON -section_id eda_board_design_signal_integrity
-
-set_instance_assignment -name DONT_MERGE_REGISTER ON -to *u_transceiver|tx_pma_clkout*
-set_instance_assignment -name DONT_MERGE_REGISTER ON -to *u_transceiver|tx_pma_div_clkout*
-set_instance_assignment -name DONT_MERGE_REGISTER ON -to *u_transceiver|rx_pma_clkout*
-set_instance_assignment -name DONT_MERGE_REGISTER ON -to *u_transceiver|rx_pma_div_clkout*
-
-
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_test/build/quartus/unb2_test_qsys.qsys b/boards/uniboard2/designs/unb2_test/build/quartus/unb2_test_qsys.qsys
deleted file mode 100644
index 9ba6cde3dba322604093624b904cbe6197bbe248..0000000000000000000000000000000000000000
--- a/boards/uniboard2/designs/unb2_test/build/quartus/unb2_test_qsys.qsys
+++ /dev/null
@@ -1,2894 +0,0 @@
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-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
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-   description=""
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-{
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-   element avs_i2c_master_0
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-   element eth_tse_0.control_port
-   {
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-   element eth_tse_1.control_port
-   {
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-      datum sopceditor_expanded
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-   {
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-   element ram_hdr_remove_front.mem
-   {
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-      {
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-         type = "String";
-      }
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-   element nios2_qsys_0
-   {
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-         type = "int";
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-   element onchip_memory2_0
-   {
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-      }
-   }
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-   {
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-      {
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-   element avs_i2c_master_8.protocol
-   {
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-         type = "String";
-      }
-   }
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-   element avs_i2c_master_10.result
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-   element avs_i2c_master_5.result
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-   element avs_i2c_master_0.result
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-   element onchip_memory2_0.s1
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-         value = "294912";
-         type = "String";
-      }
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-   element avs_i2c_master_0.system_reset
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-         type = "String";
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-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="unb2_test.qpf" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
- <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
- <interface
-   name="avs_i2c_master_0_gs_sim"
-   internal="avs_i2c_master_0.gs_sim"
-   type="conduit"
-   dir="end" />
- <interface
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-   type="conduit"
-   dir="end" />
- <interface
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-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_0_i2c_sda"
-   internal="avs_i2c_master_0.i2c_sda"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_1_gs_sim"
-   internal="avs_i2c_master_1.gs_sim"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_1_sync"
-   internal="avs_i2c_master_1.sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_1_i2c_scl"
-   internal="avs_i2c_master_1.i2c_scl"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_1_i2c_sda"
-   internal="avs_i2c_master_1.i2c_sda"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_10_i2c_sda"
-   internal="avs_i2c_master_10.i2c_sda"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_10_i2c_scl"
-   internal="avs_i2c_master_10.i2c_scl"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_10_sync"
-   internal="avs_i2c_master_10.sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_10_gs_sim"
-   internal="avs_i2c_master_10.gs_sim"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_9_i2c_sda"
-   internal="avs_i2c_master_9.i2c_sda"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_9_i2c_scl"
-   internal="avs_i2c_master_9.i2c_scl"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_9_sync"
-   internal="avs_i2c_master_9.sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_9_gs_sim"
-   internal="avs_i2c_master_9.gs_sim"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_8_i2c_sda"
-   internal="avs_i2c_master_8.i2c_sda"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_8_sync"
-   internal="avs_i2c_master_8.sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_8_gs_sim"
-   internal="avs_i2c_master_8.gs_sim"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_8_i2c_scl"
-   internal="avs_i2c_master_8.i2c_scl"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_7_i2c_sda"
-   internal="avs_i2c_master_7.i2c_sda"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_7_i2c_scl"
-   internal="avs_i2c_master_7.i2c_scl"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_7_sync"
-   internal="avs_i2c_master_7.sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_7_gs_sim"
-   internal="avs_i2c_master_7.gs_sim"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_6_i2c_sda"
-   internal="avs_i2c_master_6.i2c_sda"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_6_i2c_scl"
-   internal="avs_i2c_master_6.i2c_scl"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_6_sync"
-   internal="avs_i2c_master_6.sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_6_gs_sim"
-   internal="avs_i2c_master_6.gs_sim"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_5_i2c_sda"
-   internal="avs_i2c_master_5.i2c_sda"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_5_i2c_scl"
-   internal="avs_i2c_master_5.i2c_scl"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_5_sync"
-   internal="avs_i2c_master_5.sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_5_gs_sim"
-   internal="avs_i2c_master_5.gs_sim"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_4_i2c_sda"
-   internal="avs_i2c_master_4.i2c_sda"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_4_sync"
-   internal="avs_i2c_master_4.sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_4_gs_sim"
-   internal="avs_i2c_master_4.gs_sim"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_4_i2c_scl"
-   internal="avs_i2c_master_4.i2c_scl"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_3_gs_sim"
-   internal="avs_i2c_master_3.gs_sim"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_3_sync"
-   internal="avs_i2c_master_3.sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_3_i2c_scl"
-   internal="avs_i2c_master_3.i2c_scl"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_3_i2c_sda"
-   internal="avs_i2c_master_3.i2c_sda"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_2_gs_sim"
-   internal="avs_i2c_master_2.gs_sim"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_2_sync"
-   internal="avs_i2c_master_2.sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_2_i2c_scl"
-   internal="avs_i2c_master_2.i2c_scl"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_2_i2c_sda"
-   internal="avs_i2c_master_2.i2c_sda"
-   type="conduit"
-   dir="end" />
- <interface
-   name="eth_tse_0_serial_connection"
-   internal="eth_tse_0.serial_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="eth_tse_0_pcs_ref_clk_clock_connection"
-   internal="eth_tse_0.pcs_ref_clk_clock_connection"
-   type="clock"
-   dir="end" />
- <interface
-   name="eth_tse_1_pcs_ref_clk_clock_connection"
-   internal="eth_tse_1.pcs_ref_clk_clock_connection"
-   type="clock"
-   dir="end" />
- <interface
-   name="eth_tse_1_serial_connection"
-   internal="eth_tse_1.serial_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="pio_0_external_connection"
-   internal="pio_0.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_11_gs_sim"
-   internal="avs_i2c_master_11.gs_sim"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_11_sync"
-   internal="avs_i2c_master_11.sync"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_11_i2c_scl"
-   internal="avs_i2c_master_11.i2c_scl"
-   type="conduit"
-   dir="end" />
- <interface
-   name="avs_i2c_master_11_i2c_sda"
-   internal="avs_i2c_master_11.i2c_sda"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_mac_front_read"
-   internal="reg_mac_front.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_mac_front_address"
-   internal="reg_mac_front.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_mac_front_write"
-   internal="reg_mac_front.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_mac_front_writedata"
-   internal="reg_mac_front.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_mac_front_readdata"
-   internal="reg_mac_front.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_mac_front_waitrequest"
-   internal="reg_mac_front.waitrequest"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_mac_back_address"
-   internal="reg_mac_back.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_mac_back_write"
-   internal="reg_mac_back.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_mac_back_writedata"
-   internal="reg_mac_back.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_mac_back_read"
-   internal="reg_mac_back.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_mac_back_readdata"
-   internal="reg_mac_back.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_mac_back_waitrequest"
-   internal="reg_mac_back.waitrequest"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_hdr_insert_front_readdata"
-   internal="reg_hdr_insert_front.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_hdr_insert_front_read"
-   internal="reg_hdr_insert_front.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_hdr_insert_front_writedata"
-   internal="reg_hdr_insert_front.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_hdr_insert_front_address"
-   internal="reg_hdr_insert_front.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_hdr_insert_front_write"
-   internal="reg_hdr_insert_front.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_hdr_insert_back_readdata"
-   internal="reg_hdr_insert_back.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_hdr_insert_back_read"
-   internal="reg_hdr_insert_back.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_hdr_insert_back_writedata"
-   internal="reg_hdr_insert_back.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_hdr_insert_back_write"
-   internal="reg_hdr_insert_back.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_hdr_insert_back_address"
-   internal="reg_hdr_insert_back.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_insert_front_readdata"
-   internal="ram_hdr_insert_front.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_insert_front_read"
-   internal="ram_hdr_insert_front.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_insert_front_writedata"
-   internal="ram_hdr_insert_front.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_insert_front_write"
-   internal="ram_hdr_insert_front.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_insert_front_address"
-   internal="ram_hdr_insert_front.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_insert_back_address"
-   internal="ram_hdr_insert_back.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_insert_back_write"
-   internal="ram_hdr_insert_back.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_insert_back_writedata"
-   internal="ram_hdr_insert_back.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_insert_back_read"
-   internal="ram_hdr_insert_back.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_remove_front_readdata"
-   internal="ram_hdr_remove_front.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_remove_front_read"
-   internal="ram_hdr_remove_front.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_remove_front_writedata"
-   internal="ram_hdr_remove_front.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_remove_front_write"
-   internal="ram_hdr_remove_front.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_remove_front_address"
-   internal="ram_hdr_remove_front.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_remove_back_address"
-   internal="ram_hdr_remove_back.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_remove_back_write"
-   internal="ram_hdr_remove_back.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_remove_back_writedata"
-   internal="ram_hdr_remove_back.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_remove_back_read"
-   internal="ram_hdr_remove_back.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="ram_hdr_remove_back_readdata"
-   internal="ram_hdr_remove_back.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_0_address"
-   internal="reg_diagnostics_front_0.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_0_write"
-   internal="reg_diagnostics_front_0.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_0_writedata"
-   internal="reg_diagnostics_front_0.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_0_read"
-   internal="reg_diagnostics_front_0.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_0_readdata"
-   internal="reg_diagnostics_front_0.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_1_readdata"
-   internal="reg_diagnostics_front_1.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_1_read"
-   internal="reg_diagnostics_front_1.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_1_writedata"
-   internal="reg_diagnostics_front_1.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_1_write"
-   internal="reg_diagnostics_front_1.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_2_readdata"
-   internal="reg_diagnostics_front_2.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_2_read"
-   internal="reg_diagnostics_front_2.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_2_writedata"
-   internal="reg_diagnostics_front_2.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_2_write"
-   internal="reg_diagnostics_front_2.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_2_address"
-   internal="reg_diagnostics_front_2.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_0_readdata"
-   internal="reg_diagnostics_back_0.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_0_read"
-   internal="reg_diagnostics_back_0.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_0_writedata"
-   internal="reg_diagnostics_back_0.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_0_write"
-   internal="reg_diagnostics_back_0.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_0_address"
-   internal="reg_diagnostics_back_0.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_1_address"
-   internal="reg_diagnostics_back_1.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_1_write"
-   internal="reg_diagnostics_back_1.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_1_writedata"
-   internal="reg_diagnostics_back_1.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_1_read"
-   internal="reg_diagnostics_back_1.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_1_readdata"
-   internal="reg_diagnostics_back_1.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_2_address"
-   internal="reg_diagnostics_back_2.address"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_2_write"
-   internal="reg_diagnostics_back_2.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_2_writedata"
-   internal="reg_diagnostics_back_2.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_2_read"
-   internal="reg_diagnostics_back_2.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_back_2_readdata"
-   internal="reg_diagnostics_back_2.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_diagnostics_front_1_address"
-   internal="reg_diagnostics_front_1.address"
-   type="conduit"
-   dir="end" />
- <module kind="clock_source" version="14.0" enabled="1" name="clk_0">
-  <parameter name="clockFrequency" value="50000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="0" />
-  <parameter name="resetSynchronousEdges" value="NONE" />
- </module>
- <module
-   kind="altera_nios2_qsys"
-   version="14.0"
-   enabled="1"
-   name="nios2_qsys_0">
-  <parameter name="setting_showUnpublishedSettings" value="false" />
-  <parameter name="setting_showInternalSettings" value="false" />
-  <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
-  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
-  <parameter name="setting_preciseDivisionErrorException" value="false" />
-  <parameter name="setting_performanceCounter" value="false" />
-  <parameter name="setting_illegalMemAccessDetection" value="false" />
-  <parameter name="setting_illegalInstructionsTrap" value="false" />
-  <parameter name="setting_fullWaveformSignals" value="false" />
-  <parameter name="setting_extraExceptionInfo" value="false" />
-  <parameter name="setting_exportPCB" value="false" />
-  <parameter name="setting_debugSimGen" value="false" />
-  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
-  <parameter name="setting_bit31BypassDCache" value="true" />
-  <parameter name="setting_bigEndian" value="false" />
-  <parameter name="setting_export_large_RAMs" value="false" />
-  <parameter name="setting_asic_enabled" value="false" />
-  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
-  <parameter name="setting_oci_export_jtag_signals" value="false" />
-  <parameter name="setting_bhtIndexPcOnly" value="false" />
-  <parameter name="setting_avalonDebugPortPresent" value="false" />
-  <parameter name="setting_alwaysEncrypt" value="true" />
-  <parameter name="setting_allowFullAddressRange" value="false" />
-  <parameter name="setting_activateTrace" value="true" />
-  <parameter name="setting_activateTrace_user" value="false" />
-  <parameter name="setting_activateTestEndChecker" value="false" />
-  <parameter name="setting_ecc_sim_test_ports" value="false" />
-  <parameter name="setting_activateMonitors" value="true" />
-  <parameter name="setting_activateModelChecker" value="false" />
-  <parameter name="setting_HDLSimCachesCleared" value="true" />
-  <parameter name="setting_HBreakTest" value="false" />
-  <parameter name="setting_breakslaveoveride" value="false" />
-  <parameter name="muldiv_divider" value="false" />
-  <parameter name="mpu_useLimit" value="false" />
-  <parameter name="mpu_enabled" value="false" />
-  <parameter name="mmu_enabled" value="false" />
-  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
-  <parameter name="manuallyAssignCpuID" value="true" />
-  <parameter name="debug_triggerArming" value="true" />
-  <parameter name="debug_embeddedPLL" value="true" />
-  <parameter name="debug_debugReqSignals" value="false" />
-  <parameter name="debug_assignJtagInstanceID" value="false" />
-  <parameter name="dcache_omitDataMaster" value="false" />
-  <parameter name="cpuReset" value="false" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="setting_removeRAMinit" value="false" />
-  <parameter name="setting_shadowRegisterSets" value="0" />
-  <parameter name="mpu_numOfInstRegion" value="8" />
-  <parameter name="mpu_numOfDataRegion" value="8" />
-  <parameter name="mmu_TLBMissExcOffset" value="0" />
-  <parameter name="debug_jtagInstanceID" value="0" />
-  <parameter name="resetOffset" value="0" />
-  <parameter name="exceptionOffset" value="32" />
-  <parameter name="cpuID" value="0" />
-  <parameter name="cpuID_stored" value="0" />
-  <parameter name="breakOffset" value="32" />
-  <parameter name="userDefinedSettings" value="" />
-  <parameter name="resetSlave" value="Absolute" />
-  <parameter name="mmu_TLBMissExcSlave" value="None" />
-  <parameter name="exceptionSlave" value="Absolute" />
-  <parameter name="breakSlave">nios2_qsys_0.jtag_debug_module</parameter>
-  <parameter name="setting_perfCounterWidth" value="32" />
-  <parameter name="setting_interruptControllerType" value="Internal" />
-  <parameter name="setting_branchPredictionType" value="Automatic" />
-  <parameter name="setting_bhtPtrSz" value="8" />
-  <parameter name="muldiv_multiplierType" value="DSPBlock" />
-  <parameter name="mpu_minInstRegionSize" value="12" />
-  <parameter name="mpu_minDataRegionSize" value="12" />
-  <parameter name="mmu_uitlbNumEntries" value="4" />
-  <parameter name="mmu_udtlbNumEntries" value="6" />
-  <parameter name="mmu_tlbPtrSz" value="7" />
-  <parameter name="mmu_tlbNumWays" value="16" />
-  <parameter name="mmu_processIDNumBits" value="8" />
-  <parameter name="impl" value="Fast" />
-  <parameter name="icache_size" value="4096" />
-  <parameter name="icache_tagramBlockType" value="Automatic" />
-  <parameter name="icache_ramBlockType" value="Automatic" />
-  <parameter name="icache_numTCIM" value="0" />
-  <parameter name="icache_burstType" value="None" />
-  <parameter name="dcache_bursts" value="false" />
-  <parameter name="dcache_victim_buf_impl" value="ram" />
-  <parameter name="debug_level" value="Level1" />
-  <parameter name="debug_OCIOnchipTrace" value="_128" />
-  <parameter name="dcache_size" value="2048" />
-  <parameter name="dcache_tagramBlockType" value="Automatic" />
-  <parameter name="dcache_ramBlockType" value="Automatic" />
-  <parameter name="dcache_numTCDM" value="0" />
-  <parameter name="dcache_lineSize" value="32" />
-  <parameter name="setting_exportvectors" value="false" />
-  <parameter name="setting_ecc_present" value="false" />
-  <parameter name="setting_ic_ecc_present" value="true" />
-  <parameter name="setting_rf_ecc_present" value="true" />
-  <parameter name="setting_mmu_ecc_present" value="true" />
-  <parameter name="setting_dc_ecc_present" value="false" />
-  <parameter name="setting_itcm_ecc_present" value="false" />
-  <parameter name="setting_dtcm_ecc_present" value="false" />
-  <parameter name="regfile_ramBlockType" value="Automatic" />
-  <parameter name="ocimem_ramBlockType" value="Automatic" />
-  <parameter name="mmu_ramBlockType" value="Automatic" />
-  <parameter name="bht_ramBlockType" value="Automatic" />
-  <parameter name="instAddrWidth" value="19" />
-  <parameter name="dataAddrWidth" value="19" />
-  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
-  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
-  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
-  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x48000' end='0x50000' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x50800' end='0x51000' /></address-map>]]></parameter>
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='reg_mac_back.mem' start='0x0' end='0x20000' /><slave name='reg_mac_front.mem' start='0x20000' end='0x40000' /><slave name='onchip_memory2_0.s1' start='0x48000' end='0x50000' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x50800' end='0x51000' /><slave name='avs_i2c_master_11.result' start='0x51000' end='0x51400' /><slave name='avs_i2c_master_11.protocol' start='0x51400' end='0x51800' /><slave name='eth_tse_1.control_port' start='0x51800' end='0x51C00' /><slave name='eth_tse_0.control_port' start='0x51C00' end='0x52000' /><slave name='avs_i2c_master_10.result' start='0x52000' end='0x52400' /><slave name='avs_i2c_master_10.protocol' start='0x52400' end='0x52800' /><slave name='avs_i2c_master_9.result' start='0x52800' end='0x52C00' /><slave name='avs_i2c_master_9.protocol' start='0x52C00' end='0x53000' /><slave name='avs_i2c_master_8.result' start='0x53000' end='0x53400' /><slave name='avs_i2c_master_8.protocol' start='0x53400' end='0x53800' /><slave name='avs_i2c_master_7.result' start='0x53800' end='0x53C00' /><slave name='avs_i2c_master_7.protocol' start='0x53C00' end='0x54000' /><slave name='avs_i2c_master_6.result' start='0x54000' end='0x54400' /><slave name='avs_i2c_master_6.protocol' start='0x54400' end='0x54800' /><slave name='avs_i2c_master_5.result' start='0x54800' end='0x54C00' /><slave name='avs_i2c_master_5.protocol' start='0x54C00' end='0x55000' /><slave name='avs_i2c_master_4.result' start='0x55000' end='0x55400' /><slave name='avs_i2c_master_4.protocol' start='0x55400' end='0x55800' /><slave name='avs_i2c_master_3.result' start='0x55800' end='0x55C00' /><slave name='avs_i2c_master_3.protocol' start='0x55C00' end='0x56000' /><slave name='avs_i2c_master_2.result' start='0x56000' end='0x56400' /><slave name='avs_i2c_master_2.protocol' start='0x56400' end='0x56800' /><slave name='avs_i2c_master_1.result' start='0x56800' end='0x56C00' /><slave name='avs_i2c_master_1.protocol' start='0x56C00' end='0x57000' /><slave name='avs_i2c_master_0.result' start='0x57000' end='0x57400' /><slave name='avs_i2c_master_0.protocol' start='0x57400' end='0x57800' /><slave name='reg_diagnostics_back_2.mem' start='0x57800' end='0x57900' /><slave name='reg_diagnostics_back_1.mem' start='0x57900' end='0x57A00' /><slave name='reg_diagnostics_back_0.mem' start='0x57A00' end='0x57B00' /><slave name='reg_diagnostics_front_2.mem' start='0x57B00' end='0x57C00' /><slave name='reg_diagnostics_front_1.mem' start='0x57C00' end='0x57D00' /><slave name='reg_diagnostics_front_0.mem' start='0x57D00' end='0x57E00' /><slave name='ram_hdr_remove_back.mem' start='0x57E00' end='0x57F00' /><slave name='ram_hdr_remove_front.mem' start='0x57F00' end='0x58000' /><slave name='ram_hdr_insert_back.mem' start='0x58000' end='0x58100' /><slave name='ram_hdr_insert_front.mem' start='0x58100' end='0x58200' /><slave name='reg_hdr_insert_back.mem' start='0x58200' end='0x58220' /><slave name='reg_hdr_insert_front.mem' start='0x58220' end='0x58240' /><slave name='pio_0.s1' start='0x58240' end='0x58250' /><slave name='avs_i2c_master_11.control' start='0x58250' end='0x58258' /><slave name='avs_i2c_master_10.control' start='0x58258' end='0x58260' /><slave name='avs_i2c_master_9.control' start='0x58260' end='0x58268' /><slave name='avs_i2c_master_8.control' start='0x58268' end='0x58270' /><slave name='avs_i2c_master_7.control' start='0x58270' end='0x58278' /><slave name='avs_i2c_master_6.control' start='0x58278' end='0x58280' /><slave name='avs_i2c_master_5.control' start='0x58280' end='0x58288' /><slave name='avs_i2c_master_4.control' start='0x58288' end='0x58290' /><slave name='avs_i2c_master_3.control' start='0x58290' end='0x58298' /><slave name='avs_i2c_master_2.control' start='0x58298' end='0x582A0' /><slave name='avs_i2c_master_1.control' start='0x582A0' end='0x582A8' /><slave name='avs_i2c_master_0.control' start='0x582A8' end='0x582B0' /></address-map>]]></parameter>
-  <parameter name="clockFrequency" value="50000000" />
-  <parameter name="deviceFamilyName" value="Arria 10" />
-  <parameter name="internalIrqMaskSystemInfo" value="2047" />
-  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
-  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGICAL_FLOORPLANNER_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 0 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
-  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
-  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
-  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
- </module>
- <module
-   kind="avs_i2c_master"
-   version="1.0"
-   enabled="1"
-   name="avs_i2c_master_0">
-  <parameter name="g_control_adr_w" value="1" />
-  <parameter name="g_protocol_adr_w" value="10" />
-  <parameter name="g_result_adr_w" value="10" />
-  <parameter name="g_clk_cnt" value="399" />
-  <parameter name="g_comma_w" value="0" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_i2c_master"
-   version="1.0"
-   enabled="1"
-   name="avs_i2c_master_1">
-  <parameter name="g_control_adr_w" value="1" />
-  <parameter name="g_protocol_adr_w" value="10" />
-  <parameter name="g_result_adr_w" value="10" />
-  <parameter name="g_clk_cnt" value="399" />
-  <parameter name="g_comma_w" value="0" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="altera_avalon_onchip_memory2"
-   version="14.0"
-   enabled="1"
-   name="onchip_memory2_0">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="dataWidth" value="32" />
-  <parameter name="dualPort" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_mem.hex" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="32768" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
-  <parameter name="deviceFamily" value="Arria 10" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGICAL_FLOORPLANNER_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 0 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
- </module>
- <module
-   kind="avs_i2c_master"
-   version="1.0"
-   enabled="1"
-   name="avs_i2c_master_2">
-  <parameter name="g_control_adr_w" value="1" />
-  <parameter name="g_protocol_adr_w" value="10" />
-  <parameter name="g_result_adr_w" value="10" />
-  <parameter name="g_clk_cnt" value="399" />
-  <parameter name="g_comma_w" value="0" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_i2c_master"
-   version="1.0"
-   enabled="1"
-   name="avs_i2c_master_3">
-  <parameter name="g_control_adr_w" value="1" />
-  <parameter name="g_protocol_adr_w" value="10" />
-  <parameter name="g_result_adr_w" value="10" />
-  <parameter name="g_clk_cnt" value="399" />
-  <parameter name="g_comma_w" value="0" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_i2c_master"
-   version="1.0"
-   enabled="1"
-   name="avs_i2c_master_4">
-  <parameter name="g_control_adr_w" value="1" />
-  <parameter name="g_protocol_adr_w" value="10" />
-  <parameter name="g_result_adr_w" value="10" />
-  <parameter name="g_clk_cnt" value="399" />
-  <parameter name="g_comma_w" value="0" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_i2c_master"
-   version="1.0"
-   enabled="1"
-   name="avs_i2c_master_5">
-  <parameter name="g_control_adr_w" value="1" />
-  <parameter name="g_protocol_adr_w" value="10" />
-  <parameter name="g_result_adr_w" value="10" />
-  <parameter name="g_clk_cnt" value="399" />
-  <parameter name="g_comma_w" value="0" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_i2c_master"
-   version="1.0"
-   enabled="1"
-   name="avs_i2c_master_6">
-  <parameter name="g_control_adr_w" value="1" />
-  <parameter name="g_protocol_adr_w" value="10" />
-  <parameter name="g_result_adr_w" value="10" />
-  <parameter name="g_clk_cnt" value="399" />
-  <parameter name="g_comma_w" value="0" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_i2c_master"
-   version="1.0"
-   enabled="1"
-   name="avs_i2c_master_7">
-  <parameter name="g_control_adr_w" value="1" />
-  <parameter name="g_protocol_adr_w" value="10" />
-  <parameter name="g_result_adr_w" value="10" />
-  <parameter name="g_clk_cnt" value="399" />
-  <parameter name="g_comma_w" value="0" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_i2c_master"
-   version="1.0"
-   enabled="1"
-   name="avs_i2c_master_8">
-  <parameter name="g_control_adr_w" value="1" />
-  <parameter name="g_protocol_adr_w" value="10" />
-  <parameter name="g_result_adr_w" value="10" />
-  <parameter name="g_clk_cnt" value="399" />
-  <parameter name="g_comma_w" value="0" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_i2c_master"
-   version="1.0"
-   enabled="1"
-   name="avs_i2c_master_9">
-  <parameter name="g_control_adr_w" value="1" />
-  <parameter name="g_protocol_adr_w" value="10" />
-  <parameter name="g_result_adr_w" value="10" />
-  <parameter name="g_clk_cnt" value="399" />
-  <parameter name="g_comma_w" value="0" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_i2c_master"
-   version="1.0"
-   enabled="1"
-   name="avs_i2c_master_10">
-  <parameter name="g_control_adr_w" value="1" />
-  <parameter name="g_protocol_adr_w" value="10" />
-  <parameter name="g_result_adr_w" value="10" />
-  <parameter name="g_clk_cnt" value="399" />
-  <parameter name="g_comma_w" value="0" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module kind="altera_eth_tse" version="14.0" enabled="1" name="eth_tse_0">
-  <parameter name="deviceFamilyName" value="Arria 10" />
-  <parameter name="core_variation" value="MAC_PCS" />
-  <parameter name="ifGMII" value="MII_GMII" />
-  <parameter name="enable_use_internal_fifo" value="true" />
-  <parameter name="enable_ecc" value="false" />
-  <parameter name="max_channels" value="1" />
-  <parameter name="use_misc_ports" value="true" />
-  <parameter name="transceiver_type" value="LVDS_IO" />
-  <parameter name="enable_hd_logic" value="false" />
-  <parameter name="enable_gmii_loopback" value="false" />
-  <parameter name="enable_sup_addr" value="false" />
-  <parameter name="stat_cnt_ena" value="true" />
-  <parameter name="ext_stat_cnt_ena" value="false" />
-  <parameter name="ena_hash" value="false" />
-  <parameter name="enable_shift16" value="true" />
-  <parameter name="enable_mac_flow_ctrl" value="false" />
-  <parameter name="enable_mac_vlan" value="false" />
-  <parameter name="enable_magic_detect" value="true" />
-  <parameter name="useMDIO" value="false" />
-  <parameter name="mdio_clk_div" value="40" />
-  <parameter name="enable_ena" value="32" />
-  <parameter name="eg_addr" value="11" />
-  <parameter name="ing_addr" value="11" />
-  <parameter name="phy_identifier" value="0" />
-  <parameter name="enable_sgmii" value="false" />
-  <parameter name="export_pwrdn" value="false" />
-  <parameter name="enable_alt_reconfig" value="false" />
-  <parameter name="starting_channel_number" value="0" />
-  <parameter name="phyip_pll_type" value="CMU" />
-  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
-  <parameter name="phyip_en_synce_support" value="false" />
-  <parameter name="phyip_pma_bonding_mode" value="x1" />
-  <parameter name="nf_phyip_rcfg_enable" value="false" />
-  <parameter name="enable_timestamping" value="false" />
-  <parameter name="enable_ptp_1step" value="false" />
-  <parameter name="tstamp_fp_width" value="4" />
-  <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
- </module>
- <module kind="altera_eth_tse" version="14.0" enabled="1" name="eth_tse_1">
-  <parameter name="deviceFamilyName" value="Arria 10" />
-  <parameter name="core_variation" value="MAC_PCS" />
-  <parameter name="ifGMII" value="MII_GMII" />
-  <parameter name="enable_use_internal_fifo" value="true" />
-  <parameter name="enable_ecc" value="false" />
-  <parameter name="max_channels" value="1" />
-  <parameter name="use_misc_ports" value="true" />
-  <parameter name="transceiver_type" value="LVDS_IO" />
-  <parameter name="enable_hd_logic" value="false" />
-  <parameter name="enable_gmii_loopback" value="false" />
-  <parameter name="enable_sup_addr" value="false" />
-  <parameter name="stat_cnt_ena" value="true" />
-  <parameter name="ext_stat_cnt_ena" value="false" />
-  <parameter name="ena_hash" value="false" />
-  <parameter name="enable_shift16" value="true" />
-  <parameter name="enable_mac_flow_ctrl" value="false" />
-  <parameter name="enable_mac_vlan" value="false" />
-  <parameter name="enable_magic_detect" value="true" />
-  <parameter name="useMDIO" value="false" />
-  <parameter name="mdio_clk_div" value="40" />
-  <parameter name="enable_ena" value="32" />
-  <parameter name="eg_addr" value="11" />
-  <parameter name="ing_addr" value="11" />
-  <parameter name="phy_identifier" value="0" />
-  <parameter name="enable_sgmii" value="false" />
-  <parameter name="export_pwrdn" value="false" />
-  <parameter name="enable_alt_reconfig" value="false" />
-  <parameter name="starting_channel_number" value="0" />
-  <parameter name="phyip_pll_type" value="CMU" />
-  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
-  <parameter name="phyip_en_synce_support" value="false" />
-  <parameter name="phyip_pma_bonding_mode" value="x1" />
-  <parameter name="nf_phyip_rcfg_enable" value="false" />
-  <parameter name="enable_timestamping" value="false" />
-  <parameter name="enable_ptp_1step" value="false" />
-  <parameter name="tstamp_fp_width" value="4" />
-  <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
- </module>
- <module kind="altera_avalon_pio" version="14.0" enabled="1" name="pio_0">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="direction" value="Input" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="false" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="11" />
-  <parameter name="clockRate" value="50000000" />
- </module>
- <module
-   kind="avs_i2c_master"
-   version="1.0"
-   enabled="1"
-   name="avs_i2c_master_11">
-  <parameter name="g_control_adr_w" value="1" />
-  <parameter name="g_protocol_adr_w" value="10" />
-  <parameter name="g_result_adr_w" value="10" />
-  <parameter name="g_clk_cnt" value="399" />
-  <parameter name="g_comma_w" value="0" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_common_mm_readlatency0"
-   version="1.0"
-   enabled="1"
-   name="reg_mac_front">
-  <parameter name="g_adr_w" value="15" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_common_mm_readlatency0"
-   version="1.0"
-   enabled="1"
-   name="reg_mac_back">
-  <parameter name="g_adr_w" value="15" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_common_mm"
-   version="1.0"
-   enabled="1"
-   name="reg_hdr_insert_front">
-  <parameter name="g_adr_w" value="3" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_common_mm"
-   version="1.0"
-   enabled="1"
-   name="reg_hdr_insert_back">
-  <parameter name="g_adr_w" value="3" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_common_mm"
-   version="1.0"
-   enabled="1"
-   name="ram_hdr_insert_front">
-  <parameter name="g_adr_w" value="6" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_common_mm"
-   version="1.0"
-   enabled="1"
-   name="ram_hdr_insert_back">
-  <parameter name="g_adr_w" value="6" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_common_mm"
-   version="1.0"
-   enabled="1"
-   name="ram_hdr_remove_front">
-  <parameter name="g_adr_w" value="6" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_common_mm"
-   version="1.0"
-   enabled="1"
-   name="ram_hdr_remove_back">
-  <parameter name="g_adr_w" value="6" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_common_mm"
-   version="1.0"
-   enabled="1"
-   name="reg_diagnostics_front_0">
-  <parameter name="g_adr_w" value="6" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_common_mm"
-   version="1.0"
-   enabled="1"
-   name="reg_diagnostics_front_1">
-  <parameter name="g_adr_w" value="6" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_common_mm"
-   version="1.0"
-   enabled="1"
-   name="reg_diagnostics_front_2">
-  <parameter name="g_adr_w" value="6" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_common_mm"
-   version="1.0"
-   enabled="1"
-   name="reg_diagnostics_back_0">
-  <parameter name="g_adr_w" value="6" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_common_mm"
-   version="1.0"
-   enabled="1"
-   name="reg_diagnostics_back_1">
-  <parameter name="g_adr_w" value="6" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module
-   kind="avs_common_mm"
-   version="1.0"
-   enabled="1"
-   name="reg_diagnostics_back_2">
-  <parameter name="g_adr_w" value="6" />
-  <parameter name="g_dat_w" value="32" />
-  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.instruction_master"
-   end="nios2_qsys_0.jtag_debug_module">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00050800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="nios2_qsys_0.jtag_debug_module">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00050800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection kind="clock" version="14.0" start="clk_0.clk" end="nios2_qsys_0.clk" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="nios2_qsys_0.reset_n" />
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="avs_i2c_master_0.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="avs_i2c_master_0.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_0.control">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x000582a8" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_0.protocol">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00057400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_0.result">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00057000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.0"
-   start="nios2_qsys_0.d_irq"
-   end="avs_i2c_master_0.interrupt">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="avs_i2c_master_1.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="avs_i2c_master_1.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_1.control">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x000582a0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_1.protocol">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00056c00" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_1.result">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00056800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.0"
-   start="nios2_qsys_0.d_irq"
-   end="avs_i2c_master_1.interrupt">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.instruction_master"
-   end="onchip_memory2_0.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00048000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="onchip_memory2_0.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00048000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="onchip_memory2_0.clk1" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="onchip_memory2_0.reset1" />
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="avs_i2c_master_2.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="avs_i2c_master_2.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_2.control">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058298" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_2.protocol">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00056400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_2.result">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00056000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="avs_i2c_master_3.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="avs_i2c_master_3.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_3.control">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058290" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_3.protocol">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00055c00" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_3.result">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00055800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="avs_i2c_master_4.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="avs_i2c_master_4.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_4.control">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058288" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_4.protocol">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00055400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_4.result">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00055000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="avs_i2c_master_5.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="avs_i2c_master_5.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_5.control">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058280" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_5.protocol">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00054c00" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_5.result">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00054800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="avs_i2c_master_6.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="avs_i2c_master_6.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_6.control">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058278" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_6.protocol">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00054400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_6.result">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00054000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="avs_i2c_master_7.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="avs_i2c_master_7.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_7.control">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058270" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_7.protocol">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00053c00" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_7.result">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00053800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="avs_i2c_master_8.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="avs_i2c_master_8.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_8.control">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058268" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_8.protocol">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00053400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_8.result">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00053000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="avs_i2c_master_9.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="avs_i2c_master_9.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_9.control">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058260" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_9.protocol">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00052c00" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_9.result">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00052800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="avs_i2c_master_10.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="avs_i2c_master_10.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_10.control">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058258" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_10.protocol">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00052400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_10.result">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00052000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.0"
-   start="nios2_qsys_0.d_irq"
-   end="avs_i2c_master_2.interrupt">
-  <parameter name="irqNumber" value="2" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.0"
-   start="nios2_qsys_0.d_irq"
-   end="avs_i2c_master_3.interrupt">
-  <parameter name="irqNumber" value="3" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.0"
-   start="nios2_qsys_0.d_irq"
-   end="avs_i2c_master_4.interrupt">
-  <parameter name="irqNumber" value="4" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.0"
-   start="nios2_qsys_0.d_irq"
-   end="avs_i2c_master_5.interrupt">
-  <parameter name="irqNumber" value="5" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.0"
-   start="nios2_qsys_0.d_irq"
-   end="avs_i2c_master_6.interrupt">
-  <parameter name="irqNumber" value="6" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.0"
-   start="nios2_qsys_0.d_irq"
-   end="avs_i2c_master_7.interrupt">
-  <parameter name="irqNumber" value="7" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.0"
-   start="nios2_qsys_0.d_irq"
-   end="avs_i2c_master_8.interrupt">
-  <parameter name="irqNumber" value="8" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.0"
-   start="nios2_qsys_0.d_irq"
-   end="avs_i2c_master_9.interrupt">
-  <parameter name="irqNumber" value="9" />
- </connection>
- <connection
-   kind="interrupt"
-   version="14.0"
-   start="nios2_qsys_0.d_irq"
-   end="avs_i2c_master_10.interrupt">
-  <parameter name="irqNumber" value="10" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="eth_tse_0.control_port_clock_connection" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="eth_tse_0.reset_connection" />
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="eth_tse_0.receive_clock_connection" />
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="eth_tse_0.transmit_clock_connection" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="eth_tse_0.control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00051c00" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="eth_tse_1.control_port_clock_connection" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="eth_tse_1.reset_connection" />
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="eth_tse_1.receive_clock_connection" />
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="eth_tse_1.transmit_clock_connection" />
- <connection
-   kind="avalon_streaming"
-   version="14.0"
-   start="eth_tse_0.receive"
-   end="eth_tse_1.transmit" />
- <connection
-   kind="avalon_streaming"
-   version="14.0"
-   start="eth_tse_1.receive"
-   end="eth_tse_0.transmit" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="eth_tse_1.control_port">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00051800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection kind="clock" version="14.0" start="clk_0.clk" end="pio_0.clk" />
- <connection kind="reset" version="14.0" start="clk_0.clk_reset" end="pio_0.reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="pio_0.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058240" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="avs_i2c_master_11.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="avs_i2c_master_11.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_11.control">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058250" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_11.protocol">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00051400" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="avs_i2c_master_11.result">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00051000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="reg_mac_front.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="reg_mac_front.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="reg_mac_front.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00020000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="reg_mac_back.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="reg_mac_back.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="reg_mac_back.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="reg_hdr_insert_front.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="reg_hdr_insert_front.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="reg_hdr_insert_front.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058220" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="reg_hdr_insert_back.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="reg_hdr_insert_back.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="reg_hdr_insert_back.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058200" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="ram_hdr_insert_front.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="ram_hdr_insert_front.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="ram_hdr_insert_front.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058100" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="ram_hdr_insert_back.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="ram_hdr_insert_back.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="ram_hdr_insert_back.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00058000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="ram_hdr_remove_front.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="ram_hdr_remove_front.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="ram_hdr_remove_front.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00057f00" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="ram_hdr_remove_back.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="ram_hdr_remove_back.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="ram_hdr_remove_back.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00057e00" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="reg_diagnostics_front_0.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="reg_diagnostics_front_0.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="reg_diagnostics_front_0.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00057d00" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="reg_diagnostics_front_1.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="reg_diagnostics_front_1.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="reg_diagnostics_front_1.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00057c00" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="reg_diagnostics_front_2.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="reg_diagnostics_front_2.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="reg_diagnostics_front_2.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00057b00" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="reg_diagnostics_back_0.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="reg_diagnostics_back_0.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="reg_diagnostics_back_0.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00057a00" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="reg_diagnostics_back_1.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="reg_diagnostics_back_1.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="reg_diagnostics_back_1.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00057900" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="14.0"
-   start="clk_0.clk"
-   end="reg_diagnostics_back_2.system" />
- <connection
-   kind="reset"
-   version="14.0"
-   start="clk_0.clk_reset"
-   end="reg_diagnostics_back_2.system_reset" />
- <connection
-   kind="avalon"
-   version="14.0"
-   start="nios2_qsys_0.data_master"
-   end="reg_diagnostics_back_2.mem">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00057800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
-</system>
diff --git a/boards/uniboard2/designs/unb2_test/src/ip/ddr4.qsys b/boards/uniboard2/designs/unb2_test/src/ip/ddr4.qsys
deleted file mode 100644
index 77341b0b94ad6494ac51e65a81c23c84873bb54b..0000000000000000000000000000000000000000
--- a/boards/uniboard2/designs/unb2_test/src/ip/ddr4.qsys
+++ /dev/null
@@ -1,656 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags="INTERNAL_COMPONENT=true"
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $${FILENAME}
-   {
-   }
-   element ddr4_inst
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="true" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="global_reset_reset_sink"
-   internal="ddr4_inst.global_reset_reset_sink"
-   type="reset"
-   dir="end">
-  <port name="global_reset_n" internal="global_reset_n" />
- </interface>
- <interface
-   name="pll_ref_clk_clock_sink"
-   internal="ddr4_inst.pll_ref_clk_clock_sink"
-   type="clock"
-   dir="end">
-  <port name="pll_ref_clk" internal="pll_ref_clk" />
- </interface>
- <interface
-   name="oct_conduit_end"
-   internal="ddr4_inst.oct_conduit_end"
-   type="conduit"
-   dir="end">
-  <port name="oct_rzqin" internal="oct_rzqin" />
- </interface>
- <interface
-   name="mem_conduit_end"
-   internal="ddr4_inst.mem_conduit_end"
-   type="conduit"
-   dir="end">
-  <port name="mem_ck" internal="mem_ck" />
-  <port name="mem_ck_n" internal="mem_ck_n" />
-  <port name="mem_a" internal="mem_a" />
-  <port name="mem_act_n" internal="mem_act_n" />
-  <port name="mem_ba" internal="mem_ba" />
-  <port name="mem_bg" internal="mem_bg" />
-  <port name="mem_cke" internal="mem_cke" />
-  <port name="mem_cs_n" internal="mem_cs_n" />
-  <port name="mem_odt" internal="mem_odt" />
-  <port name="mem_reset_n" internal="mem_reset_n" />
-  <port name="mem_par" internal="mem_par" />
-  <port name="mem_alert_n" internal="mem_alert_n" />
-  <port name="mem_dqs" internal="mem_dqs" />
-  <port name="mem_dqs_n" internal="mem_dqs_n" />
-  <port name="mem_dq" internal="mem_dq" />
-  <port name="mem_dbi_n" internal="mem_dbi_n" />
- </interface>
- <interface
-   name="status_conduit_end"
-   internal="ddr4_inst.status_conduit_end"
-   type="conduit"
-   dir="end">
-  <port name="local_cal_success" internal="local_cal_success" />
-  <port name="local_cal_fail" internal="local_cal_fail" />
- </interface>
- <interface
-   name="emif_usr_reset_reset_source"
-   internal="ddr4_inst.emif_usr_reset_reset_source"
-   type="reset"
-   dir="start">
-  <port name="emif_usr_reset_n" internal="emif_usr_reset_n" />
- </interface>
- <interface
-   name="emif_usr_clk_clock_source"
-   internal="ddr4_inst.emif_usr_clk_clock_source"
-   type="clock"
-   dir="start">
-  <port name="emif_usr_clk" internal="emif_usr_clk" />
- </interface>
- <interface
-   name="ctrl_amm_avalon_slave_0"
-   internal="ddr4_inst.ctrl_amm_avalon_slave_0"
-   type="avalon"
-   dir="end">
-  <port name="amm_ready_0" internal="amm_ready_0" />
-  <port name="amm_read_0" internal="amm_read_0" />
-  <port name="amm_write_0" internal="amm_write_0" />
-  <port name="amm_address_0" internal="amm_address_0" />
-  <port name="amm_readdata_0" internal="amm_readdata_0" />
-  <port name="amm_writedata_0" internal="amm_writedata_0" />
-  <port name="amm_burstcount_0" internal="amm_burstcount_0" />
-  <port name="amm_byteenable_0" internal="amm_byteenable_0" />
-  <port name="amm_readdatavalid_0" internal="amm_readdatavalid_0" />
- </interface>
- <module
-   kind="altera_emif"
-   version="14.0"
-   enabled="1"
-   name="ddr4_inst"
-   autoexport="1">
-  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="SYS_INFO_DEVICE" value="10AX115U3F45I2SGES" />
-  <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
-  <parameter name="IS_ED_SLAVE" value="false" />
-  <parameter name="INTERNAL_TESTING_MODE" value="false" />
-  <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_ddr4_inst</parameter>
-  <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
-  <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="1066.667" />
-  <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="false" />
-  <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="133.333" />
-  <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
-  <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
-  <parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
-  <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
-  <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="1200.0" />
-  <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
-  <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="25.0" />
-  <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
-  <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
-  <parameter name="PHY_DDR4_DEFAULT_IO" value="true" />
-  <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
-  <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
-  <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
-  <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
-  <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
-  <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
-  <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
-  <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
-  <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
-  <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
-  <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
-  <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
-  <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
-  <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
-  <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
-  <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
-  <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
-  <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
-  <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
-  <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
-  <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
-  <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
-  <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
-  <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
-  <parameter name="MEM_DDR3_DQ_WIDTH" value="72" />
-  <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
-  <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
-  <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
-  <parameter name="MEM_DDR3_CK_WIDTH" value="1" />
-  <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="14" />
-  <parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
-  <parameter name="MEM_DDR3_DM_EN" value="true" />
-  <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="false" />
-  <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0000000000000000" />
-  <parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
-  <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
-  <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
-  <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
-  <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
-  <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
-  <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
-  <parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
-  <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_6" />
-  <parameter name="MEM_DDR3_DLL_EN" value="true" />
-  <parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
-  <parameter name="MEM_DDR3_RTT_WR_ENUM">DDR3_RTT_WR_ODT_DISABLED</parameter>
-  <parameter name="MEM_DDR3_WTCL" value="6" />
-  <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
-  <parameter name="MEM_DDR3_TCL" value="7" />
-  <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
-  <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
-  <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
-  <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_DDR3_R_ODT0_2X2" value="off,on" />
-  <parameter name="MEM_DDR3_R_ODT1_2X2" value="on,off" />
-  <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,on" />
-  <parameter name="MEM_DDR3_W_ODT1_2X2" value="on,on" />
-  <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR3_R_ODT0_4X2" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR3_R_ODT0_4X4" value="off,off,off,off" />
-  <parameter name="MEM_DDR3_R_ODT1_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_R_ODT2_4X4" value="off,off,off,off" />
-  <parameter name="MEM_DDR3_R_ODT3_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
-  <parameter name="MEM_DDR3_TIS_PS" value="60" />
-  <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
-  <parameter name="MEM_DDR3_TIH_PS" value="95" />
-  <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
-  <parameter name="MEM_DDR3_TDS_PS" value="53" />
-  <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
-  <parameter name="MEM_DDR3_TDH_PS" value="55" />
-  <parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
-  <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
-  <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
-  <parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
-  <parameter name="MEM_DDR3_TDQSS_CYC" value="0.27" />
-  <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
-  <parameter name="MEM_DDR3_TDSH_CYC" value="0.18" />
-  <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
-  <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
-  <parameter name="MEM_DDR3_TDSS_CYC" value="0.18" />
-  <parameter name="MEM_DDR3_TINIT_US" value="500" />
-  <parameter name="MEM_DDR3_TMRD_CK_CYC" value="4" />
-  <parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
-  <parameter name="MEM_DDR3_TRCD_NS" value="13.09" />
-  <parameter name="MEM_DDR3_TRP_NS" value="13.09" />
-  <parameter name="MEM_DDR3_TREFI_US" value="7.8" />
-  <parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
-  <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
-  <parameter name="MEM_DDR3_TWTR_CYC" value="4" />
-  <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
-  <parameter name="MEM_DDR3_TRRD_CYC" value="6" />
-  <parameter name="MEM_DDR3_TRTP_CYC" value="8" />
-  <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_SODIMM" />
-  <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
-  <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
-  <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
-  <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="2" />
-  <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
-  <parameter name="MEM_DDR4_CK_WIDTH" value="2" />
-  <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
-  <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
-  <parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="2" />
-  <parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
-  <parameter name="MEM_DDR4_DM_EN" value="true" />
-  <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
-  <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_DATA_LANES</parameter>
-  <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
-  <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
-  <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
-  <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="false" />
-  <parameter name="MEM_DDR4_RDIMM_CONFIG" value="0000000000000000" />
-  <parameter name="MEM_DDR4_LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
-  <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
-  <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
-  <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
-  <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
-  <parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
-  <parameter name="MEM_DDR4_WRITE_CMD_LATENCY" value="4" />
-  <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
-  <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
-  <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
-  <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
-  <parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="false" />
-  <parameter name="MEM_DDR4_CAL_MODE" value="0" />
-  <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
-  <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
-  <parameter name="MEM_DDR4_READ_PREAMBLE" value="1" />
-  <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
-  <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
-  <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
-  <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
-  <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
-  <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
-  <parameter name="MEM_DDR4_READ_DBI" value="false" />
-  <parameter name="MEM_DDR4_VREFDQ_TRAINING_VALUE" value="60.0" />
-  <parameter name="MEM_DDR4_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
-  <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
-  <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
-  <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
-  <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
-  <parameter name="MEM_DDR4_DLL_EN" value="true" />
-  <parameter name="MEM_DDR4_RTT_NOM_ENUM">DDR4_RTT_NOM_ODT_DISABLED</parameter>
-  <parameter name="MEM_DDR4_RTT_WR_ENUM">DDR4_RTT_WR_ODT_DISABLED</parameter>
-  <parameter name="MEM_DDR4_WTCL" value="18" />
-  <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
-  <parameter name="MEM_DDR4_TCL" value="18" />
-  <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="true" />
-  <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_DDR4_R_ODT0_1X1" value="off" />
-  <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
-  <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
-  <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_DDR4_R_ODT0_2X2" value="off,on" />
-  <parameter name="MEM_DDR4_R_ODT1_2X2" value="on,off" />
-  <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
-  <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,on" />
-  <parameter name="MEM_DDR4_W_ODT1_2X2" value="on,on" />
-  <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR4_R_ODT0_4X4" value="off,off,off,off" />
-  <parameter name="MEM_DDR4_R_ODT1_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_R_ODT2_4X4" value="off,off,off,off" />
-  <parameter name="MEM_DDR4_R_ODT3_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
-  <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
-  <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
-  <parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2400" />
-  <parameter name="MEM_DDR4_TIS_PS" value="60" />
-  <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
-  <parameter name="MEM_DDR4_TIH_PS" value="95" />
-  <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
-  <parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
-  <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
-  <parameter name="MEM_DDR4_TDQSQ_PS" value="75" />
-  <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
-  <parameter name="MEM_DDR4_TDQSCK_PS" value="180" />
-  <parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
-  <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
-  <parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
-  <parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
-  <parameter name="MEM_DDR4_TWLS_PS" value="122.0" />
-  <parameter name="MEM_DDR4_TWLH_PS" value="122.0" />
-  <parameter name="MEM_DDR4_TINIT_US" value="500" />
-  <parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
-  <parameter name="MEM_DDR4_TRAS_NS" value="33.0" />
-  <parameter name="MEM_DDR4_TRCD_NS" value="14.06" />
-  <parameter name="MEM_DDR4_TRP_NS" value="14.06" />
-  <parameter name="MEM_DDR4_TREFI_US" value="7.8" />
-  <parameter name="MEM_DDR4_TRFC_NS" value="160.0" />
-  <parameter name="MEM_DDR4_TWR_NS" value="15.0" />
-  <parameter name="MEM_DDR4_TWTR_L_CYC" value="4" />
-  <parameter name="MEM_DDR4_TWTR_S_CYC" value="2" />
-  <parameter name="MEM_DDR4_TFAW_NS" value="25.0" />
-  <parameter name="MEM_DDR4_TRRD_L_CYC" value="5" />
-  <parameter name="MEM_DDR4_TRRD_S_CYC" value="4" />
-  <parameter name="MEM_DDR4_TCCD_L_CYC" value="5" />
-  <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
-  <parameter name="MEM_DDR4_TRTP_CYC" value="8" />
-  <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
-  <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
-  <parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
-  <parameter name="MEM_QDR2_BWS_EN" value="true" />
-  <parameter name="MEM_QDR2_BL" value="4" />
-  <parameter name="MEM_QDR2_SPEEDBIN_ENUM" value="QDR2_SPEEDBIN_633" />
-  <parameter name="MEM_QDR2_TRL_CYC" value="2.5" />
-  <parameter name="MEM_QDR2_TSA_NS" value="0.23" />
-  <parameter name="MEM_QDR2_THA_NS" value="0.18" />
-  <parameter name="MEM_QDR2_TSD_NS" value="0.23" />
-  <parameter name="MEM_QDR2_THD_NS" value="0.18" />
-  <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
-  <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
-  <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
-  <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
-  <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
-  <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
-  <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
-  <parameter name="MEM_RLD2_ADDR_WIDTH" value="21" />
-  <parameter name="MEM_RLD2_BANK_ADDR_WIDTH" value="3" />
-  <parameter name="MEM_RLD2_DM_EN" value="true" />
-  <parameter name="MEM_RLD2_BL" value="4" />
-  <parameter name="MEM_RLD2_CONFIG_ENUM">RLD2_CONFIG_TRC_8_TRL_8_TWL_9</parameter>
-  <parameter name="MEM_RLD2_DRIVE_IMPEDENCE_ENUM">RLD2_DRIVE_IMPEDENCE_INTERNAL_50</parameter>
-  <parameter name="MEM_RLD2_ODT_MODE_ENUM" value="RLD2_ODT_ON" />
-  <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
-  <parameter name="MEM_RLD2_REFRESH_INTERVAL_US" value="0.24" />
-  <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
-  <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
-  <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
-  <parameter name="MEM_RLD2_TAH_NS" value="0.3" />
-  <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
-  <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
-  <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
-  <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
-  <parameter name="MEM_RLD2_TCKDK_MAX_NS" value="0.3" />
-  <parameter name="MEM_RLD2_TCKDK_MIN_NS" value="-0.3" />
-  <parameter name="MEM_RLD2_TCKQK_MAX_NS" value="0.2" />
-  <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
-  <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
-  <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
-  <parameter name="MEM_RLD3_ADDR_WIDTH" value="20" />
-  <parameter name="MEM_RLD3_BANK_ADDR_WIDTH" value="4" />
-  <parameter name="MEM_RLD3_DM_EN" value="true" />
-  <parameter name="MEM_RLD3_BL" value="2" />
-  <parameter name="MEM_RLD3_DATA_LATENCY_MODE_ENUM" value="RLD3_DL_RL16_WL17" />
-  <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
-  <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
-  <parameter name="MEM_RLD3_ODT_MODE_ENUM" value="RLD3_ODT_40" />
-  <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
-  <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
-  <parameter name="MEM_RLD3_SPEEDBIN_ENUM" value="RLD3_SPEEDBIN_093E" />
-  <parameter name="MEM_RLD3_TDS_PS" value="-30" />
-  <parameter name="MEM_RLD3_TDH_PS" value="5" />
-  <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
-  <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
-  <parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
-  <parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
-  <parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
-  <parameter name="MEM_RLD3_TIS_PS" value="85" />
-  <parameter name="MEM_RLD3_TIH_PS" value="65" />
-  <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="1.0" />
-  <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
-  <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.094" />
-  <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.094" />
-  <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.031" />
-  <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.063" />
-  <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.063" />
-  <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
-  <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_PKG+BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
-  <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
-  <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.094" />
-  <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.094" />
-  <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.031" />
-  <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.063" />
-  <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.063" />
-  <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="true" />
-  <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_PKG+BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
-  <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
-  <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.094" />
-  <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.094" />
-  <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.031" />
-  <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.063" />
-  <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.063" />
-  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
-  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
-  <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
-  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_Q_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_D_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
-  <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
-  <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
-  <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
-  <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
-  <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.094" />
-  <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.094" />
-  <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.031" />
-  <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.063" />
-  <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.063" />
-  <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
-  <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_PKG+BRD_SKEW_WITHIN_QK_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
-  <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
-  <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
-  <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
-  <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
-  <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
-  <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
-  <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
-  <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
-  <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
-  <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
-  <parameter name="CTRL_DDR3_ECC_EN" value="false" />
-  <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
-  <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
-  <parameter name="CTRL_DDR3_STARVE_LIMIT" value="63" />
-  <parameter name="CTRL_DDR3_MMR_EN" value="false" />
-  <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
-  <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
-  <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
-  <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
-  <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
-  <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
-  <parameter name="CTRL_DDR4_ECC_EN" value="false" />
-  <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
-  <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
-  <parameter name="CTRL_DDR4_STARVE_LIMIT" value="63" />
-  <parameter name="CTRL_DDR4_MMR_EN" value="false" />
-  <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
-  <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
-  <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
-  <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
-  <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
-  <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
-  <parameter name="DIAG_EXPORT_VJI" value="false" />
-  <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
-  <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
-  <parameter name="DIAG_EXTRA_CONFIGS" value="" />
-  <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
-  <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
-  <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
-  <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
-  <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
-  <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
-  <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
-  <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
-  <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
-  <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
-  <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
-  <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
- </module>
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
-</system>
diff --git a/boards/uniboard2/designs/unb2_test/src/ip/system_pll.qsys b/boards/uniboard2/designs/unb2_test/src/ip/system_pll.qsys
deleted file mode 100644
index 5fe3aef22825203cf665d1ee833f39aa82713704..0000000000000000000000000000000000000000
--- a/boards/uniboard2/designs/unb2_test/src/ip/system_pll.qsys
+++ /dev/null
@@ -1,370 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags="INTERNAL_COMPONENT=true"
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $${FILENAME}
-   {
-   }
-   element system_pll_inst
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="true" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="outclk2"
-   internal="system_pll_inst.outclk2"
-   type="clock"
-   dir="start">
-  <port name="outclk_2" internal="outclk_2" />
- </interface>
- <interface name="reset" internal="system_pll_inst.reset" type="reset" dir="end">
-  <port name="rst" internal="rst" />
- </interface>
- <interface
-   name="outclk1"
-   internal="system_pll_inst.outclk1"
-   type="clock"
-   dir="start">
-  <port name="outclk_1" internal="outclk_1" />
- </interface>
- <interface
-   name="refclk"
-   internal="system_pll_inst.refclk"
-   type="clock"
-   dir="end">
-  <port name="refclk" internal="refclk" />
- </interface>
- <interface
-   name="outclk0"
-   internal="system_pll_inst.outclk0"
-   type="clock"
-   dir="start">
-  <port name="outclk_0" internal="outclk_0" />
- </interface>
- <interface
-   name="locked"
-   internal="system_pll_inst.locked"
-   type="conduit"
-   dir="end">
-  <port name="locked" internal="locked" />
- </interface>
- <module
-   kind="altera_iopll"
-   version="14.0"
-   enabled="1"
-   name="system_pll_inst"
-   autoexport="1">
-  <parameter name="gui_en_reconf" value="false" />
-  <parameter name="gui_en_dps_ports" value="false" />
-  <parameter name="gui_pll_mode" value="Integer-N PLL" />
-  <parameter name="gui_reference_clock_frequency" value="125.0" />
-  <parameter name="gui_fractional_cout" value="32" />
-  <parameter name="gui_dsm_out_sel" value="1st_order" />
-  <parameter name="gui_use_locked" value="true" />
-  <parameter name="gui_en_adv_params" value="false" />
-  <parameter name="gui_pll_bandwidth_preset" value="Low" />
-  <parameter name="gui_pll_auto_reset" value="false" />
-  <parameter name="gui_en_lvds_ports" value="false" />
-  <parameter name="gui_operation_mode" value="direct" />
-  <parameter name="gui_feedback_clock" value="Global Clock" />
-  <parameter name="gui_refclk_switch" value="false" />
-  <parameter name="gui_refclk1_frequency" value="100.0" />
-  <parameter name="gui_en_phout_ports" value="false" />
-  <parameter name="gui_phout_division" value="1" />
-  <parameter name="gui_en_extclkout_ports" value="false" />
-  <parameter name="gui_number_of_clocks" value="3" />
-  <parameter name="gui_multiply_factor" value="1" />
-  <parameter name="gui_divide_factor_n" value="1" />
-  <parameter name="gui_frac_multiply_factor" value="1" />
-  <parameter name="gui_fix_vco_frequency" value="false" />
-  <parameter name="gui_fixed_vco_frequency" value="600.0" />
-  <parameter name="gui_enable_output_counter_cascading" value="false" />
-  <parameter name="gui_mif_generate" value="false" />
-  <parameter name="gui_device_speed_grade" value="1" />
-  <parameter name="system_info_device_family" value="Arria 10" />
-  <parameter name="system_info_device_component" value="10AX115U3F45I2LG" />
-  <parameter name="system_info_device_speed_grade" value="2" />
-  <parameter name="gui_active_clk" value="false" />
-  <parameter name="gui_clk_bad" value="false" />
-  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
-  <parameter name="gui_switchover_delay" value="0" />
-  <parameter name="gui_enable_cascade_out" value="false" />
-  <parameter name="gui_cascade_outclk_index" value="0" />
-  <parameter name="gui_enable_cascade_in" value="false" />
-  <parameter name="gui_pll_cascading_mode" value="adjpllin" />
-  <parameter name="gui_enable_mif_dps" value="false" />
-  <parameter name="gui_dps_cntr" value="C0" />
-  <parameter name="gui_dps_num" value="1" />
-  <parameter name="gui_dps_dir" value="Positive" />
-  <parameter name="gui_extclkout_0_source" value="C0" />
-  <parameter name="gui_extclkout_1_source" value="C0" />
-  <parameter name="gui_clock_name_global0" value="false" />
-  <parameter name="gui_clock_name_global1" value="false" />
-  <parameter name="gui_clock_name_global2" value="false" />
-  <parameter name="gui_clock_name_global3" value="false" />
-  <parameter name="gui_clock_name_global4" value="false" />
-  <parameter name="gui_clock_name_global5" value="false" />
-  <parameter name="gui_clock_name_global6" value="false" />
-  <parameter name="gui_clock_name_global7" value="false" />
-  <parameter name="gui_clock_name_global8" value="false" />
-  <parameter name="gui_clock_name_global9" value="false" />
-  <parameter name="gui_clock_name_global10" value="false" />
-  <parameter name="gui_clock_name_global11" value="false" />
-  <parameter name="gui_clock_name_global12" value="false" />
-  <parameter name="gui_clock_name_global13" value="false" />
-  <parameter name="gui_clock_name_global14" value="false" />
-  <parameter name="gui_clock_name_global15" value="false" />
-  <parameter name="gui_clock_name_global16" value="false" />
-  <parameter name="gui_clock_name_global17" value="false" />
-  <parameter name="gui_clock_name_string0" value="" />
-  <parameter name="gui_clock_name_string1" value="" />
-  <parameter name="gui_clock_name_string2" value="" />
-  <parameter name="gui_clock_name_string3" value="" />
-  <parameter name="gui_clock_name_string4" value="" />
-  <parameter name="gui_clock_name_string5" value="" />
-  <parameter name="gui_clock_name_string6" value="" />
-  <parameter name="gui_clock_name_string7" value="" />
-  <parameter name="gui_clock_name_string8" value="" />
-  <parameter name="gui_clock_name_string9" value="" />
-  <parameter name="gui_clock_name_string10" value="" />
-  <parameter name="gui_clock_name_string11" value="" />
-  <parameter name="gui_clock_name_string12" value="" />
-  <parameter name="gui_clock_name_string13" value="" />
-  <parameter name="gui_clock_name_string14" value="" />
-  <parameter name="gui_clock_name_string15" value="" />
-  <parameter name="gui_clock_name_string16" value="" />
-  <parameter name="gui_clock_name_string17" value="" />
-  <parameter name="gui_divide_factor_c0" value="1" />
-  <parameter name="gui_divide_factor_c1" value="1" />
-  <parameter name="gui_divide_factor_c2" value="1" />
-  <parameter name="gui_divide_factor_c3" value="1" />
-  <parameter name="gui_divide_factor_c4" value="1" />
-  <parameter name="gui_divide_factor_c5" value="1" />
-  <parameter name="gui_divide_factor_c6" value="1" />
-  <parameter name="gui_divide_factor_c7" value="1" />
-  <parameter name="gui_divide_factor_c8" value="1" />
-  <parameter name="gui_divide_factor_c9" value="1" />
-  <parameter name="gui_divide_factor_c10" value="1" />
-  <parameter name="gui_divide_factor_c11" value="1" />
-  <parameter name="gui_divide_factor_c12" value="1" />
-  <parameter name="gui_divide_factor_c13" value="1" />
-  <parameter name="gui_divide_factor_c14" value="1" />
-  <parameter name="gui_divide_factor_c15" value="1" />
-  <parameter name="gui_divide_factor_c16" value="1" />
-  <parameter name="gui_divide_factor_c17" value="1" />
-  <parameter name="gui_cascade_counter0" value="false" />
-  <parameter name="gui_cascade_counter1" value="false" />
-  <parameter name="gui_cascade_counter2" value="false" />
-  <parameter name="gui_cascade_counter3" value="false" />
-  <parameter name="gui_cascade_counter4" value="false" />
-  <parameter name="gui_cascade_counter5" value="false" />
-  <parameter name="gui_cascade_counter6" value="false" />
-  <parameter name="gui_cascade_counter7" value="false" />
-  <parameter name="gui_cascade_counter8" value="false" />
-  <parameter name="gui_cascade_counter9" value="false" />
-  <parameter name="gui_cascade_counter10" value="false" />
-  <parameter name="gui_cascade_counter11" value="false" />
-  <parameter name="gui_cascade_counter12" value="false" />
-  <parameter name="gui_cascade_counter13" value="false" />
-  <parameter name="gui_cascade_counter14" value="false" />
-  <parameter name="gui_cascade_counter15" value="false" />
-  <parameter name="gui_cascade_counter16" value="false" />
-  <parameter name="gui_cascade_counter17" value="false" />
-  <parameter name="gui_output_clock_frequency0" value="100.0" />
-  <parameter name="gui_output_clock_frequency1" value="300.0" />
-  <parameter name="gui_output_clock_frequency2" value="125.0" />
-  <parameter name="gui_output_clock_frequency3" value="100.0" />
-  <parameter name="gui_output_clock_frequency4" value="100.0" />
-  <parameter name="gui_output_clock_frequency5" value="100.0" />
-  <parameter name="gui_output_clock_frequency6" value="100.0" />
-  <parameter name="gui_output_clock_frequency7" value="100.0" />
-  <parameter name="gui_output_clock_frequency8" value="100.0" />
-  <parameter name="gui_output_clock_frequency9" value="100.0" />
-  <parameter name="gui_output_clock_frequency10" value="100.0" />
-  <parameter name="gui_output_clock_frequency11" value="100.0" />
-  <parameter name="gui_output_clock_frequency12" value="100.0" />
-  <parameter name="gui_output_clock_frequency13" value="100.0" />
-  <parameter name="gui_output_clock_frequency14" value="100.0" />
-  <parameter name="gui_output_clock_frequency15" value="100.0" />
-  <parameter name="gui_output_clock_frequency16" value="100.0" />
-  <parameter name="gui_output_clock_frequency17" value="100.0" />
-  <parameter name="gui_actual_output_clock_frequency0" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency1" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency2" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency3" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency4" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency5" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency6" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency7" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency8" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency9" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency10" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency11" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency12" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency13" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency14" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency15" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency16" value="0.0" />
-  <parameter name="gui_actual_output_clock_frequency17" value="0.0" />
-  <parameter name="gui_ps_units0" value="ps" />
-  <parameter name="gui_ps_units1" value="ps" />
-  <parameter name="gui_ps_units2" value="ps" />
-  <parameter name="gui_ps_units3" value="ps" />
-  <parameter name="gui_ps_units4" value="ps" />
-  <parameter name="gui_ps_units5" value="ps" />
-  <parameter name="gui_ps_units6" value="ps" />
-  <parameter name="gui_ps_units7" value="ps" />
-  <parameter name="gui_ps_units8" value="ps" />
-  <parameter name="gui_ps_units9" value="ps" />
-  <parameter name="gui_ps_units10" value="ps" />
-  <parameter name="gui_ps_units11" value="ps" />
-  <parameter name="gui_ps_units12" value="ps" />
-  <parameter name="gui_ps_units13" value="ps" />
-  <parameter name="gui_ps_units14" value="ps" />
-  <parameter name="gui_ps_units15" value="ps" />
-  <parameter name="gui_ps_units16" value="ps" />
-  <parameter name="gui_ps_units17" value="ps" />
-  <parameter name="gui_phase_shift0" value="0.0" />
-  <parameter name="gui_phase_shift1" value="0.0" />
-  <parameter name="gui_phase_shift2" value="0.0" />
-  <parameter name="gui_phase_shift3" value="0.0" />
-  <parameter name="gui_phase_shift4" value="0.0" />
-  <parameter name="gui_phase_shift5" value="0.0" />
-  <parameter name="gui_phase_shift6" value="0.0" />
-  <parameter name="gui_phase_shift7" value="0.0" />
-  <parameter name="gui_phase_shift8" value="0.0" />
-  <parameter name="gui_phase_shift9" value="0.0" />
-  <parameter name="gui_phase_shift10" value="0.0" />
-  <parameter name="gui_phase_shift11" value="0.0" />
-  <parameter name="gui_phase_shift12" value="0.0" />
-  <parameter name="gui_phase_shift13" value="0.0" />
-  <parameter name="gui_phase_shift14" value="0.0" />
-  <parameter name="gui_phase_shift15" value="0.0" />
-  <parameter name="gui_phase_shift16" value="0.0" />
-  <parameter name="gui_phase_shift17" value="0.0" />
-  <parameter name="gui_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_actual_phase_shift0" value="0.0" />
-  <parameter name="gui_actual_phase_shift1" value="0.0" />
-  <parameter name="gui_actual_phase_shift2" value="0.0" />
-  <parameter name="gui_actual_phase_shift3" value="0.0" />
-  <parameter name="gui_actual_phase_shift4" value="0.0" />
-  <parameter name="gui_actual_phase_shift5" value="0.0" />
-  <parameter name="gui_actual_phase_shift6" value="0.0" />
-  <parameter name="gui_actual_phase_shift7" value="0.0" />
-  <parameter name="gui_actual_phase_shift8" value="0.0" />
-  <parameter name="gui_actual_phase_shift9" value="0.0" />
-  <parameter name="gui_actual_phase_shift10" value="0.0" />
-  <parameter name="gui_actual_phase_shift11" value="0.0" />
-  <parameter name="gui_actual_phase_shift12" value="0.0" />
-  <parameter name="gui_actual_phase_shift13" value="0.0" />
-  <parameter name="gui_actual_phase_shift14" value="0.0" />
-  <parameter name="gui_actual_phase_shift15" value="0.0" />
-  <parameter name="gui_actual_phase_shift16" value="0.0" />
-  <parameter name="gui_actual_phase_shift17" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
-  <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
-  <parameter name="gui_duty_cycle0" value="50.0" />
-  <parameter name="gui_duty_cycle1" value="50.0" />
-  <parameter name="gui_duty_cycle2" value="50.0" />
-  <parameter name="gui_duty_cycle3" value="50.0" />
-  <parameter name="gui_duty_cycle4" value="50.0" />
-  <parameter name="gui_duty_cycle5" value="50.0" />
-  <parameter name="gui_duty_cycle6" value="50.0" />
-  <parameter name="gui_duty_cycle7" value="50.0" />
-  <parameter name="gui_duty_cycle8" value="50.0" />
-  <parameter name="gui_duty_cycle9" value="50.0" />
-  <parameter name="gui_duty_cycle10" value="50.0" />
-  <parameter name="gui_duty_cycle11" value="50.0" />
-  <parameter name="gui_duty_cycle12" value="50.0" />
-  <parameter name="gui_duty_cycle13" value="50.0" />
-  <parameter name="gui_duty_cycle14" value="50.0" />
-  <parameter name="gui_duty_cycle15" value="50.0" />
-  <parameter name="gui_duty_cycle16" value="50.0" />
-  <parameter name="gui_duty_cycle17" value="50.0" />
-  <parameter name="gui_actual_duty_cycle0" value="50.0" />
-  <parameter name="gui_actual_duty_cycle1" value="50.0" />
-  <parameter name="gui_actual_duty_cycle2" value="50.0" />
-  <parameter name="gui_actual_duty_cycle3" value="50.0" />
-  <parameter name="gui_actual_duty_cycle4" value="50.0" />
-  <parameter name="gui_actual_duty_cycle5" value="50.0" />
-  <parameter name="gui_actual_duty_cycle6" value="50.0" />
-  <parameter name="gui_actual_duty_cycle7" value="50.0" />
-  <parameter name="gui_actual_duty_cycle8" value="50.0" />
-  <parameter name="gui_actual_duty_cycle9" value="50.0" />
-  <parameter name="gui_actual_duty_cycle10" value="50.0" />
-  <parameter name="gui_actual_duty_cycle11" value="50.0" />
-  <parameter name="gui_actual_duty_cycle12" value="50.0" />
-  <parameter name="gui_actual_duty_cycle13" value="50.0" />
-  <parameter name="gui_actual_duty_cycle14" value="50.0" />
-  <parameter name="gui_actual_duty_cycle15" value="50.0" />
-  <parameter name="gui_actual_duty_cycle16" value="50.0" />
-  <parameter name="gui_actual_duty_cycle17" value="50.0" />
-  <parameter name="AUTO_REFCLK_CLOCK_RATE" value="0" />
- </module>
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
-</system>
diff --git a/boards/uniboard2/designs/unb2_test/src/ip/transceiver_phy.qsys b/boards/uniboard2/designs/unb2_test/src/ip/transceiver_phy.qsys
deleted file mode 100644
index c4b730b00171aab513804d3a0d232bf300b87e4a..0000000000000000000000000000000000000000
--- a/boards/uniboard2/designs/unb2_test/src/ip/transceiver_phy.qsys
+++ /dev/null
@@ -1,439 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags="INTERNAL_COMPONENT=true"
-   categories="" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $${FILENAME}
-   {
-   }
-   element transceiver_phy_inst
-   {
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="true" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="tx_analogreset"
-   internal="transceiver_phy_inst.tx_analogreset"
-   type="conduit"
-   dir="end">
-  <port name="tx_analogreset" internal="tx_analogreset" />
- </interface>
- <interface
-   name="tx_digitalreset"
-   internal="transceiver_phy_inst.tx_digitalreset"
-   type="conduit"
-   dir="end">
-  <port name="tx_digitalreset" internal="tx_digitalreset" />
- </interface>
- <interface
-   name="rx_analogreset"
-   internal="transceiver_phy_inst.rx_analogreset"
-   type="conduit"
-   dir="end">
-  <port name="rx_analogreset" internal="rx_analogreset" />
- </interface>
- <interface
-   name="rx_digitalreset"
-   internal="transceiver_phy_inst.rx_digitalreset"
-   type="conduit"
-   dir="end">
-  <port name="rx_digitalreset" internal="rx_digitalreset" />
- </interface>
- <interface
-   name="tx_cal_busy"
-   internal="transceiver_phy_inst.tx_cal_busy"
-   type="conduit"
-   dir="end">
-  <port name="tx_cal_busy" internal="tx_cal_busy" />
- </interface>
- <interface
-   name="rx_cal_busy"
-   internal="transceiver_phy_inst.rx_cal_busy"
-   type="conduit"
-   dir="end">
-  <port name="rx_cal_busy" internal="rx_cal_busy" />
- </interface>
- <interface
-   name="tx_serial_clk0"
-   internal="transceiver_phy_inst.tx_serial_clk0"
-   type="conduit"
-   dir="end">
-  <port name="tx_serial_clk0" internal="tx_serial_clk0" />
- </interface>
- <interface
-   name="rx_cdr_refclk0"
-   internal="transceiver_phy_inst.rx_cdr_refclk0"
-   type="conduit"
-   dir="end">
-  <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
- </interface>
- <interface
-   name="tx_serial_data"
-   internal="transceiver_phy_inst.tx_serial_data"
-   type="conduit"
-   dir="end">
-  <port name="tx_serial_data" internal="tx_serial_data" />
- </interface>
- <interface
-   name="rx_serial_data"
-   internal="transceiver_phy_inst.rx_serial_data"
-   type="conduit"
-   dir="end">
-  <port name="rx_serial_data" internal="rx_serial_data" />
- </interface>
- <interface
-   name="rx_is_lockedtodata"
-   internal="transceiver_phy_inst.rx_is_lockedtodata"
-   type="conduit"
-   dir="end">
-  <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
- </interface>
- <interface
-   name="tx_coreclkin"
-   internal="transceiver_phy_inst.tx_coreclkin"
-   type="conduit"
-   dir="end">
-  <port name="tx_coreclkin" internal="tx_coreclkin" />
- </interface>
- <interface
-   name="rx_coreclkin"
-   internal="transceiver_phy_inst.rx_coreclkin"
-   type="conduit"
-   dir="end">
-  <port name="rx_coreclkin" internal="rx_coreclkin" />
- </interface>
- <interface
-   name="tx_clkout"
-   internal="transceiver_phy_inst.tx_clkout"
-   type="conduit"
-   dir="end">
-  <port name="tx_clkout" internal="tx_clkout" />
- </interface>
- <interface
-   name="rx_clkout"
-   internal="transceiver_phy_inst.rx_clkout"
-   type="conduit"
-   dir="end">
-  <port name="rx_clkout" internal="rx_clkout" />
- </interface>
- <interface
-   name="tx_parallel_data"
-   internal="transceiver_phy_inst.tx_parallel_data"
-   type="conduit"
-   dir="end">
-  <port name="tx_parallel_data" internal="tx_parallel_data" />
- </interface>
- <interface
-   name="tx_control"
-   internal="transceiver_phy_inst.tx_control"
-   type="conduit"
-   dir="end">
-  <port name="tx_control" internal="tx_control" />
- </interface>
- <interface
-   name="tx_err_ins"
-   internal="transceiver_phy_inst.tx_err_ins"
-   type="conduit"
-   dir="end">
-  <port name="tx_err_ins" internal="tx_err_ins" />
- </interface>
- <interface
-   name="unused_tx_parallel_data"
-   internal="transceiver_phy_inst.unused_tx_parallel_data"
-   type="conduit"
-   dir="end">
-  <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
- </interface>
- <interface
-   name="unused_tx_control"
-   internal="transceiver_phy_inst.unused_tx_control"
-   type="conduit"
-   dir="end">
-  <port name="unused_tx_control" internal="unused_tx_control" />
- </interface>
- <interface
-   name="rx_parallel_data"
-   internal="transceiver_phy_inst.rx_parallel_data"
-   type="conduit"
-   dir="end">
-  <port name="rx_parallel_data" internal="rx_parallel_data" />
- </interface>
- <interface
-   name="rx_control"
-   internal="transceiver_phy_inst.rx_control"
-   type="conduit"
-   dir="end">
-  <port name="rx_control" internal="rx_control" />
- </interface>
- <interface
-   name="unused_rx_parallel_data"
-   internal="transceiver_phy_inst.unused_rx_parallel_data"
-   type="conduit"
-   dir="end">
-  <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
- </interface>
- <interface
-   name="unused_rx_control"
-   internal="transceiver_phy_inst.unused_rx_control"
-   type="conduit"
-   dir="end">
-  <port name="unused_rx_control" internal="unused_rx_control" />
- </interface>
- <interface
-   name="tx_enh_data_valid"
-   internal="transceiver_phy_inst.tx_enh_data_valid"
-   type="conduit"
-   dir="end">
-  <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
- </interface>
- <interface
-   name="rx_enh_data_valid"
-   internal="transceiver_phy_inst.rx_enh_data_valid"
-   type="conduit"
-   dir="end">
-  <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
- </interface>
- <interface
-   name="rx_enh_blk_lock"
-   internal="transceiver_phy_inst.rx_enh_blk_lock"
-   type="conduit"
-   dir="end">
-  <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
- </interface>
- <module
-   kind="altera_xcvr_native_a10"
-   version="14.0"
-   enabled="1"
-   name="transceiver_phy_inst"
-   autoexport="1">
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="device" value="10AX115U3F45I2SGES" />
-  <parameter name="design_environment" value="NATIVE" />
-  <parameter name="message_level" value="error" />
-  <parameter name="support_mode" value="user_mode" />
-  <parameter name="protocol_mode" value="teng_baser_mode" />
-  <parameter name="pma_mode" value="basic" />
-  <parameter name="duplex_mode" value="duplex" />
-  <parameter name="channels" value="48" />
-  <parameter name="set_data_rate" value="10312.5" />
-  <parameter name="rcfg_iface_enable" value="0" />
-  <parameter name="enable_simple_interface" value="1" />
-  <parameter name="enable_split_interface" value="0" />
-  <parameter name="set_enable_calibration" value="0" />
-  <parameter name="enable_transparent_pcs" value="0" />
-  <parameter name="enable_parallel_loopback" value="0" />
-  <parameter name="bonded_mode" value="not_bonded" />
-  <parameter name="set_pcs_bonding_master" value="Auto" />
-  <parameter name="tx_pma_clk_div" value="1" />
-  <parameter name="plls" value="1" />
-  <parameter name="pll_select" value="0" />
-  <parameter name="enable_port_tx_pma_clkout" value="0" />
-  <parameter name="enable_port_tx_pma_div_clkout" value="0" />
-  <parameter name="tx_pma_div_clkout_divider" value="33" />
-  <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
-  <parameter name="enable_port_tx_pma_elecidle" value="0" />
-  <parameter name="enable_port_tx_pma_qpipullup" value="0" />
-  <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
-  <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
-  <parameter name="enable_port_tx_pma_rxfound" value="0" />
-  <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
-  <parameter name="cdr_refclk_cnt" value="1" />
-  <parameter name="cdr_refclk_select" value="0" />
-  <parameter name="set_cdr_refclk_freq" value="644.531250" />
-  <parameter name="rx_ppm_detect_threshold" value="100" />
-  <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
-  <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
-  <parameter name="rx_pma_dfe_fixed_taps" value="3" />
-  <parameter name="enable_rx_pma_floatingtap" value="0" />
-  <parameter name="enable_ports_adaptation" value="0" />
-  <parameter name="enable_port_rx_pma_clkout" value="0" />
-  <parameter name="enable_port_rx_pma_div_clkout" value="0" />
-  <parameter name="rx_pma_div_clkout_divider" value="0" />
-  <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
-  <parameter name="enable_port_rx_pma_clkslip" value="0" />
-  <parameter name="enable_port_rx_pma_qpipullup" value="0" />
-  <parameter name="enable_port_rx_is_lockedtodata" value="1" />
-  <parameter name="enable_port_rx_is_lockedtoref" value="0" />
-  <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
-  <parameter name="enable_ports_rx_manual_ppm" value="0" />
-  <parameter name="enable_port_rx_signaldetect" value="0" />
-  <parameter name="enable_port_rx_seriallpbken" value="0" />
-  <parameter name="enable_ports_rx_prbs" value="0" />
-  <parameter name="std_pcs_pma_width" value="10" />
-  <parameter name="std_low_latency_bypass_enable" value="0" />
-  <parameter name="enable_hip" value="0" />
-  <parameter name="enable_hard_reset" value="0" />
-  <parameter name="set_hip_cal_en" value="0" />
-  <parameter name="std_tx_pcfifo_mode" value="low_latency" />
-  <parameter name="std_rx_pcfifo_mode" value="low_latency" />
-  <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
-  <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
-  <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
-  <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
-  <parameter name="std_tx_byte_ser_mode" value="Disabled" />
-  <parameter name="std_rx_byte_deser_mode" value="Disabled" />
-  <parameter name="std_tx_8b10b_enable" value="1" />
-  <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
-  <parameter name="std_rx_8b10b_enable" value="1" />
-  <parameter name="std_rx_rmfifo_mode" value="disabled" />
-  <parameter name="std_rx_rmfifo_pattern_n" value="0" />
-  <parameter name="std_rx_rmfifo_pattern_p" value="0" />
-  <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
-  <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
-  <parameter name="pcie_rate_match" value="Bypass" />
-  <parameter name="std_tx_bitslip_enable" value="0" />
-  <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
-  <parameter name="std_rx_word_aligner_mode">synchronous state machine</parameter>
-  <parameter name="std_rx_word_aligner_pattern_len" value="7" />
-  <parameter name="std_rx_word_aligner_pattern" value="124" />
-  <parameter name="std_rx_word_aligner_rknumber" value="3" />
-  <parameter name="std_rx_word_aligner_renumber" value="3" />
-  <parameter name="std_rx_word_aligner_rgnumber" value="3" />
-  <parameter name="std_rx_word_aligner_rvnumber" value="0" />
-  <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
-  <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
-  <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
-  <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
-  <parameter name="enable_port_rx_std_bitslip" value="0" />
-  <parameter name="std_tx_bitrev_enable" value="0" />
-  <parameter name="std_tx_byterev_enable" value="0" />
-  <parameter name="std_tx_polinv_enable" value="0" />
-  <parameter name="enable_port_tx_polinv" value="0" />
-  <parameter name="std_rx_bitrev_enable" value="0" />
-  <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
-  <parameter name="std_rx_byterev_enable" value="0" />
-  <parameter name="enable_port_rx_std_byterev_ena" value="0" />
-  <parameter name="std_rx_polinv_enable" value="0" />
-  <parameter name="enable_port_rx_polinv" value="0" />
-  <parameter name="enable_port_rx_std_signaldetect" value="0" />
-  <parameter name="enable_ports_pipe_sw" value="0" />
-  <parameter name="enable_ports_pipe_hclk" value="0" />
-  <parameter name="enable_ports_pipe_g3_analog" value="0" />
-  <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
-  <parameter name="enable_port_pipe_rx_polarity" value="0" />
-  <parameter name="enh_pcs_pma_width" value="32" />
-  <parameter name="enh_pld_pcs_width" value="66" />
-  <parameter name="enh_low_latency_enable" value="0" />
-  <parameter name="enh_rxtxfifo_double_width" value="0" />
-  <parameter name="enh_txfifo_mode" value="Phase compensation" />
-  <parameter name="enh_txfifo_pfull" value="11" />
-  <parameter name="enh_txfifo_pempty" value="2" />
-  <parameter name="enable_port_tx_enh_fifo_full" value="0" />
-  <parameter name="enable_port_tx_enh_fifo_pfull" value="0" />
-  <parameter name="enable_port_tx_enh_fifo_empty" value="0" />
-  <parameter name="enable_port_tx_enh_fifo_pempty" value="0" />
-  <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
-  <parameter name="enh_rxfifo_mode" value="10GBase-R" />
-  <parameter name="enh_rxfifo_pfull" value="23" />
-  <parameter name="enh_rxfifo_pempty" value="2" />
-  <parameter name="enh_rxfifo_align_del" value="0" />
-  <parameter name="enh_rxfifo_control_del" value="0" />
-  <parameter name="enable_port_rx_enh_data_valid" value="1" />
-  <parameter name="enable_port_rx_enh_fifo_full" value="0" />
-  <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
-  <parameter name="enable_port_rx_enh_fifo_empty" value="0" />
-  <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
-  <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
-  <parameter name="enable_port_rx_enh_fifo_del" value="0" />
-  <parameter name="enable_port_rx_enh_fifo_insert" value="0" />
-  <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
-  <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
-  <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
-  <parameter name="enh_tx_frmgen_enable" value="0" />
-  <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
-  <parameter name="enh_tx_frmgen_burst_enable" value="0" />
-  <parameter name="enable_port_tx_enh_frame" value="0" />
-  <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
-  <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
-  <parameter name="enh_rx_frmsync_enable" value="0" />
-  <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
-  <parameter name="enable_port_rx_enh_frame" value="0" />
-  <parameter name="enable_port_rx_enh_frame_lock" value="0" />
-  <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
-  <parameter name="enh_tx_crcgen_enable" value="0" />
-  <parameter name="enh_tx_crcerr_enable" value="0" />
-  <parameter name="enh_rx_crcchk_enable" value="0" />
-  <parameter name="enable_port_rx_enh_crc32_err" value="0" />
-  <parameter name="enable_port_rx_enh_highber" value="0" />
-  <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
-  <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
-  <parameter name="enh_tx_64b66b_enable" value="1" />
-  <parameter name="enh_rx_64b66b_enable" value="1" />
-  <parameter name="enh_tx_sh_err" value="0" />
-  <parameter name="enh_tx_scram_enable" value="1" />
-  <parameter name="enh_tx_scram_seed" value="288230376151711743" />
-  <parameter name="enh_rx_descram_enable" value="1" />
-  <parameter name="enh_tx_dispgen_enable" value="0" />
-  <parameter name="enh_rx_dispchk_enable" value="0" />
-  <parameter name="enh_rx_blksync_enable" value="1" />
-  <parameter name="enable_port_rx_enh_blk_lock" value="1" />
-  <parameter name="enh_tx_bitslip_enable" value="0" />
-  <parameter name="enh_tx_polinv_enable" value="0" />
-  <parameter name="enh_rx_bitslip_enable" value="0" />
-  <parameter name="enh_rx_polinv_enable" value="0" />
-  <parameter name="enable_port_tx_enh_bitslip" value="0" />
-  <parameter name="enable_port_rx_enh_bitslip" value="0" />
-  <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
-  <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
-  <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
-  <parameter name="enh_tx_krfec_burst_err_len" value="1" />
-  <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
-  <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
-  <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
-  <parameter name="pcs_direct_width" value="8" />
-  <parameter name="generate_docs" value="1" />
-  <parameter name="generate_add_hdl_instance_example" value="0" />
-  <parameter name="validation_rule_select" value="" />
-  <parameter name="rcfg_enable" value="0" />
-  <parameter name="rcfg_shared" value="0" />
-  <parameter name="rcfg_jtag_enable" value="0" />
-  <parameter name="set_embedded_debug_enable" value="0" />
-  <parameter name="set_capability_reg_enable" value="0" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="set_csr_soft_logic_enable" value="0" />
-  <parameter name="set_prbs_soft_logic_enable" value="0" />
-  <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
-  <parameter name="rcfg_sv_file_enable" value="0" />
-  <parameter name="rcfg_h_file_enable" value="0" />
-  <parameter name="rcfg_mif_file_enable" value="0" />
-  <parameter name="rcfg_multi_enable" value="0" />
-  <parameter name="rcfg_reduced_files_enable" value="0" />
-  <parameter name="rcfg_profile_cnt" value="2" />
-  <parameter name="rcfg_profile_select" value="1" />
-  <parameter name="rcfg_profile_data0" value="" />
-  <parameter name="rcfg_profile_data1" value="" />
-  <parameter name="rcfg_profile_data2" value="" />
-  <parameter name="rcfg_profile_data3" value="" />
-  <parameter name="rcfg_profile_data4" value="" />
-  <parameter name="rcfg_profile_data5" value="" />
-  <parameter name="rcfg_profile_data6" value="" />
-  <parameter name="rcfg_profile_data7" value="" />
- </module>
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
-</system>
diff --git a/boards/uniboard2/designs/unb2_test/src/ip/transceiver_pll.qsys b/boards/uniboard2/designs/unb2_test/src/ip/transceiver_pll.qsys
deleted file mode 100644
index 178dcd50d049ed26b0da055b7c05aa09a3743736..0000000000000000000000000000000000000000
--- a/boards/uniboard2/designs/unb2_test/src/ip/transceiver_pll.qsys
+++ /dev/null
@@ -1,154 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags="INTERNAL_COMPONENT=true"
-   categories="" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $${FILENAME}
-   {
-   }
-   element transceiver_pll_inst
-   {
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="true" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="pll_powerdown"
-   internal="transceiver_pll_inst.pll_powerdown"
-   type="conduit"
-   dir="end">
-  <port name="pll_powerdown" internal="pll_powerdown" />
- </interface>
- <interface
-   name="pll_refclk0"
-   internal="transceiver_pll_inst.pll_refclk0"
-   type="clock"
-   dir="end">
-  <port name="pll_refclk0" internal="pll_refclk0" />
- </interface>
- <interface
-   name="pll_locked"
-   internal="transceiver_pll_inst.pll_locked"
-   type="conduit"
-   dir="end">
-  <port name="pll_locked" internal="pll_locked" />
- </interface>
- <interface
-   name="pll_cal_busy"
-   internal="transceiver_pll_inst.pll_cal_busy"
-   type="conduit"
-   dir="end">
-  <port name="pll_cal_busy" internal="pll_cal_busy" />
- </interface>
- <interface
-   name="mcgb_rst"
-   internal="transceiver_pll_inst.mcgb_rst"
-   type="conduit"
-   dir="end">
-  <port name="mcgb_rst" internal="mcgb_rst" />
- </interface>
- <interface
-   name="mcgb_serial_clk"
-   internal="transceiver_pll_inst.mcgb_serial_clk"
-   type="hssi_serial_clock"
-   dir="start">
-  <port name="mcgb_serial_clk" internal="mcgb_serial_clk" />
- </interface>
- <module
-   kind="altera_xcvr_atx_pll_a10"
-   version="14.0"
-   enabled="1"
-   name="transceiver_pll_inst"
-   autoexport="1">
-  <parameter name="rcfg_debug" value="0" />
-  <parameter name="enable_pll_reconfig" value="0" />
-  <parameter name="rcfg_jtag_enable" value="0" />
-  <parameter name="set_embedded_debug_enable" value="0" />
-  <parameter name="set_capability_reg_enable" value="0" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="set_csr_soft_logic_enable" value="0" />
-  <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
-  <parameter name="rcfg_sv_file_enable" value="0" />
-  <parameter name="rcfg_h_file_enable" value="0" />
-  <parameter name="rcfg_txt_file_enable" value="0" />
-  <parameter name="rcfg_mif_file_enable" value="0" />
-  <parameter name="rcfg_multi_enable" value="0" />
-  <parameter name="rcfg_profile_cnt" value="2" />
-  <parameter name="rcfg_profile_select" value="1" />
-  <parameter name="rcfg_param_vals1" value="" />
-  <parameter name="rcfg_param_vals2" value="" />
-  <parameter name="generate_docs" value="1" />
-  <parameter name="generate_add_hdl_instance_example" value="0" />
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="device" value="10AX115U3F45I2SGES" />
-  <parameter name="test_mode" value="0" />
-  <parameter name="enable_pld_atx_cal_busy_port" value="1" />
-  <parameter name="enable_debug_ports_parameters" value="0" />
-  <parameter name="support_mode" value="user_mode" />
-  <parameter name="message_level" value="error" />
-  <parameter name="prot_mode" value="Basic" />
-  <parameter name="bw_sel" value="low" />
-  <parameter name="refclk_cnt" value="1" />
-  <parameter name="refclk_index" value="0" />
-  <parameter name="silicon_rev" value="false" />
-  <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
-  <parameter name="enable_8G_path" value="0" />
-  <parameter name="enable_16G_path" value="0" />
-  <parameter name="enable_pcie_clk" value="0" />
-  <parameter name="enable_cascade_out" value="0" />
-  <parameter name="enable_hip_cal_done_port" value="0" />
-  <parameter name="set_hip_cal_en" value="0" />
-  <parameter name="select_manual_config" value="0" />
-  <parameter name="set_output_clock_frequency" value="5156.25" />
-  <parameter name="enable_fractional" value="0" />
-  <parameter name="set_auto_reference_clock_frequency" value="644.53125" />
-  <parameter name="set_manual_reference_clock_frequency" value="100.0" />
-  <parameter name="set_fref_clock_frequency" value="100.0" />
-  <parameter name="set_m_counter" value="1" />
-  <parameter name="set_ref_clk_div" value="1" />
-  <parameter name="set_l_counter" value="2" />
-  <parameter name="set_k_counter" value="1" />
-  <parameter name="enable_mcgb" value="1" />
-  <parameter name="mcgb_div" value="1" />
-  <parameter name="enable_hfreq_clk" value="1" />
-  <parameter name="enable_mcgb_pcie_clksw" value="0" />
-  <parameter name="mcgb_aux_clkin_cnt" value="0" />
-  <parameter name="enable_bonding_clks" value="0" />
-  <parameter name="enable_fb_comp_bonding" value="0" />
-  <parameter name="pma_width" value="64" />
-  <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
-  <parameter name="AUTO_PLL_REFCLK0_CLOCK_RATE" value="-1" />
-  <parameter name="AUTO_PLL_REFCLK1_CLOCK_RATE" value="-1" />
-  <parameter name="AUTO_PLL_REFCLK2_CLOCK_RATE" value="-1" />
-  <parameter name="AUTO_PLL_REFCLK3_CLOCK_RATE" value="-1" />
-  <parameter name="AUTO_PLL_REFCLK4_CLOCK_RATE" value="-1" />
-  <parameter name="AUTO_RECONFIG_CLK0_CLOCK_RATE" value="-1" />
-  <parameter name="AUTO_RECONFIG_CLK1_CLOCK_RATE" value="-1" />
- </module>
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
-</system>
diff --git a/boards/uniboard2/designs/unb2_test/src/ip/transceiver_reset_controller.qsys b/boards/uniboard2/designs/unb2_test/src/ip/transceiver_reset_controller.qsys
deleted file mode 100644
index dc0a29763e51887c2351c6069a3270b39c71a4e2..0000000000000000000000000000000000000000
--- a/boards/uniboard2/designs/unb2_test/src/ip/transceiver_reset_controller.qsys
+++ /dev/null
@@ -1,166 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags="INTERNAL_COMPONENT=true"
-   categories="" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $${FILENAME}
-   {
-   }
-   element transceiver_reset_controller_inst
-   {
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="true" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="clock"
-   internal="transceiver_reset_controller_inst.clock"
-   type="clock"
-   dir="end">
-  <port name="clock" internal="clock" />
- </interface>
- <interface
-   name="reset"
-   internal="transceiver_reset_controller_inst.reset"
-   type="reset"
-   dir="end">
-  <port name="reset" internal="reset" />
- </interface>
- <interface
-   name="pll_powerdown"
-   internal="transceiver_reset_controller_inst.pll_powerdown"
-   type="conduit"
-   dir="end">
-  <port name="pll_powerdown" internal="pll_powerdown" />
- </interface>
- <interface
-   name="tx_analogreset"
-   internal="transceiver_reset_controller_inst.tx_analogreset"
-   type="conduit"
-   dir="end">
-  <port name="tx_analogreset" internal="tx_analogreset" />
- </interface>
- <interface
-   name="tx_digitalreset"
-   internal="transceiver_reset_controller_inst.tx_digitalreset"
-   type="conduit"
-   dir="end">
-  <port name="tx_digitalreset" internal="tx_digitalreset" />
- </interface>
- <interface
-   name="tx_ready"
-   internal="transceiver_reset_controller_inst.tx_ready"
-   type="conduit"
-   dir="end">
-  <port name="tx_ready" internal="tx_ready" />
- </interface>
- <interface
-   name="pll_locked"
-   internal="transceiver_reset_controller_inst.pll_locked"
-   type="conduit"
-   dir="end">
-  <port name="pll_locked" internal="pll_locked" />
- </interface>
- <interface
-   name="pll_select"
-   internal="transceiver_reset_controller_inst.pll_select"
-   type="conduit"
-   dir="end">
-  <port name="pll_select" internal="pll_select" />
- </interface>
- <interface
-   name="tx_cal_busy"
-   internal="transceiver_reset_controller_inst.tx_cal_busy"
-   type="conduit"
-   dir="end">
-  <port name="tx_cal_busy" internal="tx_cal_busy" />
- </interface>
- <interface
-   name="rx_analogreset"
-   internal="transceiver_reset_controller_inst.rx_analogreset"
-   type="conduit"
-   dir="end">
-  <port name="rx_analogreset" internal="rx_analogreset" />
- </interface>
- <interface
-   name="rx_digitalreset"
-   internal="transceiver_reset_controller_inst.rx_digitalreset"
-   type="conduit"
-   dir="end">
-  <port name="rx_digitalreset" internal="rx_digitalreset" />
- </interface>
- <interface
-   name="rx_ready"
-   internal="transceiver_reset_controller_inst.rx_ready"
-   type="conduit"
-   dir="end">
-  <port name="rx_ready" internal="rx_ready" />
- </interface>
- <interface
-   name="rx_is_lockedtodata"
-   internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
-   type="conduit"
-   dir="end">
-  <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
- </interface>
- <interface
-   name="rx_cal_busy"
-   internal="transceiver_reset_controller_inst.rx_cal_busy"
-   type="conduit"
-   dir="end">
-  <port name="rx_cal_busy" internal="rx_cal_busy" />
- </interface>
- <module
-   kind="altera_xcvr_reset_control"
-   version="14.0"
-   enabled="1"
-   name="transceiver_reset_controller_inst"
-   autoexport="1">
-  <parameter name="CHANNELS" value="48" />
-  <parameter name="PLLS" value="1" />
-  <parameter name="SYS_CLK_IN_MHZ" value="200" />
-  <parameter name="SYNCHRONIZE_RESET" value="1" />
-  <parameter name="REDUCED_SIM_TIME" value="1" />
-  <parameter name="gui_split_interfaces" value="0" />
-  <parameter name="TX_PLL_ENABLE" value="1" />
-  <parameter name="T_PLL_POWERDOWN" value="1000" />
-  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
-  <parameter name="TX_ENABLE" value="1" />
-  <parameter name="TX_PER_CHANNEL" value="0" />
-  <parameter name="gui_tx_auto_reset" value="1" />
-  <parameter name="T_TX_DIGITALRESET" value="20" />
-  <parameter name="T_PLL_LOCK_HYST" value="0" />
-  <parameter name="RX_ENABLE" value="1" />
-  <parameter name="RX_PER_CHANNEL" value="0" />
-  <parameter name="gui_rx_auto_reset" value="0" />
-  <parameter name="T_RX_ANALOGRESET" value="40" />
-  <parameter name="T_RX_DIGITALRESET" value="4000" />
-  <parameter name="AUTO_CLOCK_CLOCK_RATE" value="-1" />
- </module>
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
-</system>
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
deleted file mode 100644
index 8a117466c9a80660ed9885bb7a99fedea87f7f90..0000000000000000000000000000000000000000
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ /dev/null
@@ -1,921 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2009
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
-LIBRARY IEEE, common_lib, unb_common_lib, diagnostics_lib, dp_lib, tr_xaui_lib, tr_10GbE_lib, technology_lib, tech_memory_lib;
-use unb_common_lib.unb_common_pkg.all;
-USE IEEE.STD_LOGIC_1164.ALL;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE unb_common_lib.unb_common_pkg.ALL;
---USE tr_xaui_lib.tr_xaui_pkg.ALL;
-USE common_lib.common_interface_layers_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-USE technology_lib.technology_select_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-
-
-ENTITY unb2_test IS
-  port (
-
-    -- GENERAL
-    CLK                    : IN    STD_LOGIC; -- External system clock
-    PPS                    : IN    STD_LOGIC; -- External system sync
-    WDI                    : OUT   STD_LOGIC; -- Watchdog Clear
-    INTA                   : INOUT STD_LOGIC; -- FPGA interconnect line
-    INTB                   : INOUT STD_LOGIC; -- FPGA interconnect line
-
-    -- 1GbE Control Interfaces
-    ETH_CLK                : in std_logic;
-    ETH_SGIN               : in std_logic_vector (1 downto 0);
-    ETH_SGOUT              : out std_logic_vector (1 downto 0);
-
-    -- Transceiver clocks
-    SA_CLK                 : IN    STD_LOGIC; -- SerDes reference clock front 
-    SB_CLK                 : IN    STD_LOGIC; -- SerDes reference clock back
-    BCK_REF_CLK            : IN    STD_LOGIC; -- SerDes reference clock back
-
-    -- SO-DIMM DDR4 Memory Bank i2c (common)
-    MB_SCL                 : inout std_logic;
-    MB_SDA                 : inout std_logic;
-    -- SO-DIMM DDR4 Memory Bank I
-    MB_I_RZQ       : in   STD_LOGIC;
-    MB_I_REF_CLK   : in    STD_LOGIC; -- External reference clock
-    MB_I_A : out std_logic_vector (13 downto 0);
-    MB_I_ACT_N : out std_logic_vector(0 downto 0);
-    MB_I_BA : out std_logic_vector (1 downto 0);
-    MB_I_BG : out std_logic_vector (1 downto 0);
-    MB_I_CAS_A15 : out std_logic;
-    MB_I_CB : inout std_logic_vector (7 downto 0);
-    MB_I_CK : out std_logic_vector (1 downto 0);
-    MB_I_CK_n : out std_logic_vector (1 downto 0);
-    MB_I_CKE : out std_logic_vector (1 downto 0);
-    MB_I_CS : out std_logic_vector (1 downto 0);
-    MB_I_DM : inout std_logic_vector (8 downto 0); -- !! temporarily chg to inout
-    MB_I_DQ : inout std_logic_vector (63 downto 0);
-    MB_I_DQS : inout std_logic_vector (8 downto 0);
-    MB_I_DQS_n : inout std_logic_vector (8 downto 0);
-    MB_I_ODT : out std_logic_vector (1 downto 0);
-    MB_I_PARITY : out std_logic_vector(0 downto 0);
-    MB_I_RAS_A16 : out std_logic;
-    MB_I_WE_A14 : out std_logic;
-    MB_I_RESET_N           : out std_logic_vector(0 downto 0);
-    MB_I_ALERT_N           : in std_logic_vector(0 downto 0);
-    -- SO-DIMM DDR4 Memory Bank II
-    MB_II_RZQ    : in   STD_LOGIC;
-    MB_II_REF_CLK : in    STD_LOGIC; -- External reference clock
-    MB_II_A : out std_logic_vector (13 downto 0);
-    MB_II_ACT_N : out std_logic_vector(0 downto 0);
-    MB_II_BA : out std_logic_vector (1 downto 0);
-    MB_II_BG : out std_logic_vector (1 downto 0);
-    MB_II_CAS_A15 : out std_logic;
-    MB_II_CB : inout std_logic_vector (7 downto 0);
-    MB_II_CK : out std_logic_vector (1 downto 0);
-    MB_II_CK_n : out std_logic_vector (1 downto 0);
-    MB_II_CKE : out std_logic_vector (1 downto 0);
-    MB_II_CS : out std_logic_vector (1 downto 0);
-    MB_II_DM : inout std_logic_vector (8 downto 0); -- !! temporarily chg to inout
-    MB_II_DQ : inout std_logic_vector (63 downto 0);
-    MB_II_DQS : inout std_logic_vector (8 downto 0);
-    MB_II_DQS_n : inout std_logic_vector (8 downto 0);
-    MB_II_ODT : out std_logic_vector (1 downto 0);
-    MB_II_PARITY : out std_logic_vector(0 downto 0);
-    MB_II_RAS_A16 : out std_logic;
-    MB_II_WE_A14 : out std_logic;
-    MB_II_RESET_N          : out std_logic_vector(0 downto 0);
-    MB_II_ALERT_N           : in std_logic_vector(0 downto 0);
-    
-    -- back transceivers
-    BCK_RX : in std_logic_vector (47 downto 0);
-    BCK_TX : out std_logic_vector (47 downto 0);
-    BCK_SDA : inout std_logic_vector (2 downto 0);
-    BCK_SCL : inout std_logic_vector (2 downto 0);
-    BCK_ERR : inout std_logic_vector (2 downto 0);
-    -- ring transceivers
-    RING_0_RX : in std_logic_vector (11 downto 0);
-    RING_0_TX : out std_logic_vector (11 downto 0);
-    RING_1_RX : in std_logic_vector (11 downto 0);
-    RING_1_TX : out std_logic_vector (11 downto 0);
-    -- pmbus
-    PMBUS_SC : inout std_logic;
-    PMBUS_SD : inout std_logic;
-    PMBUS_ALERT : in std_logic;
-    -- front transceivers
-    QSFP_0_RX : in std_logic_vector (3 downto 0);
-    QSFP_0_TX : out std_logic_vector (3 downto 0);
-    QSFP_1_RX : in std_logic_vector (3 downto 0);
-    QSFP_1_TX : out std_logic_vector (3 downto 0);
-    QSFP_2_RX : in std_logic_vector (3 downto 0);
-    QSFP_2_TX : out std_logic_vector (3 downto 0);
-    QSFP_3_RX : in std_logic_vector (3 downto 0);
-    QSFP_3_TX : out std_logic_vector (3 downto 0);
-    QSFP_4_RX : in std_logic_vector (3 downto 0);
-    QSFP_4_TX : out std_logic_vector (3 downto 0);
-    QSFP_5_RX : in std_logic_vector (3 downto 0);
-    QSFP_5_TX : out std_logic_vector (3 downto 0);
-    QSFP_SDA : inout std_logic_vector (5 downto 0);
-    QSFP_SCL : inout std_logic_vector (5 downto 0);
-    QSFP_RST : inout std_logic;
-    -- I2C Interface to Sensors
-    SENS_SC                : inOUT   STD_LOGIC;
-    SENS_SD                : INOUT STD_LOGIC;
-     -- Others
---    CFG_DATA               : inout std_logic_vector (3 downto 0);
-    VERSION                : IN    STD_LOGIC_VECTOR(1 DOWNTO 0);
-    ID                     : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);
-    TESTIO                 : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-  );
-
-end unb2_test;
-
-
-architecture str of unb2_test is
-
-    component ddr4 is
-      port (
-        global_reset_n      : in    std_logic                      := 'X';             -- reset_n
-        pll_ref_clk         : in    std_logic                      := 'X';             -- clk
-        oct_rzqin           : in    std_logic                      := 'X';             -- oct_rzqin
-        mem_ck              : out   std_logic_vector(1 downto 0);                      -- mem_ck
-        mem_ck_n            : out   std_logic_vector(1 downto 0);                      -- mem_ck_n
-        mem_a               : out   std_logic_vector(16 downto 0);                     -- mem_a
-        mem_act_n           : out   std_logic_vector(0 downto 0);                      -- mem_act_n
-        mem_ba              : out   std_logic_vector(1 downto 0);                      -- mem_ba
-        mem_bg              : out   std_logic_vector(1 downto 0);                      -- mem_bg
-        mem_cke             : out   std_logic_vector(1 downto 0);                      -- mem_cke
-        mem_cs_n            : out   std_logic_vector(1 downto 0);                      -- mem_cs_n
-        mem_odt             : out   std_logic_vector(1 downto 0);                      -- mem_odt
-        mem_reset_n         : out   std_logic_vector(0 downto 0);                      -- mem_reset_n
-        mem_alert_n         : in   std_logic_vector(0 downto 0);                       -- mem_alert_n
-        mem_par             : out   std_logic_vector(0 downto 0);                      -- mem_par  ** new in 14.0 **
-        mem_dqs             : inout std_logic_vector(8 downto 0)   := (others => 'X'); -- mem_dqs
-        mem_dqs_n           : inout std_logic_vector(8 downto 0)   := (others => 'X'); -- mem_dqs_n
-        mem_dq              : inout std_logic_vector(71 downto 0)  := (others => 'X'); -- mem_dq
-        mem_dbi_n           : inout std_logic_vector(8 downto 0)   := (others => 'X'); -- mem_dbi_n
-        local_cal_success   : out   std_logic;                                         -- local_cal_success
-        local_cal_fail      : out   std_logic;                                         -- local_cal_fail
-        emif_usr_reset_n    : out   std_logic;                                         -- reset_n
-        emif_usr_clk        : out   std_logic;                                         -- clk
-        amm_ready_0         : out   std_logic;                                         -- waitrequest_n
-        amm_read_0          : in    std_logic                      := 'X';             -- read
-        amm_write_0         : in    std_logic                      := 'X';             -- write
-        amm_address_0       : in    std_logic_vector(26 downto 0)  := (others => 'X'); -- address ** chg from 23 bits in 14.0 **
-        amm_readdata_0      : out   std_logic_vector(575 downto 0);                    -- readdata
-        amm_writedata_0     : in    std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
-        amm_burstcount_0    : in    std_logic_vector(6 downto 0)   := (others => 'X'); -- burstcount ** chg from 8 bits in 14.0 **
-        amm_byteenable_0    : in    std_logic_vector(71 downto 0)  := (others => 'X'); -- byteenable
-        amm_readdatavalid_0 : out   std_logic                                          -- readdatavalid
-      );
-    end component ddr4;
-
-
-   component system_pll is
-     port (
-       refclk    : in  std_logic := 'X'; -- clk
-       rst       : in  std_logic := 'X';
-       locked    : out std_logic;       
-       outclk_0  : out std_logic;        -- outclk0
-       outclk_1  : out std_logic;        -- outclk1
-       outclk_2  : out std_logic         -- outclk2
-     );
-  end component system_pll;
-
-  component unb2_test_qsys is
-    port (
-      clk_clk                          : in    std_logic := 'X'; -- clk
-      reset_reset_n                    : in    std_logic := 'X'; -- reset_n
-      avs_i2c_master_0_gs_sim_export   : in    std_logic := 'X'; -- export
-      avs_i2c_master_0_sync_export     : in    std_logic := 'X'; -- export
-      avs_i2c_master_0_i2c_scl_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_0_i2c_sda_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_1_gs_sim_export   : in    std_logic := 'X'; -- export
-      avs_i2c_master_1_sync_export     : in    std_logic := 'X'; -- export
-      avs_i2c_master_1_i2c_scl_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_1_i2c_sda_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_11_i2c_sda_export : inout std_logic := 'X'; -- export
-      avs_i2c_master_11_i2c_scl_export : inout std_logic := 'X'; -- export
-      avs_i2c_master_11_sync_export    : in    std_logic := 'X'; -- export
-      avs_i2c_master_11_gs_sim_export  : in    std_logic := 'X'; -- export
-      avs_i2c_master_10_i2c_sda_export : inout std_logic := 'X'; -- export
-      avs_i2c_master_10_i2c_scl_export : inout std_logic := 'X'; -- export
-      avs_i2c_master_10_sync_export    : in    std_logic := 'X'; -- export
-      avs_i2c_master_10_gs_sim_export  : in    std_logic := 'X'; -- export
-      avs_i2c_master_9_i2c_sda_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_9_i2c_scl_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_9_sync_export     : in    std_logic := 'X'; -- export
-      avs_i2c_master_9_gs_sim_export   : in    std_logic := 'X'; -- export
-      avs_i2c_master_8_i2c_sda_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_8_sync_export     : in    std_logic := 'X'; -- export
-      avs_i2c_master_8_gs_sim_export   : in    std_logic := 'X'; -- export
-      avs_i2c_master_8_i2c_scl_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_7_i2c_sda_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_7_i2c_scl_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_7_sync_export     : in    std_logic := 'X'; -- export
-      avs_i2c_master_7_gs_sim_export   : in    std_logic := 'X'; -- export
-      avs_i2c_master_6_i2c_sda_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_6_i2c_scl_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_6_sync_export     : in    std_logic := 'X'; -- export
-      avs_i2c_master_6_gs_sim_export   : in    std_logic := 'X'; -- export
-      avs_i2c_master_5_i2c_sda_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_5_i2c_scl_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_5_sync_export     : in    std_logic := 'X'; -- export
-      avs_i2c_master_5_gs_sim_export   : in    std_logic := 'X'; -- export
-      avs_i2c_master_4_i2c_sda_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_4_sync_export     : in    std_logic := 'X'; -- export
-      avs_i2c_master_4_gs_sim_export   : in    std_logic := 'X'; -- export
-      avs_i2c_master_4_i2c_scl_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_3_gs_sim_export   : in    std_logic := 'X'; -- export
-      avs_i2c_master_3_sync_export     : in    std_logic := 'X'; -- export
-      avs_i2c_master_3_i2c_scl_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_3_i2c_sda_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_2_gs_sim_export   : in    std_logic := 'X'; -- export
-      avs_i2c_master_2_sync_export     : in    std_logic := 'X'; -- export
-      avs_i2c_master_2_i2c_scl_export  : inout std_logic := 'X'; -- export
-      avs_i2c_master_2_i2c_sda_export  : inout std_logic := 'X'; -- export
-      eth_tse_0_serial_connection_rxp_0          : in    std_logic := 'X'; -- rxp
-      eth_tse_0_serial_connection_txp_0          : out   std_logic;        -- txp
-      eth_tse_0_pcs_ref_clk_clock_connection_clk : in    std_logic := 'X'; -- clk
-      eth_tse_1_pcs_ref_clk_clock_connection_clk : in    std_logic := 'X'; -- clk
-      eth_tse_1_serial_connection_rxp_0          : in    std_logic := 'X'; -- rxp
-      eth_tse_1_serial_connection_txp_0          : out   std_logic;         -- txp
-      pio_0_external_connection_export           : in    std_logic_vector(10 downto 0) := (others => 'X');  -- export
-
-               reg_mac_front_read_export                  : out   std_logic;                                        -- export
-                reg_mac_front_address_export               : out   std_logic_vector(14 downto 0);                    -- export
-                reg_mac_front_write_export                 : out   std_logic;                                        -- export
-                reg_mac_front_writedata_export             : out   std_logic_vector(31 downto 0);                    -- export
-                reg_mac_front_readdata_export              : in    std_logic_vector(31 downto 0) := (others => 'X'); -- export
-                reg_mac_front_waitrequest_export           : in    std_logic                     := 'X';             -- export
-                reg_mac_back_address_export                : out   std_logic_vector(14 downto 0);                    -- export
-                reg_mac_back_write_export                  : out   std_logic;                                        -- export
-                reg_mac_back_writedata_export              : out   std_logic_vector(31 downto 0);                    -- export
-                reg_mac_back_read_export                   : out   std_logic;                                        -- export
-                reg_mac_back_readdata_export               : in    std_logic_vector(31 downto 0) := (others => 'X'); -- export
-                reg_mac_back_waitrequest_export            : in    std_logic                     := 'X';             -- export
-                reg_hdr_insert_front_readdata_export       : in    std_logic_vector(31 downto 0) := (others => 'X'); -- export
-                reg_hdr_insert_front_read_export           : out   std_logic;                                        -- export
-                reg_hdr_insert_front_writedata_export      : out   std_logic_vector(31 downto 0);                    -- export
-                reg_hdr_insert_front_address_export        : out   std_logic_vector(2 downto 0);                     -- export
-                reg_hdr_insert_front_write_export          : out   std_logic;                                        -- export
-                reg_hdr_insert_back_readdata_export        : in    std_logic_vector(31 downto 0) := (others => 'X'); -- export
-                reg_hdr_insert_back_read_export            : out   std_logic;                                        -- export
-                reg_hdr_insert_back_writedata_export       : out   std_logic_vector(31 downto 0);                    -- export
-                reg_hdr_insert_back_write_export           : out   std_logic;                                        -- export
-                reg_hdr_insert_back_address_export         : out   std_logic_vector(2 downto 0);                     -- export
-                ram_hdr_insert_front_readdata_export       : in    std_logic_vector(31 downto 0) := (others => 'X'); -- export
-                ram_hdr_insert_front_read_export           : out   std_logic;                                        -- export
-                ram_hdr_insert_front_writedata_export      : out   std_logic_vector(31 downto 0);                    -- export
-                ram_hdr_insert_front_write_export          : out   std_logic;                                        -- export
-                ram_hdr_insert_front_address_export        : out   std_logic_vector(5 downto 0);                     -- export
-                ram_hdr_insert_back_address_export         : out   std_logic_vector(5 downto 0);                     -- export
-                ram_hdr_insert_back_write_export           : out   std_logic;                                        -- export
-                ram_hdr_insert_back_writedata_export       : out   std_logic_vector(31 downto 0);                    -- export
-                ram_hdr_insert_back_read_export            : out   std_logic;                                        -- export
-                ram_hdr_remove_front_readdata_export       : in    std_logic_vector(31 downto 0) := (others => 'X'); -- export
-                ram_hdr_remove_front_read_export           : out   std_logic;                                        -- export
-                ram_hdr_remove_front_writedata_export      : out   std_logic_vector(31 downto 0);                    -- export
-                ram_hdr_remove_front_write_export          : out   std_logic;                                        -- export
-                ram_hdr_remove_front_address_export        : out   std_logic_vector(5 downto 0);                     -- export
-                ram_hdr_remove_back_address_export         : out   std_logic_vector(5 downto 0);                     -- export
-                ram_hdr_remove_back_write_export           : out   std_logic;                                        -- export
-                ram_hdr_remove_back_writedata_export       : out   std_logic_vector(31 downto 0);                    -- export
-                ram_hdr_remove_back_read_export            : out   std_logic;                                        -- export
-                ram_hdr_remove_back_readdata_export        : in    std_logic_vector(31 downto 0) := (others => 'X'); -- export
-                reg_diagnostics_front_0_address_export     : out   std_logic_vector(5 downto 0);                     -- export
-                reg_diagnostics_front_0_write_export       : out   std_logic;                                        -- export
-                reg_diagnostics_front_0_writedata_export   : out   std_logic_vector(31 downto 0);                    -- export
-                reg_diagnostics_front_0_read_export        : out   std_logic;                                        -- export
-                reg_diagnostics_front_0_readdata_export    : in    std_logic_vector(31 downto 0) := (others => 'X'); -- export
-                reg_diagnostics_front_1_readdata_export    : in    std_logic_vector(31 downto 0) := (others => 'X'); -- export
-                reg_diagnostics_front_1_read_export        : out   std_logic;                                        -- export
-                reg_diagnostics_front_1_writedata_export   : out   std_logic_vector(31 downto 0);                    -- export
-                reg_diagnostics_front_1_write_export       : out   std_logic;                                        -- export
-                reg_diagnostics_front_1_address_export     : out   std_logic_vector(5 downto 0);                     -- export
-                reg_diagnostics_front_2_readdata_export    : in    std_logic_vector(31 downto 0) := (others => 'X'); -- export
-                reg_diagnostics_front_2_read_export        : out   std_logic;                                        -- export
-                reg_diagnostics_front_2_writedata_export   : out   std_logic_vector(31 downto 0);                    -- export
-                reg_diagnostics_front_2_write_export       : out   std_logic;                                        -- export
-                reg_diagnostics_front_2_address_export     : out   std_logic_vector(5 downto 0);                     -- export
-                reg_diagnostics_back_0_readdata_export     : in    std_logic_vector(31 downto 0) := (others => 'X'); -- export
-                reg_diagnostics_back_0_read_export         : out   std_logic;                                        -- export
-                reg_diagnostics_back_0_writedata_export    : out   std_logic_vector(31 downto 0);                    -- export
-                reg_diagnostics_back_0_write_export        : out   std_logic;                                        -- export
-                reg_diagnostics_back_0_address_export      : out   std_logic_vector(5 downto 0);                     -- export
-                reg_diagnostics_back_1_address_export      : out   std_logic_vector(5 downto 0);                     -- export
-                reg_diagnostics_back_1_write_export        : out   std_logic;                                        -- export
-                reg_diagnostics_back_1_writedata_export    : out   std_logic_vector(31 downto 0);                    -- export
-                reg_diagnostics_back_1_read_export         : out   std_logic;                                        -- export
-                reg_diagnostics_back_1_readdata_export     : in    std_logic_vector(31 downto 0) := (others => 'X'); -- export
-                reg_diagnostics_back_2_address_export      : out   std_logic_vector(5 downto 0);                     -- export
-                reg_diagnostics_back_2_write_export        : out   std_logic;                                        -- export
-                reg_diagnostics_back_2_writedata_export    : out   std_logic_vector(31 downto 0);                    -- export
-                reg_diagnostics_back_2_readdata_export     : in    std_logic_vector(31 downto 0) := (others => 'X'); -- export
-                reg_diagnostics_back_2_read_export         : out   std_logic                                         -- export
-
-   );
-  end component unb2_test_qsys;
-
-    -- constants
-    constant cs_sim                : std_logic := '0';
-    constant cs_sync               : std_logic := '1';
-    --CONSTANT c_block_len            : NATURAL := 180; -- = 1440 user bytes. Including packetizing: 1508 bytes.
-    CONSTANT c_block_len            : NATURAL := 1118;-- = 8944 user bytes. Including packetizing: 9012 bytes.
-    type t_mem_mosi_arr is array (0 to 2) of t_mem_mosi;
-    type t_mem_miso_arr is array (0 to 2) of t_mem_miso;
-
-    -- general reset and clock signals
-    signal reset_n                 : std_logic := '0';
-    signal reset_p                 : std_logic := '0';
-    signal pout_wdi                : std_logic := '0';
-    signal sys_clk                 : std_logic := '0';
-    signal sys_locked              : std_logic := '0';
-    signal mm_clk                  : std_logic := '0';
-    signal clk_125                 : std_logic := '0';
-
-    -- signals for the ddr4 controllers
-    signal local_i_cal_success     : std_logic;
-    signal local_i_cal_fail        : std_logic;
-    signal local_i_reset_n         : std_logic;
-    signal local_i_clk             : std_logic;
-    signal local_i_ready           : std_logic;
-    signal local_i_read            : std_logic;
-    signal local_i_write           : std_logic;
-    signal local_i_address         : std_logic_vector(26 downto 0);
-    signal local_i_readdata        : std_logic_vector(575 downto 0);
-    signal local_i_writedata       : std_logic_vector(575 downto 0);
-    signal local_i_burstcount      : std_logic_vector(6 downto 0);
-    signal local_i_be              : std_logic_vector(71 downto 0);
-    signal local_i_read_data_valid : std_logic;
-    signal mb_i_a_internal         : std_logic_vector(16 downto 0);
-    signal local_ii_cal_success    : std_logic;
-    signal local_ii_cal_fail       : std_logic;
-    signal local_ii_reset_n        : std_logic;
-    signal local_ii_clk            : std_logic;
-    signal local_ii_ready          : std_logic;
-    signal local_ii_read           : std_logic;
-    signal local_ii_write          : std_logic;
-    signal local_ii_address        : std_logic_vector(26 downto 0);
-    signal local_ii_readdata       : std_logic_vector(575 downto 0);
-    signal local_ii_writedata      : std_logic_vector(575 downto 0);
-    signal local_ii_burstcount     : std_logic_vector(6 downto 0);
-    signal local_ii_be             : std_logic_vector(71 downto 0);
-    signal local_ii_read_data_valid: std_logic;
-    signal mb_ii_a_internal        : std_logic_vector(16 downto 0);
-
-    -- signals for the mm buses
-    signal reg_diagnostics_front_mosi    : t_mem_mosi_arr;
-    signal reg_diagnostics_front_miso    : t_mem_miso_arr;
-    signal reg_hdr_insert_front_mosi     : t_mem_mosi;
-    signal ram_hdr_insert_front_mosi     : t_mem_mosi;
-    signal ram_hdr_remove_front_mosi     : t_mem_mosi;
-    signal ram_hdr_remove_front_miso     : t_mem_miso;
-    signal reg_mac_front_mosi            : t_mem_mosi;
-    signal reg_mac_front_miso            : t_mem_miso;
-
-    signal reg_diagnostics_back_mosi     : t_mem_mosi_arr;
-    signal reg_diagnostics_back_miso     : t_mem_miso_arr;
-    signal reg_hdr_insert_back_mosi      : t_mem_mosi;
-    signal ram_hdr_insert_back_mosi      : t_mem_mosi;
-    signal ram_hdr_remove_back_mosi      : t_mem_mosi;
-    signal ram_hdr_remove_back_miso      : t_mem_miso;
-    signal reg_mac_back_mosi             : t_mem_mosi;
-    signal reg_mac_back_miso             : t_mem_miso;
---    signal xaui_rx_arr_dummy             : t_unb_xaui_sl_2arr(47 downto 0) := (others=>"0000");
-    signal xaui_rx_arr_dummy             : t_xaui_arr(47 DOWNTO 0);
-
-    -- signals for the transceivers
-    signal tx_serial_data_front    : std_logic_vector(47 downto 0);
-    signal rx_serial_data_front    : std_logic_vector(47 downto 0);
-    signal diagnostics_front_snk_in_arr   : t_dp_sosi_arr(47 DOWNTO 0);
-    signal diagnostics_front_snk_out_arr  : t_dp_siso_arr(47 DOWNTO 0);
-    signal diagnostics_front_src_out_arr  : t_dp_sosi_arr(47 DOWNTO 0);
-    signal diagnostics_front_src_in_arr   : t_dp_siso_arr(47 DOWNTO 0);
-
-
-    signal tx_serial_data_back    : std_logic_vector(47 downto 0);
-    signal rx_serial_data_back    : std_logic_vector(47 downto 0);
-    signal diagnostics_back_snk_in_arr   : t_dp_sosi_arr(47 DOWNTO 0);
-    signal diagnostics_back_snk_out_arr  : t_dp_siso_arr(47 DOWNTO 0);
-    signal diagnostics_back_src_out_arr  : t_dp_sosi_arr(47 DOWNTO 0);
-    signal diagnostics_back_src_in_arr   : t_dp_siso_arr(47 DOWNTO 0);
-
-    -- signals for the bidirectional and misc ios
-    signal inta_in    : std_logic;
-    signal intb_in    : std_logic;
-    signal testio_in  : std_logic_vector(7 downto 0);
-    signal bck_err_in : std_logic_vector(2 downto 0);
-    signal inta_out   : std_logic;
-    signal intb_out   : std_logic;
-    signal testio_out : std_logic_vector(7 downto 0);
-    signal bck_err_out : std_logic_vector(2 downto 0);
-    signal ver_id_pmbusalert     : std_logic_vector(10 downto 0);
-
-begin
-
-    WDI <= 'Z';
-
-    --  ****** DDR4 memory controllers ******
-
-    mb_i_a <= mb_i_a_internal(13 downto 0);
-    mb_i_we_a14 <= mb_i_a_internal(14);
-    mb_i_cas_a15 <= mb_i_a_internal(15);
-    mb_i_ras_a16 <= mb_i_a_internal(16);
-
-    local_i_proc : process(local_i_clk, local_i_reset_n)
-    begin
-      if local_i_reset_n = '0' then
-        local_i_read <= '0';
-        local_i_write <= '0';
-        local_i_address <= (others => '0');
-        local_i_writedata <= (others => '0');
-        local_i_burstcount <= (others => '0');
-        local_i_be <= (others => '0');
-      else
-        if local_i_clk'event and local_i_clk = '1' then
-          local_i_be <= (others => '1');
-          if local_i_ready = '1' then
-	    local_i_read <= not local_i_read;
-            local_i_write <= local_i_read_data_valid;
-            local_i_address <= local_i_address+1;
-	    if local_i_read_data_valid = '1' then
-              local_i_writedata <= not local_i_readdata;
-	    else
-	      local_i_writedata <= (others => '1');
-            end if;
-          end if;
-	end if;
-      end if;
-    end process;
-
-    u_ddr4_i : ddr4 
-      port map (
-        global_reset_n      => reset_n,
-        pll_ref_clk         => MB_I_REF_CLK,
-        oct_rzqin           => MB_I_RZQ,
-        mem_ck              => mb_i_ck,
-        mem_ck_n            => mb_i_ck_n,
-        mem_a               => mb_i_a_internal,
-        mem_act_n           => mb_i_act_n,
-        mem_ba              => mb_i_ba,
-        mem_bg              => mb_i_bg,
-        mem_cke             => mb_i_cke,
-        mem_cs_n            => mb_i_cs, 
-        mem_odt             => mb_i_odt,
-        mem_reset_n         => mb_i_reset_n,
-        mem_alert_n         => mb_i_alert_n,
-        mem_par             => mb_i_parity,
-        mem_dqs             => mb_i_dqs,
-        mem_dqs_n           => mb_i_dqs_n,
-        mem_dq(63 downto 0) => mb_i_dq,
-        mem_dq(71 downto 64)=> mb_i_cb,
-        mem_dbi_n           => mb_i_dm,
-        local_cal_success   => local_i_cal_success,
-        local_cal_fail      => local_i_cal_fail,
-        emif_usr_reset_n    => local_i_reset_n,
-        emif_usr_clk        => local_i_clk,
-        amm_ready_0         => local_i_ready,
-        amm_read_0          => local_i_read,
-        amm_write_0         => local_i_write,
-        amm_address_0       => local_i_address,
-        amm_readdata_0      => local_i_readdata,
-        amm_writedata_0     => local_i_writedata,
-        amm_burstcount_0    => local_i_burstcount,
-        amm_byteenable_0    => local_i_be,
-        amm_readdatavalid_0 => local_i_read_data_valid
-     );
-
-    mb_ii_a <= mb_ii_a_internal(13 downto 0);
-    mb_ii_we_a14 <= mb_ii_a_internal(14);
-    mb_ii_cas_a15 <= mb_ii_a_internal(15);
-    mb_ii_ras_a16 <= mb_ii_a_internal(16);
-
-    local_ii_proc : process(local_ii_clk, local_ii_reset_n)
-    begin
-      if local_ii_reset_n = '0' then
-        local_ii_read <= '0';
-        local_ii_write <= '0';
-        local_ii_address <= (others => '0');
-        local_ii_writedata <= (others => '0');
-        local_ii_burstcount <= (others => '0');
-        local_ii_be <= (others => '0');
-      else
-        if local_ii_clk'event and local_ii_clk = '1' then
-          local_ii_be <= (others => '1');
-          if local_ii_ready = '1' then
-	    local_ii_read <= not local_ii_read;
-            local_ii_write <= local_ii_read_data_valid;
-            local_ii_address <= local_ii_address+1;
-	    if local_ii_read_data_valid = '1' then
-              local_ii_writedata <= not local_ii_readdata;
-	    else
-	      local_ii_writedata <= (others => '1');
-            end if;
-          end if;
-	end if;
-      end if;
-    end process;
-
-    u_ddr4_ii : ddr4 
-      port map (
-        global_reset_n      => reset_n,
-        pll_ref_clk         => MB_II_REF_CLK,
-        oct_rzqin           => MB_II_RZQ,
-        mem_ck              => mb_ii_ck,
-        mem_ck_n            => mb_ii_ck_n,
-        mem_a               => mb_ii_a_internal,
-        mem_act_n           => mb_ii_act_n,
-        mem_ba              => mb_ii_ba,
-        mem_bg              => mb_ii_bg,
-        mem_cke             => mb_ii_cke,
-        mem_cs_n            => mb_ii_cs, 
-        mem_odt             => mb_ii_odt,
-        mem_reset_n         => mb_ii_reset_n,
-        mem_alert_n         => mb_ii_alert_n,
-        mem_par             => mb_ii_parity,
-        mem_dqs             => mb_ii_dqs,
-        mem_dqs_n           => mb_ii_dqs_n,
-        mem_dq(63 downto 0) => mb_ii_dq,
-        mem_dq(71 downto 64)=> mb_ii_cb,
-        mem_dbi_n           => mb_ii_dm,
-        local_cal_success   => local_ii_cal_success,
-        local_cal_fail      => local_ii_cal_fail,
-        emif_usr_reset_n    => local_ii_reset_n,
-        emif_usr_clk        => local_ii_clk,
-        amm_ready_0         => local_ii_ready,
-        amm_read_0          => local_ii_read,
-        amm_write_0         => local_ii_write,
-        amm_address_0       => local_ii_address,
-        amm_readdata_0      => local_ii_readdata,
-        amm_writedata_0     => local_ii_writedata,
-        amm_burstcount_0    => local_ii_burstcount,
-        amm_byteenable_0    => local_ii_be,
-        amm_readdatavalid_0 => local_ii_read_data_valid
-     );
-
-
---    -- ****** Front side transceivers and diagnostics ******
---
-    RING_0_TX <= tx_serial_data_front(47 downto 36);
-    QSFP_0_TX  <= tx_serial_data_front(35 downto 32);
-    QSFP_1_TX  <= tx_serial_data_front(31 downto 28);
-    QSFP_2_TX  <= tx_serial_data_front(27 downto 24);
-    QSFP_3_TX  <= tx_serial_data_front(23 downto 20);
-    QSFP_4_TX  <= tx_serial_data_front(19 downto 16);
-    QSFP_5_TX  <= tx_serial_data_front(15 downto 12);
-    RING_1_TX <= tx_serial_data_front(11 downto 0);
-    
-    rx_serial_data_front <= RING_0_RX  
-                          & QSFP_0_RX & QSFP_1_RX & QSFP_2_RX & QSFP_3_RX & QSFP_4_RX & QSFP_5_RX
-                          & RING_1_RX ;
-
-    gen_diagnostics_front : for i in 0 to 2 generate
-      mms_diagnostics_front: ENTITY diagnostics_lib.mms_diagnostics
-      GENERIC MAP(
-        g_data_w       => c_xgmii_data_w,
-        g_block_len    => c_block_len,
-        g_nof_streams  => 16,
-        g_separate_clk => FALSE
-      )
-      PORT MAP (
-        mm_rst          => reset_p,
-        mm_clk          => mm_clk,
-        st_rst          => reset_p,
-        st_clk          => mm_clk,
-        mm_mosi         => reg_diagnostics_front_mosi(i),
-        mm_miso         => reg_diagnostics_front_miso(i),
-        src_out_arr     => diagnostics_front_src_out_arr((i+1)*16-1 downto i*16),
-        src_in_arr      => diagnostics_front_src_in_arr((i+1)*16-1 downto i*16),
-        snk_out_arr     => diagnostics_front_snk_out_arr((i+1)*16-1 downto i*16),
-        snk_in_arr      => diagnostics_front_snk_in_arr((i+1)*16-1 downto i*16)
-      );
-    end generate gen_diagnostics_front;
-
-    tr_10GbE_front: ENTITY tr_10GbE_lib.tr_10GbE
-    GENERIC MAP(
-      g_technology    => c_tech_arria10,
-      g_sim           => false,
-      g_sim_level     => 0,
-      g_nof_macs      => 48,
-      g_use_mdio      => false,
-      g_mdio_epcs_dis => false,
-      g_lpbk_sosi     => true,
-      g_lpbk_xgmii    => false,
-      g_lpbk_xaui     => false,
-      g_use_hdr_ram   => true
-    )
-    PORT MAP (
-      -- System
-      mm_rst              => reset_p,
-      mm_clk              => mm_clk,
-      tr_clk              => SA_CLK,
-      cal_rec_clk         => mm_clk,
-      dp_rst              => reset_p,
-      dp_clk              => mm_clk,
-      -- MM registers
-      reg_mac_mosi        => reg_mac_front_mosi,
-      reg_mac_miso        => reg_mac_front_miso,
-      reg_hdr_insert_mosi => reg_hdr_insert_front_mosi,
-      ram_hdr_insert_mosi => ram_hdr_insert_front_mosi,
-      ram_hdr_remove_mosi => ram_hdr_remove_front_mosi,
-      ram_hdr_remove_miso => ram_hdr_remove_front_miso,
-      src_out_arr         => diagnostics_front_snk_in_arr,
-      src_in_arr          => diagnostics_front_snk_out_arr,
-      snk_out_arr         => diagnostics_front_src_in_arr,
-      snk_in_arr          => diagnostics_front_src_out_arr,
-      xaui_tx_out_arr     => open,
-      xaui_rx_in_arr      => xaui_rx_arr_dummy,
-      tx_serial_data      => tx_serial_data_front,
-      rx_serial_data      => rx_serial_data_front,
-      mdio_mdc_arr        => open,
-      mdio_mdat_in_arr    => (others => '0'),
-      mdio_mdat_oen_arr   => open
-    );
-
-
-
-    -- ****** Back side transceivers ******
-
-    BCK_TX <= tx_serial_data_back(47 downto 0);
-    
-    rx_serial_data_back <= BCK_RX;
-
-    gen_diagnostics_back : for i in 0 to 2 generate
-      mms_diagnostics_back : ENTITY diagnostics_lib.mms_diagnostics
-      GENERIC MAP(
-        g_data_w       => c_xgmii_data_w,
-        g_block_len    => c_block_len,
-        g_nof_streams  => 16,
-        g_separate_clk => FALSE
-      )
-      PORT MAP (
-        mm_rst          => reset_p,
-        mm_clk          => mm_clk,
-        st_rst          => reset_p,
-        st_clk          => mm_clk,
-        mm_mosi         => reg_diagnostics_back_mosi(i),
-        mm_miso         => reg_diagnostics_back_miso(i),
-        src_out_arr     => diagnostics_back_src_out_arr((i+1)*16-1 downto i*16),
-        src_in_arr      => diagnostics_back_src_in_arr((i+1)*16-1 downto i*16),
-        snk_out_arr     => diagnostics_back_snk_out_arr((i+1)*16-1 downto i*16),
-        snk_in_arr      => diagnostics_back_snk_in_arr((i+1)*16-1 downto i*16)
-      );
-    end generate gen_diagnostics_back;
-
-    tr_10GbE_back : ENTITY tr_10GbE_lib.tr_10GbE
-    GENERIC MAP(
-      g_technology    => c_tech_arria10,
-      g_sim           => false,
-      g_sim_level     => 0,
-      g_nof_macs      => 48,
-      g_use_mdio      => false,
-      g_mdio_epcs_dis => false,
-      g_lpbk_sosi     => false,
-      g_lpbk_xgmii    => false,
-      g_lpbk_xaui     => false,
-      g_use_hdr_ram   => false
-    )
-    PORT MAP (
-      -- System
-      mm_rst              => reset_p,
-      mm_clk              => mm_clk,
-      tr_clk              => SB_CLK,
-      cal_rec_clk         => mm_clk,
-      dp_rst              => reset_p,
-      dp_clk              => mm_clk,
-      -- MM registers
-      reg_mac_mosi        => reg_mac_back_mosi,
-      reg_mac_miso        => reg_mac_back_miso,
-      reg_hdr_insert_mosi => reg_hdr_insert_back_mosi,
-      ram_hdr_insert_mosi => ram_hdr_insert_back_mosi,
-      ram_hdr_remove_mosi => ram_hdr_remove_back_mosi,
-      ram_hdr_remove_miso => ram_hdr_remove_back_miso,
-      src_out_arr         => diagnostics_back_snk_in_arr,
-      src_in_arr          => diagnostics_back_snk_out_arr,
-      snk_out_arr         => diagnostics_back_src_in_arr,
-      snk_in_arr          => diagnostics_back_src_out_arr,
-      xaui_tx_out_arr     => open,
-      xaui_rx_in_arr      => xaui_rx_arr_dummy,
-      tx_serial_data      => tx_serial_data_back,
-      rx_serial_data      => rx_serial_data_back,
-      mdio_mdc_arr        => open,
-      mdio_mdat_in_arr    => (others => '0'),
-      mdio_mdat_oen_arr   => open
-    );
-
-
-
-    -- ****** node control for resets and wdi
-
-    u_node_ctrl : entity unb_common_lib.unb_node_ctrl
-      generic map (
-        g_pulse_us => c_unb_tse_clk_freq / (10**6)   -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
-      )
-      port map (
-        xo_clk      => ETH_clk,
-        xo_rst_n    => reset_n,
-        sys_clk     => sys_clk,
-        sys_locked  => sys_locked,
-        sys_rst     => open,
-        st_clk      => clk,
-        st_rst      => open,
-        wdi_in      => pout_wdi,
-        wdi_out     => WDI,   -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
-        pulse_us    => open,
-        pulse_ms    => open,
-        pulse_s     => open   -- could be used to toggle a LED
-      );
-
-    reset_p <= not reset_n;
-  
-    u_system_pll : system_pll
-      port map(
-        refclk       => ETH_CLK,
-        rst          => reset_p,
-        locked       => sys_locked,
-        outclk_0     => mm_clk,  -- 100MHz
-        outclk_1     => sys_clk, -- 300MHz
-	outclk_2     => clk_125  -- 125MHz for 1ge
-     );
-
-    -- ****** i2c interfaces ******
-
-    u_qsys : unb2_test_qsys
-      port map (
-        clk_clk                          => mm_clk,
-        reset_reset_n                    => reset_n,
-        avs_i2c_master_0_gs_sim_export   => cs_sim,
-        avs_i2c_master_0_sync_export     => cs_sync,
-        avs_i2c_master_0_i2c_scl_export  => sens_sc,
-        avs_i2c_master_0_i2c_sda_export  => sens_sd,
-        avs_i2c_master_1_gs_sim_export   => cs_sim,
-        avs_i2c_master_1_sync_export     => cs_sync,
-        avs_i2c_master_1_i2c_scl_export  => pmbus_sc,
-        avs_i2c_master_1_i2c_sda_export  => pmbus_sd,
-        avs_i2c_master_2_gs_sim_export   => cs_sim,
-        avs_i2c_master_2_sync_export     => cs_sync,
-        avs_i2c_master_2_i2c_scl_export  => bck_scl(0),
-        avs_i2c_master_2_i2c_sda_export  => bck_sda(0),
-        avs_i2c_master_3_gs_sim_export   => cs_sim,
-        avs_i2c_master_3_sync_export     => cs_sync,
-        avs_i2c_master_3_i2c_scl_export  => bck_scl(1),
-        avs_i2c_master_3_i2c_sda_export  => bck_sda(1),
-        avs_i2c_master_4_sync_export     => cs_sync,
-        avs_i2c_master_4_gs_sim_export   => cs_sim,
-        avs_i2c_master_4_i2c_scl_export  => bck_scl(2),
-        avs_i2c_master_4_i2c_sda_export  => bck_sda(2),
-        avs_i2c_master_5_sync_export     => cs_sync,
-        avs_i2c_master_5_gs_sim_export   => cs_sim,
-        avs_i2c_master_5_i2c_sda_export  => qsfp_sda(0),
-        avs_i2c_master_5_i2c_scl_export  => qsfp_scl(0),
-        avs_i2c_master_6_sync_export     => cs_sync,
-        avs_i2c_master_6_gs_sim_export   => cs_sim,
-        avs_i2c_master_6_i2c_sda_export  => qsfp_sda(1),
-        avs_i2c_master_6_i2c_scl_export  => qsfp_scl(1),
-        avs_i2c_master_7_sync_export     => cs_sync,
-        avs_i2c_master_7_gs_sim_export   => cs_sim,
-        avs_i2c_master_7_i2c_sda_export  => qsfp_sda(2),
-        avs_i2c_master_7_i2c_scl_export  => qsfp_scl(2),
-        avs_i2c_master_8_sync_export     => cs_sync,
-        avs_i2c_master_8_gs_sim_export   => cs_sim,
-        avs_i2c_master_8_i2c_sda_export  => qsfp_sda(3),
-        avs_i2c_master_8_i2c_scl_export  => qsfp_scl(3),
-        avs_i2c_master_9_sync_export     => cs_sync,
-        avs_i2c_master_9_gs_sim_export   => cs_sim,
-        avs_i2c_master_9_i2c_sda_export  => qsfp_sda(4),
-        avs_i2c_master_9_i2c_scl_export  => qsfp_scl(4),
-        avs_i2c_master_10_sync_export    => cs_sync,
-        avs_i2c_master_10_gs_sim_export  => cs_sim,
-        avs_i2c_master_10_i2c_sda_export => qsfp_sda(5),
-        avs_i2c_master_10_i2c_scl_export => qsfp_scl(5),
-        avs_i2c_master_11_sync_export    => cs_sync,
-        avs_i2c_master_11_gs_sim_export  => cs_sim,
-        avs_i2c_master_11_i2c_sda_export => mb_sda,
-        avs_i2c_master_11_i2c_scl_export => mb_scl,
-        eth_tse_0_serial_connection_rxp_0          => ETH_SGIN(0), 
-        eth_tse_0_serial_connection_txp_0          => ETH_SGOUT(0), 
---        eth_tse_0_pcs_ref_clk_clock_connection_clk => clk_125,
-        eth_tse_0_pcs_ref_clk_clock_connection_clk => ETH_CLK,
---        eth_tse_1_pcs_ref_clk_clock_connection_clk => clk_125,
-        eth_tse_1_pcs_ref_clk_clock_connection_clk => ETH_CLK,
-        eth_tse_1_serial_connection_rxp_0          => ETH_SGIN(1),   
-        eth_tse_1_serial_connection_txp_0          => ETH_SGOUT(1),
-        pio_0_external_connection_export           => ver_id_pmbusalert,
-        reg_mac_front_read_export                  => reg_mac_front_mosi.rd,         
-        reg_mac_front_address_export               => reg_mac_front_mosi.address(14 downto 0),     
-        reg_mac_front_write_export                 => reg_mac_front_mosi.wr,      
-        reg_mac_front_writedata_export             => reg_mac_front_mosi.wrdata(31 downto 0), 
-        reg_mac_front_readdata_export              => reg_mac_front_miso.rddata(31 downto 0), 
-        reg_mac_front_waitrequest_export           => reg_mac_front_miso.waitrequest,  
-        reg_mac_back_address_export                => reg_mac_back_mosi.address(14 downto 0),    
-        reg_mac_back_write_export                  => reg_mac_back_mosi.wr,     
-        reg_mac_back_writedata_export              => reg_mac_back_mosi.wrdata(31 downto 0),
-        reg_mac_back_read_export                   => reg_mac_back_mosi.rd,    
-        reg_mac_back_readdata_export               => reg_mac_back_miso.rddata(31 downto 0),          
-        reg_mac_back_waitrequest_export            => reg_mac_back_miso.waitrequest,      
-        reg_hdr_insert_front_readdata_export       => open,
-        reg_hdr_insert_front_read_export           => reg_hdr_insert_front_mosi.rd,   
-        reg_hdr_insert_front_writedata_export      => reg_hdr_insert_front_mosi.wrdata(31 downto 0),   
-        reg_hdr_insert_front_address_export        => reg_hdr_insert_front_mosi.address(2 downto 0),    
-        reg_hdr_insert_front_write_export          => reg_hdr_insert_front_mosi.wr,     
-        reg_hdr_insert_back_readdata_export        => open,  
-        reg_hdr_insert_back_read_export            => reg_hdr_insert_back_mosi.rd,     
-        reg_hdr_insert_back_writedata_export       => reg_hdr_insert_back_mosi.wrdata(31 downto 0),  
-        reg_hdr_insert_back_write_export           => reg_hdr_insert_back_mosi.wr,     
-        reg_hdr_insert_back_address_export         => reg_hdr_insert_back_mosi.address(2 downto 0),  
-        ram_hdr_insert_front_readdata_export       => open,
-        ram_hdr_insert_front_read_export           => ram_hdr_insert_front_mosi.rd,   
-        ram_hdr_insert_front_writedata_export      => ram_hdr_insert_front_mosi.wrdata(31 downto 0),  
-        ram_hdr_insert_front_write_export          => ram_hdr_insert_front_mosi.wr,     
-        ram_hdr_insert_front_address_export        => ram_hdr_insert_front_mosi.address(5 downto 0),   
-        ram_hdr_insert_back_read_export            => ram_hdr_insert_back_mosi.rd,   
-        ram_hdr_insert_back_writedata_export       => ram_hdr_insert_back_mosi.wrdata(31 downto 0),  
-        ram_hdr_insert_back_address_export         => ram_hdr_insert_back_mosi.address(5 downto 0),    
-        ram_hdr_insert_back_write_export           => ram_hdr_insert_back_mosi.wr,      
-
-        ram_hdr_remove_front_readdata_export       => ram_hdr_remove_front_miso.rddata(31 downto 0),    
-        ram_hdr_remove_front_read_export           => ram_hdr_remove_front_mosi.rd,    
-        ram_hdr_remove_front_writedata_export      => ram_hdr_remove_front_mosi.wrdata(31 downto 0), 
-        ram_hdr_remove_front_write_export          => ram_hdr_remove_front_mosi.wr,     
-        ram_hdr_remove_front_address_export        => ram_hdr_remove_front_mosi.address(5 downto 0),   
-        ram_hdr_remove_back_address_export         => ram_hdr_remove_back_mosi.address(5 downto 0),    
-        ram_hdr_remove_back_write_export           => ram_hdr_remove_back_mosi.wr,      
-        ram_hdr_remove_back_writedata_export       => ram_hdr_remove_back_mosi.wrdata(31 downto 0),  
-        ram_hdr_remove_back_read_export            => ram_hdr_remove_back_mosi.rd,       
-        ram_hdr_remove_back_readdata_export        => ram_hdr_remove_back_miso.rddata(31 downto 0),   
-        reg_diagnostics_front_0_address_export     => reg_diagnostics_front_mosi(0).address(5 downto 0),
-        reg_diagnostics_front_0_write_export       => reg_diagnostics_front_mosi(0).wr,  
-        reg_diagnostics_front_0_writedata_export   => reg_diagnostics_front_mosi(0).wrdata(31 downto 0),  
-        reg_diagnostics_front_0_read_export        => reg_diagnostics_front_mosi(0).rd,       
-        reg_diagnostics_front_0_readdata_export    => reg_diagnostics_front_miso(0).rddata(31 downto 0),   
-        reg_diagnostics_front_1_readdata_export    => reg_diagnostics_front_miso(1).rddata(31 downto 0),   
-        reg_diagnostics_front_1_read_export        => reg_diagnostics_front_mosi(1).rd,       
-        reg_diagnostics_front_1_writedata_export   => reg_diagnostics_front_mosi(1).wrdata(31 downto 0),  
-        reg_diagnostics_front_1_write_export       => reg_diagnostics_front_mosi(1).wr,      
-        reg_diagnostics_front_1_address_export     => reg_diagnostics_front_mosi(1).address(5 downto 0),    
-        reg_diagnostics_front_2_readdata_export    => reg_diagnostics_front_miso(2).rddata(31 downto 0),   
-        reg_diagnostics_front_2_read_export        => reg_diagnostics_front_mosi(2).rd,       
-        reg_diagnostics_front_2_writedata_export   => reg_diagnostics_front_mosi(2).wrdata(31 downto 0),  
-        reg_diagnostics_front_2_write_export       => reg_diagnostics_front_mosi(2).wr,      
-        reg_diagnostics_front_2_address_export     => reg_diagnostics_front_mosi(2).address(5 downto 0),    
-        reg_diagnostics_back_0_readdata_export     => reg_diagnostics_back_miso(0).rddata(31 downto 0),    
-        reg_diagnostics_back_0_read_export         => reg_diagnostics_back_mosi(0).rd,        
-        reg_diagnostics_back_0_writedata_export    => reg_diagnostics_back_mosi(0).wrdata(31 downto 0),   
-        reg_diagnostics_back_0_write_export        => reg_diagnostics_back_mosi(0).wr,       
-        reg_diagnostics_back_0_address_export      => reg_diagnostics_back_mosi(0).address(5 downto 0),     
-        reg_diagnostics_back_1_address_export      => reg_diagnostics_back_mosi(1).address(5 downto 0),     
-        reg_diagnostics_back_1_write_export        => reg_diagnostics_back_mosi(1).wr,       
-        reg_diagnostics_back_1_writedata_export    => reg_diagnostics_back_mosi(1).wrdata(31 downto 0),   
-        reg_diagnostics_back_1_read_export         => reg_diagnostics_back_mosi(1).rd,        
-        reg_diagnostics_back_1_readdata_export     => reg_diagnostics_back_miso(1).rddata(31 downto 0),   
-        reg_diagnostics_back_2_address_export      => reg_diagnostics_back_mosi(2).address(5 downto 0),    
-        reg_diagnostics_back_2_write_export        => reg_diagnostics_back_mosi(2).wr,      
-        reg_diagnostics_back_2_writedata_export    => reg_diagnostics_back_mosi(2).wrdata(31 downto 0),  
-        reg_diagnostics_back_2_read_export         => reg_diagnostics_back_mosi(2).rd,       
-        reg_diagnostics_back_2_readdata_export     => reg_diagnostics_back_miso(2).rddata(31 downto 0)   
-    );
-
--- bidirectional and misc
--- use PPS as output enable
-
-    INTA <= inta_out when PPS = '1' else 'Z';
-    INTB <= intb_out when PPS = '1' else 'Z';
-    TESTIO <= testio_out when PPS = '1' else "ZZZZZZZZ";
-    BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
-
-    inta_in <= INTA;
-    intb_in <= INTB;
-    testio_in <= TESTIO;
-    bck_err_in <= BCK_ERR;
-    
-    inta_out <= intb_in;
-    intb_out <= inta_in;
-    testio_out(7 downto 4) <= testio_in(3 downto 0);
-    testio_out(3 downto 0) <= testio_in(7 downto 4);
-    bck_err_out(2) <= bck_err_in(1);
-    bck_err_out(1) <= bck_err_in(0);
-    bck_err_out(0) <= bck_err_in(2);
-
-
-    ver_id_pmbusalert <= version & id & pmbus_alert;
-    
-end str;