diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index b01d947170e13b13af0d4a73d735aa1b045f54e1..d4e7bd32486b7818d46073dbec2abc191660aabe 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -188,6 +188,7 @@ PACKAGE common_pkg IS
   FUNCTION vector_and(slv : STD_LOGIC_VECTOR) RETURN STD_LOGIC;  -- '1' when all slv bits are '1' else '0'
   FUNCTION vector_or( slv : STD_LOGIC_VECTOR) RETURN STD_LOGIC;  -- '0' when all slv bits are '0' else '1'
   FUNCTION vector_xor(slv : STD_LOGIC_VECTOR) RETURN STD_LOGIC;  -- '1' when the slv has an odd number of '1' bits else '0'
+  FUNCTION vector_one_hot(slv : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- Returns slv when it contains one hot bit, else returns 0.
   
   FUNCTION andv(slv : STD_LOGIC_VECTOR) RETURN STD_LOGIC;  -- alias of vector_and
   FUNCTION orv( slv : STD_LOGIC_VECTOR) RETURN STD_LOGIC;  -- alias of vector_or
@@ -666,6 +667,25 @@ PACKAGE BODY common_pkg IS
   BEGIN
     RETURN vector_tree(slv, "XOR");
   END;
+
+  FUNCTION vector_one_hot(slv : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+    VARIABLE v_one_hot : BOOLEAN := FALSE;
+    VARIABLE v_zeros   : STD_LOGIC_VECTOR(slv'RANGE) := (OTHERS=>'0');
+  BEGIN
+    FOR i IN slv'RANGE LOOP
+      IF slv(i) = '1' THEN
+        IF NOT(v_one_hot) THEN
+          -- No hot bits found so far
+          v_one_hot := TRUE;
+        ELSE
+          -- This is the second hot bit found; return zeros.
+          RETURN v_zeros;
+        END IF;
+      END IF;
+    END LOOP;
+    -- No or a single hot bit found in slv; return slv.
+    RETURN slv;
+  END;
   
   FUNCTION andv(slv : STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
   BEGIN