diff --git a/libraries/technology/memory/tech_memory_ram_rw_rw.vhd b/libraries/technology/memory/tech_memory_ram_rw_rw.vhd
index 1bd1363a593b0c2d8b2b62b30fc5ee22be40f2cc..6b692b5e07de8c9a2d77da51807626bbe61b71a2 100644
--- a/libraries/technology/memory/tech_memory_ram_rw_rw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_rw_rw.vhd
@@ -28,7 +28,7 @@
 --   more details please refer the README.txt in the ip_agi027_xxxx/ram/ folder.
 -- Reference:
 --   Copied from tech_memory_ram_crw_crw.vhd and combined two enable entity
---   ports to one and two clock enity ports to one. These changes have been
+--   ports to one and two clock entity ports to one. These changes have been
 --   incorporated into the existing generate-blocks and the generate-block
 --   for agi_xxxx is added.