diff --git a/boards/uniboard1/designs/unb1_test/quartus/sopc_unb1_test.sopc b/boards/uniboard1/designs/unb1_test/quartus/sopc_unb1_test.sopc
index c5e8450eae7511a38dac65d706c9dd5da41d460a..4de0d95d903515fa658f222bbf31f8278636d5ef 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/sopc_unb1_test.sopc
+++ b/boards/uniboard1/designs/unb1_test/quartus/sopc_unb1_test.sopc
@@ -108,11 +108,27 @@
type = "String";
}
}
- element ram_dp_ram_from_mm.mem
+ element reg_dpmm_ctrl.mem
{
datum baseAddress
{
- value = "512";
+ value = "1176";
+ type = "long";
+ }
+ }
+ element reg_diagnostics.mem
+ {
+ datum baseAddress
+ {
+ value = "256";
+ type = "long";
+ }
+ }
+ element reg_remu.mem
+ {
+ datum baseAddress
+ {
+ value = "1024";
type = "long";
}
}
@@ -124,15 +140,15 @@
type = "long";
}
}
- element reg_mmdp_ctrl.mem
+ element reg_mmdp_data.mem
{
datum baseAddress
{
- value = "1192";
+ value = "1200";
type = "long";
}
}
- element rom_system_info.mem
+ element reg_wdi.mem
{
datum _lockedAddress
{
@@ -141,113 +157,105 @@
}
datum baseAddress
{
- value = "4096";
+ value = "12288";
type = "long";
}
}
- element reg_dpmm_data.mem
+ element reg_epcs.mem
{
datum baseAddress
{
- value = "1184";
+ value = "1056";
type = "long";
}
}
- element reg_tr_10GbE.mem
+ element reg_tr_xaui.mem
{
datum baseAddress
{
- value = "32768";
+ value = "16384";
type = "long";
}
}
- element reg_dp_ram_from_mm.mem
+ element reg_dpmm_data.mem
{
datum baseAddress
{
- value = "1088";
+ value = "1184";
type = "long";
}
}
- element reg_wdi.mem
+ element reg_mmdp_ctrl.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "12288";
+ value = "1192";
type = "long";
}
}
- element reg_unb_sens.mem
+ element ram_dp_ram_from_mm.mem
{
datum baseAddress
{
- value = "224";
+ value = "512";
type = "long";
}
}
- element reg_epcs.mem
+ element pio_system_info.mem
{
- datum baseAddress
+ datum _lockedAddress
{
- value = "1056";
- type = "long";
+ value = "1";
+ type = "boolean";
}
- }
- element reg_diagnostics.mem
- {
datum baseAddress
{
- value = "256";
+ value = "0";
type = "long";
}
}
- element reg_dpmm_ctrl.mem
+ element pio_pps.mem
{
datum baseAddress
{
- value = "1176";
+ value = "1208";
type = "long";
}
}
- element reg_mmdp_data.mem
+ element rom_system_info.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "1200";
+ value = "4096";
type = "long";
}
}
- element pio_pps.mem
+ element reg_dp_ram_from_mm.mem
{
datum baseAddress
{
- value = "1208";
+ value = "1088";
type = "long";
}
}
- element reg_remu.mem
+ element reg_tr_10GbE.mem
{
datum baseAddress
{
- value = "1024";
+ value = "262144";
type = "long";
}
}
- element pio_system_info.mem
+ element reg_unb_sens.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "0";
+ value = "224";
type = "long";
}
}
@@ -255,7 +263,7 @@
{
datum baseAddress
{
- value = "16384";
+ value = "24576";
type = "long";
}
}
@@ -426,6 +434,14 @@
type = "int";
}
}
+ element reg_tr_xaui
+ {
+ datum _sortIndex
+ {
+ value = "25";
+ type = "int";
+ }
+ }
element reg_unb_sens
{
datum _sortIndex
@@ -458,11 +474,11 @@
type = "long";
}
}
- element pio_debug_wave.s1
+ element pio_wdi.s1
{
datum baseAddress
{
- value = "1120";
+ value = "1136";
type = "long";
}
}
@@ -479,11 +495,11 @@
type = "long";
}
}
- element pio_wdi.s1
+ element pio_debug_wave.s1
{
datum baseAddress
{
- value = "1136";
+ value = "1120";
type = "long";
}
}
@@ -512,8 +528,8 @@
<parameter name="maxAdditionalLatency" value="0" />
<parameter name="projectName" value="unb1_test.qpf" />
<parameter name="sopcBorderPoints" value="true" />
- <parameter name="systemHash" value="-92179261823" />
- <parameter name="timeStamp" value="1411046983375" />
+ <parameter name="systemHash" value="-97673802020" />
+ <parameter name="timeStamp" value="1412072023928" />
<parameter name="useTestBenchNamingPattern" value="false" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="25000000" />
@@ -614,8 +630,8 @@
<parameter name="dcache_numTCDM" value="_0" />
<parameter name="dcache_lineSize" value="_32" />
<parameter name="dcache_bursts" value="false" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_diagnostics.mem' start='0x100' end='0x200' /><slave name='ram_dp_ram_from_mm.mem' start='0x200' end='0x300' /><slave name='ram_dp_ram_to_mm.mem' start='0x300' end='0x400' /><slave name='reg_remu.mem' start='0x400' end='0x420' /><slave name='reg_epcs.mem' start='0x420' end='0x440' /><slave name='reg_dp_ram_from_mm.mem' start='0x440' end='0x460' /><slave name='pio_debug_wave.s1' start='0x460' end='0x470' /><slave name='pio_wdi.s1' start='0x470' end='0x480' /><slave name='altpll_0.pll_slave' start='0x480' end='0x490' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x490' end='0x498' /><slave name='reg_dpmm_ctrl.mem' start='0x498' end='0x4A0' /><slave name='reg_dpmm_data.mem' start='0x4A0' end='0x4A8' /><slave name='reg_mmdp_ctrl.mem' start='0x4A8' end='0x4B0' /><slave name='reg_mmdp_data.mem' start='0x4B0' end='0x4B8' /><slave name='pio_pps.mem' start='0x4B8' end='0x4C0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='reg_tr_10GbE.mem' start='0x8000' end='0x10000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
- <parameter name="dataAddrWidth" value="18" />
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_diagnostics.mem' start='0x100' end='0x200' /><slave name='ram_dp_ram_from_mm.mem' start='0x200' end='0x300' /><slave name='ram_dp_ram_to_mm.mem' start='0x300' end='0x400' /><slave name='reg_remu.mem' start='0x400' end='0x420' /><slave name='reg_epcs.mem' start='0x420' end='0x440' /><slave name='reg_dp_ram_from_mm.mem' start='0x440' end='0x460' /><slave name='pio_debug_wave.s1' start='0x460' end='0x470' /><slave name='pio_wdi.s1' start='0x470' end='0x480' /><slave name='altpll_0.pll_slave' start='0x480' end='0x490' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x490' end='0x498' /><slave name='reg_dpmm_ctrl.mem' start='0x498' end='0x4A0' /><slave name='reg_dpmm_data.mem' start='0x4A0' end='0x4A8' /><slave name='reg_mmdp_ctrl.mem' start='0x4A8' end='0x4B0' /><slave name='reg_mmdp_data.mem' start='0x4B0' end='0x4B8' /><slave name='pio_pps.mem' start='0x4B8' end='0x4C0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter>
+ <parameter name="dataAddrWidth" value="19" />
<parameter name="customInstSlavesSystemInfo" value="<info/>" />
<parameter name="cpuReset" value="false" />
<parameter name="cpuID" value="0" />
@@ -969,13 +985,22 @@ q]]></parameter>
version="1.0"
enabled="1"
name="reg_tr_10GbE">
- <parameter name="g_adr_w" value="13" />
+ <parameter name="g_adr_w" value="15" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
<module kind="avs2_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
<parameter name="AUTO_MM_CLOCK_RATE" value="125000000" />
</module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="reg_tr_xaui">
+ <parameter name="g_adr_w" value="11" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
<connection
kind="avalon"
version="11.1"
@@ -1267,7 +1292,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_tr_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0x00040000" />
</connection>
<connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" />
<connection
@@ -1292,7 +1317,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="avs_eth_0.mms_ram">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x4000" />
+ <parameter name="baseAddress" value="0x6000" />
</connection>
<connection
kind="interrupt"
@@ -1301,4 +1326,17 @@ q]]></parameter>
end="avs_eth_0.interrupt">
<parameter name="irqNumber" value="2" />
</connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_tr_xaui.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_tr_xaui.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x4000" />
+ </connection>
</system>
diff --git a/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl b/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
index 14269479e73f36b1c577213c4d4438c7d8409b05..1c6ce2162605decc33752830f9a829ef85cdfbe6 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
@@ -23,4 +23,66 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+# -- Front Interface (10GbE)
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/FRONT_NODE_tr_cntrl_pins.tcl
+
+set_location_assignment PIN_AA2 -to SA_CLK
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SA_CLK
+
+set_location_assignment PIN_M4 -to SI_FN_0_TX[0]
+set_location_assignment PIN_K4 -to SI_FN_0_TX[1]
+set_location_assignment PIN_D4 -to SI_FN_0_TX[2]
+set_location_assignment PIN_B4 -to SI_FN_0_TX[3]
+set_location_assignment PIN_N2 -to SI_FN_0_RX[0]
+set_location_assignment PIN_L2 -to SI_FN_0_RX[1]
+set_location_assignment PIN_E2 -to SI_FN_0_RX[2]
+set_location_assignment PIN_C2 -to SI_FN_0_RX[3]
+
+set_location_assignment PIN_AD4 -to SI_FN_1_TX[0]
+set_location_assignment PIN_AB4 -to SI_FN_1_TX[1]
+set_location_assignment PIN_T4 -to SI_FN_1_TX[2]
+set_location_assignment PIN_P4 -to SI_FN_1_TX[3]
+set_location_assignment PIN_AE2 -to SI_FN_1_RX[0]
+set_location_assignment PIN_AC2 -to SI_FN_1_RX[1]
+set_location_assignment PIN_U2 -to SI_FN_1_RX[2]
+set_location_assignment PIN_R2 -to SI_FN_1_RX[3]
+
+set_location_assignment PIN_AT4 -to SI_FN_2_TX[0]
+set_location_assignment PIN_AP4 -to SI_FN_2_TX[1]
+set_location_assignment PIN_AH4 -to SI_FN_2_TX[2]
+set_location_assignment PIN_AF4 -to SI_FN_2_TX[3]
+set_location_assignment PIN_AU2 -to SI_FN_2_RX[0]
+set_location_assignment PIN_AR2 -to SI_FN_2_RX[1]
+set_location_assignment PIN_AJ2 -to SI_FN_2_RX[2]
+set_location_assignment PIN_AG2 -to SI_FN_2_RX[3]
+
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_TX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_TX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_TX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_TX[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_RX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_RX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_RX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_RX[3]
+
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_TX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_TX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_TX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_TX[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_RX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_RX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_RX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_RX[3]
+
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_TX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_TX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_TX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_TX[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[3]
+
+
+
diff --git a/boards/uniboard1/designs/unb1_test/src/hex/default_eth_header.hex b/boards/uniboard1/designs/unb1_test/src/hex/default_eth_header.hex
new file mode 100644
index 0000000000000000000000000000000000000000..80b6a9bc0f5ed11145fe29952712dae007147b61
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_test/src/hex/default_eth_header.hex
@@ -0,0 +1,9 @@
+:0800000000074306C7000022BF
+:0800010086080000080045001C
+:080002002322000040007F11E1
+:08000300BA530A6300010A0A66
+:080004000A0A0FA00FA0230E51
+:080005000000000000000000F3
+:080006000000000000000000F2
+:080007000000000000000000F1
+:00000001FF
diff --git a/boards/uniboard1/designs/unb1_test/src/python/gen_hex_file_dp_ram_from_mm.py b/boards/uniboard1/designs/unb1_test/src/python/gen_hex_file_dp_ram_from_mm.py
new file mode 100644
index 0000000000000000000000000000000000000000..02ccd9781ee56e5af4a82fb915c7d156d3358085
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_test/src/python/gen_hex_file_dp_ram_from_mm.py
@@ -0,0 +1,153 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+from common import *
+from eth import ip_hdr_checksum
+from mem_init_file import list_to_hex
+
+# Purpose:
+# . Generate a HEX file with a default header for the RAM in tr_10GbE.vhd
+# Description:
+# . In unb_tr_10GbE, each diagnostics data block is packetized using the
+# header in the RAM.
+# . The HEX file generated here makes up the initial RAM contents.
+# . The RAM contents can be changed during run-time using
+# $UPE/peripherals/pi_dp_ram_from_mm.py.
+
+###############################################################################
+# Constants
+###############################################################################
+
+FILENAME = "../hex/default_eth_header.hex"
+WORD_WIDTH = 64 # With of the 10GbE MAC's user interface
+NOF_HDR_WORDS = 8 # 512 bits = 64 bytes (c_nof_header_words in tr_10GbE.vhd)
+NOF_PAYLOAD_WORDS = 1118 # c_block_len in node_unb_tr_10GbE.vhd
+NOF_PAYLOAD_BYTES = NOF_PAYLOAD_WORDS * c_word_w / c_byte_w # 8944 bytes
+MEM_WIDTH = WORD_WIDTH
+MEM_DEPTH = NOF_HDR_WORDS
+
+# Header lengths in bytes
+ETH_HDR_LENGTH = 14
+IP_HDR_LENGTH = 20
+UDP_HDR_LENGTH = 8
+USR_HDR_LENGTH = 22
+TOT_HDR_LENGTH = ETH_HDR_LENGTH+IP_HDR_LENGTH+UDP_HDR_LENGTH+USR_HDR_LENGTH
+
+print 'Creating Ethernet header'
+
+###############################################################################
+# Ethernet header
+###############################################################################
+eth_dst_mac = 0x00074306C700 # capture5
+eth_src_mac = 0x002286080000
+eth_type = 0x0800
+
+eth_hdr_bytes = CommonBytes(eth_dst_mac, 6) & \
+ CommonBytes(eth_src_mac, 6) & \
+ CommonBytes(eth_type , 2)
+
+###############################################################################
+# IP header
+###############################################################################
+ip_version = 4
+ip_header_length = 5 # 5 32b words
+ip_services = 0
+ip_total_length = IP_HDR_LENGTH + UDP_HDR_LENGTH + USR_HDR_LENGTH+ \
+ NOF_PAYLOAD_BYTES
+print 'ip_total_length=',ip_total_length
+ip_total_length = 8994
+print 'ip_total_length=',ip_total_length
+
+ip_identification = 0
+ip_flags = 2
+ip_fragment_offset = 0
+ip_time_to_live = 127
+ip_protocol = 17
+ip_header_checksum = 0 # to be calculated
+ip_src_addr = 0x0a630001 # 10.99.0.1
+ip_dst_addr = 0x0a0a0a0a # 10.10.10.10 # capture5
+
+ip_hdr_bits = CommonBits(ip_version , 4) & \
+ CommonBits(ip_header_length , 4) & \
+ CommonBits(ip_services , 8) & \
+ CommonBits(ip_total_length , 16) & \
+ CommonBits(ip_identification , 16) & \
+ CommonBits(ip_flags , 3) & \
+ CommonBits(ip_fragment_offset , 13) & \
+ CommonBits(ip_time_to_live , 8) & \
+ CommonBits(ip_protocol , 8) & \
+ CommonBits(ip_header_checksum , 16) & \
+ CommonBits(ip_src_addr , 32) & \
+ CommonBits(ip_dst_addr , 32)
+
+ip_hdr_bytes = CommonBytes(ip_hdr_bits.data, IP_HDR_LENGTH)
+
+# Calculate and insert the IP header checksum
+calced_checksum = ip_hdr_checksum(ip_hdr_bytes)
+print 'Inserting IP header checksum:', calced_checksum, '=', hex(calced_checksum)
+ip_hdr_bytes[9:8] = calced_checksum
+
+###############################################################################
+# UDP header
+###############################################################################
+#udp_src_port = 0x89AB
+#udp_dst_port = 0xCDEF
+udp_src_port = 4000
+udp_dst_port = 4000
+udp_total_length = USR_HDR_LENGTH + NOF_PAYLOAD_BYTES
+udp_total_length = 8974
+udp_checksum = 0 # Zero is fine
+
+udp_hdr_bytes = CommonBytes(udp_src_port , 2) & \
+ CommonBytes(udp_dst_port , 2) & \
+ CommonBytes(udp_total_length, 2) & \
+ CommonBytes(udp_checksum , 2)
+
+###############################################################################
+# USR header
+###############################################################################
+usr_hdr = 0
+usr_hdr_bytes = CommonBytes(usr_hdr, USR_HDR_LENGTH)
+
+###############################################################################
+# Total header
+###############################################################################
+tot_hdr_bytes = eth_hdr_bytes & ip_hdr_bytes & udp_hdr_bytes & usr_hdr_bytes
+
+###############################################################################
+# Convert header bytes to 64b word list
+# . The LS word of the RAM is released first. We want the MS part of the header
+# to be released into the MAC first, so we must fill the 64b word list in
+# reverse.
+###############################################################################
+tot_hdr_words = CommonWords64(tot_hdr_bytes.data, NOF_HDR_WORDS)
+
+word_list = []
+for w in reversed(range(NOF_HDR_WORDS)):
+ word_list.append(tot_hdr_words[w])
+ print 'w=',w,' data=',hex(tot_hdr_words[w])
+
+###############################################################################
+# Generate the HEX file
+###############################################################################
+print 'Generating hex file:', FILENAME
+list_to_hex(word_list, FILENAME, MEM_WIDTH, MEM_DEPTH)
+print 'Done.'
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 5e86ca21f2e836abb85625f31621d53042f7ad45..b978f9d7692646ef7ff69d607aaa275fbaafc469 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -30,13 +30,15 @@ USE unb1_board_lib.unb1_board_pkg.ALL;
USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
ENTITY mmm_unb1_test IS
GENERIC (
g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0;
- g_sim_node_nr : NATURAL := 0
+ g_sim_node_nr : NATURAL := 0;
+ g_nof_macs : NATURAL
);
PORT (
xo_clk : IN STD_LOGIC;
@@ -110,6 +112,9 @@ ENTITY mmm_unb1_test IS
reg_tr_10GbE_mosi : OUT t_mem_mosi;
reg_tr_10GbE_miso : IN t_mem_miso;
+ reg_tr_xaui_mosi : OUT t_mem_mosi;
+ reg_tr_xaui_miso : IN t_mem_miso;
+
reg_dp_ram_from_mm_mosi : OUT t_mem_mosi;
reg_dp_ram_from_mm_miso : IN t_mem_miso;
@@ -123,33 +128,36 @@ END mmm_unb1_test;
ARCHITECTURE str OF mmm_unb1_test IS
- CONSTANT c_mm_clk_period : TIME := 100 ps;
-
- CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
- CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
-
-- 10GbE MAC / XAUI related
- -- FIXME: these 2 lines are copied from unb1_tr_10GbE.vhd:
- CONSTANT c_nof_macs : NATURAL := 1;
CONSTANT c_nof_mdio : NATURAL := 4;
- CONSTANT nof_bf_units : NATURAL := 1;
- -- 10GbE related:
CONSTANT c_mac_mm_addr_w : NATURAL := 13;
- CONSTANT c_reg_tr_10GbE_addr_w : NATURAL := ceil_log2(c_nof_macs* pow2(c_mac_mm_addr_w));
- CONSTANT c_dp_reg_mm_nof_words : NATURAL := 1;
- CONSTANT c_dp_reg_mm_adr_w : NATURAL := 3; --ceil_log2(nof_bf_units * pow2(ceil_log2(c_dp_reg_mm_nof_words)));
+ CONSTANT c_reg_tr_10GbE_addr_w : NATURAL := ceil_log2(g_nof_macs* pow2(c_mac_mm_addr_w));
- --CONSTANT c_hdr_nof_words : NATURAL := c_eth_total_header_nof_words;
- CONSTANT c_hdr_nof_words : NATURAL := (c_network_total_header_len + c_network_total_header_32b_align_len)/4;
+ CONSTANT c_xaui_mosi_addr_w : NATURAL := 9; --2^9 = range of 512 addresses
+ CONSTANT c_max_nof_xaui_inst : NATURAL := 4;
+ CONSTANT c_reg_tr_xaui_addr_w : NATURAL := ceil_log2(c_max_nof_xaui_inst * pow2(c_xaui_mosi_addr_w)); -- 4* 512 = 2048 addresses -> 11 address bits.
- --CONSTANT c_dp_ram_mm_nof_words : NATURAL := c_hdr_nof_words * (c_tse_data_w/c_word_w);
- CONSTANT c_dp_ram_mm_nof_words : NATURAL := c_hdr_nof_words * (c_word_w/c_word_w);
+ CONSTANT c_dp_ram_mm_adr_w : NATURAL := ceil_log2(c_eth_nof_udp_ports * pow2(ceil_log2(c_network_total_header_32b_nof_words)));
- CONSTANT c_dp_ram_mm_adr_w : NATURAL := 6; --ceil_log2(nof_bf_units * c_dp_ram_mm_nof_words);
+ CONSTANT c_dp_reg_mm_nof_words : NATURAL := 1;
+ CONSTANT c_dp_reg_mm_adr_w : NATURAL := ceil_log2(c_eth_nof_udp_ports * pow2(ceil_log2(c_dp_reg_mm_nof_words)));
+ CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
+ CONSTANT c_cal_rec_clk_period : TIME := 25 ns; -- 40 MHz
+ CONSTANT c_dp_clk_period : TIME := 5 ns; -- 200 MHz
+ CONSTANT c_tse_clk_period : TIME := 8 ns; -- 125 MHz
+ CONSTANT c_epcs_clk_period : TIME := 50 ns; -- 20 MHz
- SIGNAL i_mm_clk : STD_LOGIC := '1';
+ CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
+ CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
+
+
+ SIGNAL i_mm_clk : STD_LOGIC := '1';
+ SIGNAL i_cal_rec_clk : STD_LOGIC := '1';
+ SIGNAL i_dp_clk : STD_LOGIC := '1';
+ SIGNAL i_eth1g_tse_clk : STD_LOGIC := '1';
+ SIGNAL i_epcs_clk : STD_LOGIC := '1';
----------------------------------------------------------------------------
-- mm_file component
@@ -171,15 +179,24 @@ ARCHITECTURE str OF mmm_unb1_test IS
BEGIN
- mm_clk <= i_mm_clk;
+ mm_clk <= i_mm_clk;
+ cal_rec_clk <= i_cal_rec_clk;
+ dp_clk <= i_dp_clk;
+ eth1g_tse_clk <= i_eth1g_tse_clk;
+ epcs_clk <= i_epcs_clk;
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
- i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;
- mm_locked <= '0', '1' AFTER c_mm_clk_period*5;
+ i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;
+ mm_locked <= '0', '1' AFTER c_mm_clk_period*5;
+ i_cal_rec_clk <= NOT i_cal_rec_clk AFTER c_cal_rec_clk_period/2;
+ i_dp_clk <= NOT i_dp_clk AFTER c_dp_clk_period/2;
+ i_eth1g_tse_clk <= NOT i_eth1g_tse_clk AFTER c_tse_clk_period/2;
+ i_epcs_clk <= NOT i_epcs_clk AFTER c_epcs_clk_period/2;
+
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
PORT MAP(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -196,10 +213,23 @@ BEGIN
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
PORT MAP(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_diagnostics : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
+ PORT MAP(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
+
+ u_mm_file_reg_dp_ram_from_mm : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_RAM_FROM_MM")
+ PORT MAP(mm_rst, i_mm_clk, reg_dp_ram_from_mm_mosi, reg_dp_ram_from_mm_miso );
+
+ u_mm_file_ram_dp_ram_from_mm : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DP_RAM_FROM_MM")
+ PORT MAP(mm_rst, i_mm_clk, ram_dp_ram_from_mm_mosi, ram_dp_ram_from_mm_miso );
+
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_tr_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE", c_mm_clk_period, FALSE, 0)
+ PORT MAP(mm_rst, i_mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso );
+
+
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -217,10 +247,10 @@ BEGIN
clk_0 => xo_clk,
reset_n => xo_rst_n,
mm_clk => i_mm_clk,
- cal_reconf_clk => cal_rec_clk,
- tse_clk => eth1g_tse_clk,
- epcs_clk => epcs_clk,
- dp_clk => dp_clk,
+ cal_reconf_clk => i_cal_rec_clk,
+ tse_clk => i_eth1g_tse_clk,
+ epcs_clk => i_epcs_clk,
+ dp_clk => i_dp_clk,
-- the_altpll_0
locked_from_the_altpll_0 => mm_locked,
@@ -397,7 +427,17 @@ BEGIN
coe_read_export_from_the_ram_dp_ram_to_mm => ram_dp_ram_to_mm_mosi.rd,
coe_readdata_export_to_the_ram_dp_ram_to_mm => ram_dp_ram_to_mm_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_dp_ram_to_mm => ram_dp_ram_to_mm_mosi.wr,
- coe_writedata_export_from_the_ram_dp_ram_to_mm => ram_dp_ram_to_mm_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ coe_writedata_export_from_the_ram_dp_ram_to_mm => ram_dp_ram_to_mm_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_tr_xaui
+ coe_clk_export_from_the_reg_tr_xaui => OPEN,
+ coe_reset_export_from_the_reg_tr_xaui => OPEN,
+ coe_address_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.address(c_reg_tr_xaui_addr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_waitrequest_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.waitrequest,
+ coe_write_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index a081ee367ac8b8c3f3edea52a69c563dfffa1de6..1527af627f17d9b11de004bc63fd91a819713dd3 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb1_board_lib, remu_lib, epcs_lib, dp_lib, eth_lib, tr_xaui_lib, tr_10GbE_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, remu_lib, epcs_lib, dp_lib, eth_lib, diagnostics_lib, tr_xaui_lib, tr_10GbE_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -41,7 +41,7 @@ ENTITY unb1_test IS
);
PORT (
-- GENERAL
- CLK : IN STD_LOGIC; -- System Clock
+ --CLK : IN STD_LOGIC; -- System Clock - not used as the SOPC generates dp_clk.
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
@@ -78,7 +78,16 @@ ENTITY unb1_test IS
SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
- SI_FN_RSTN : OUT STD_LOGIC := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ SI_FN_RSTN : OUT STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+
+ BN_BI_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0)
);
END unb1_test;
@@ -89,8 +98,11 @@ ARCHITECTURE str OF unb1_test IS
-- Firmware version x.y
CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 1);
- CONSTANT c_use_front : BOOLEAN := c_design_name(1 TO 2)="fn"; -- FIXME
- CONSTANT c_use_back : BOOLEAN := c_design_name(1 TO 2)="bn"; -- FIXME
+ CONSTANT c_use_front : BOOLEAN := TRUE; --c_design_name(1 TO 2)="fn"; -- FIXME
+ CONSTANT c_use_back : BOOLEAN := FALSE; --c_design_name(1 TO 2)="bn"; -- FIXME
+ CONSTANT c_use_pc_target : BOOLEAN := TRUE;
+
+ CONSTANT c_nof_macs : NATURAL := 3;
-- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim
CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(g_sim, 0, 1),
@@ -108,8 +120,8 @@ ARCHITECTURE str OF unb1_test IS
SIGNAL mm_locked : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC;
- SIGNAL st_rst : STD_LOGIC;
- SIGNAL st_clk : STD_LOGIC;
+ --SIGNAL st_rst : STD_LOGIC;
+ --SIGNAL st_clk : STD_LOGIC;
SIGNAL epcs_clk : STD_LOGIC;
SIGNAL cal_rec_clk : STD_LOGIC;
@@ -170,33 +182,40 @@ ARCHITECTURE str OF unb1_test IS
SIGNAL reg_remu_miso : t_mem_miso;
-- 10GbE
- CONSTANT c_nof_10GbE_offload_streams : NATURAL := 1;
-
- SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
- SIGNAL xaui_rx_arr : t_xaui_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
- SIGNAL unb_xaui_tx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
- SIGNAL unb_xaui_rx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
- SIGNAL mdio_mdc_arr : STD_LOGIC_VECTOR(c_nof_10GbE_offload_streams-1 DOWNTO 0);
- SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_10GbE_offload_streams-1 DOWNTO 0);
- SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_10GbE_offload_streams-1 DOWNTO 0);
+ SIGNAL xaui_tx_arr : t_unb1_board_xaui_sl_2arr(c_nof_macs-1 DOWNTO 0);
+ SIGNAL xaui_rx_arr : t_unb1_board_xaui_sl_2arr(c_nof_macs-1 DOWNTO 0);
+ SIGNAL i_xaui_tx_arr : t_xaui_arr(c_nof_macs-1 DOWNTO 0);
+ SIGNAL i_xaui_rx_arr : t_xaui_arr(c_nof_macs-1 DOWNTO 0);
- SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
- SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdc_arr : STD_LOGIC_VECTOR(c_nof_macs-1 DOWNTO 0);
+ SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_macs-1 DOWNTO 0);
+ SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_macs-1 DOWNTO 0);
- -- . tr_nonbonded with diagnostics
- SIGNAL reg_diagnostics_mosi : t_mem_mosi := c_mem_mosi_rst;
+ -- Diagnostics
+ SIGNAL reg_diagnostics_mosi : t_mem_mosi;
SIGNAL reg_diagnostics_miso : t_mem_miso;
SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_miso : t_mem_miso;
+
+ SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
+ SIGNAL reg_tr_xaui_miso : t_mem_miso;
+
SIGNAL reg_dp_ram_from_mm_mosi : t_mem_mosi;
- SIGNAL reg_dp_ram_from_mm_miso : t_mem_miso;
+ SIGNAL reg_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL ram_dp_ram_from_mm_mosi : t_mem_mosi;
- SIGNAL ram_dp_ram_from_mm_miso : t_mem_miso;
+ SIGNAL ram_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL ram_dp_ram_to_mm_mosi : t_mem_mosi;
SIGNAL ram_dp_ram_to_mm_miso : t_mem_miso;
+
+ CONSTANT c_block_len : NATURAL := 1118;-- = 8944 user bytes. Including packetizing: 9012 bytes.
+ SIGNAL diagnostics_snk_in_arr : t_dp_sosi_arr(c_nof_macs-1 DOWNTO 0);
+ SIGNAL diagnostics_snk_out_arr : t_dp_siso_arr(c_nof_macs-1 DOWNTO 0);
+
+ SIGNAL diagnostics_src_out_arr : t_dp_sosi_arr(c_nof_macs-1 DOWNTO 0);
+ SIGNAL diagnostics_src_in_arr : t_dp_siso_arr(c_nof_macs-1 DOWNTO 0);
BEGIN
-----------------------------------------------------------------------------
@@ -212,7 +231,8 @@ BEGIN
g_fw_version => c_fw_version,
g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux
+ g_aux => c_unb1_board_aux,
+ g_dp_clk_use_pll => FALSE
)
PORT MAP (
-- Clock and reset signals
@@ -227,11 +247,11 @@ BEGIN
epcs_clk => epcs_clk,
- dp_rst => st_rst,
- dp_clk => st_clk,
+ dp_rst => dp_rst,
+ dp_clk => OPEN,
dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
-- PIOs
-- Toggle WDI
@@ -270,7 +290,7 @@ BEGIN
-- FPGA pins
-- . General
- CLK => CLK,
+ CLK => '0', -- SOPC-generated 200MHz dp_clk is used.
PPS => PPS,
WDI => WDI,
INTA => INTA,
@@ -295,7 +315,8 @@ BEGIN
GENERIC MAP (
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
+ g_sim_node_nr => g_sim_node_nr,
+ g_nof_macs => c_nof_macs
)
PORT MAP(
xo_clk => xo_clk,
@@ -370,6 +391,9 @@ BEGIN
reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
reg_tr_10GbE_miso => reg_tr_10GbE_miso,
+ reg_tr_xaui_mosi => reg_tr_xaui_mosi ,
+ reg_tr_xaui_miso => reg_tr_xaui_miso ,
+
reg_dp_ram_from_mm_mosi => reg_dp_ram_from_mm_mosi,
reg_dp_ram_from_mm_miso => reg_dp_ram_from_mm_miso,
@@ -421,15 +445,53 @@ BEGIN
mmdp_data_miso => reg_mmdp_data_miso
);
+ -----------------------------------------------------------------------------
+ -- diagnostics
+ -----------------------------------------------------------------------------
+ u_mms_diagnostics: ENTITY diagnostics_lib.mms_diagnostics
+ GENERIC MAP(
+ g_data_w => c_xgmii_data_w,
+ g_block_len => c_block_len,
+ g_nof_streams => c_nof_macs,
+ g_separate_clk => FALSE
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ mm_mosi => reg_diagnostics_mosi,
+ mm_miso => reg_diagnostics_miso,
+
+ src_out_arr => diagnostics_src_out_arr,
+ src_in_arr => diagnostics_src_in_arr,
+
+ snk_out_arr => diagnostics_snk_out_arr,
+ snk_in_arr => diagnostics_snk_in_arr
+ );
+
-----------------------------------------------------------------------------
-- tr_10GbE
-----------------------------------------------------------------------------
+ -- Wire together different types
+ gen_wires: FOR i IN 0 TO c_nof_macs-1 GENERATE
+ xaui_tx_arr(i) <= i_xaui_tx_arr(i);
+ i_xaui_rx_arr(i) <= xaui_rx_arr(i);
+ END GENERATE;
+
u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
GENERIC MAP (
- g_sim => g_sim,
+ g_sim => FALSE,
g_sim_level => 0,
- g_nof_macs => c_nof_10GbE_offload_streams,
- g_use_mdio => TRUE
+ g_nof_macs => c_nof_macs,
+ g_use_mdio => c_use_front,
+ g_mdio_epcs_dis => c_use_pc_target,
+ g_use_hdr_ram => TRUE,
+ g_hdr_ram_init_file => "../../../src/hex/default_eth_header.hex",
+ g_hdr_release_at_init => '1', --Release default header at init so packets are sent after powerup without manual settings
+ g_pkt_len => 1130 -- 1130 64b words = 9040B (enough for jumbo frame)
)
PORT MAP (
mm_rst => mm_rst,
@@ -442,38 +504,49 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
- snk_out_arr => dp_offload_tx_src_in_arr,
- snk_in_arr => dp_offload_tx_src_out_arr,
+ -- MM registers
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
- reg_mac_mosi => reg_tr_10GbE_mosi,
- reg_mac_miso => reg_tr_10GbE_miso,
+ xaui_mosi => reg_tr_xaui_mosi,
+ xaui_miso => reg_tr_xaui_miso,
- xaui_tx_out_arr => xaui_tx_arr,
- xaui_rx_in_arr => xaui_rx_arr,
+ reg_hdr_insert_mosi => reg_dp_ram_from_mm_mosi,
+ ram_hdr_insert_mosi => ram_dp_ram_from_mm_mosi,
- --mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
- --mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
+ ram_hdr_remove_mosi => ram_dp_ram_to_mm_mosi,
+ ram_hdr_remove_miso => ram_dp_ram_to_mm_miso,
- mdio_rst => SI_FN_RSTN,
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr
- );
+ src_out_arr => diagnostics_snk_in_arr,
+ src_in_arr => diagnostics_snk_out_arr,
- -- Wire together different types
- gen_wires: FOR i IN 0 TO c_nof_10GbE_offload_streams-1 GENERATE
- unb_xaui_tx_arr(i) <= xaui_tx_arr(i);
- xaui_rx_arr(i) <= unb_xaui_rx_arr(i);
- END GENERATE;
+ snk_out_arr => diagnostics_src_in_arr,
+ snk_in_arr => diagnostics_src_out_arr,
+
+ -- Transceiver serial I/O
+ xaui_tx_out_arr => i_xaui_tx_arr,
+ xaui_rx_in_arr => i_xaui_rx_arr,
+
+ -- Serial IO for Arria
+ tx_serial_data => OPEN,
+ rx_serial_data => (OTHERS => '0'),
+
+ -- MDIO External clock and serial data.
+ mdio_rst => SI_FN_RSTN,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
+ );
+ gen_tr_front : IF c_use_front=TRUE GENERATE
u_front_io : ENTITY unb1_board_lib.unb1_board_front_io
GENERIC MAP (
- g_nof_xaui => c_nof_10GbE_offload_streams
+ g_nof_xaui => c_nof_macs
)
PORT MAP (
- xaui_tx_arr => unb_xaui_tx_arr,
- xaui_rx_arr => unb_xaui_rx_arr,
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
mdio_mdc_arr => mdio_mdc_arr,
mdio_mdat_in_arr => mdio_mdat_in_arr,
@@ -492,6 +565,7 @@ BEGIN
SI_FN_2_CNTRL => SI_FN_2_CNTRL,
SI_FN_3_CNTRL => SI_FN_3_CNTRL
);
+ END GENERATE;
-----------------------------------------------------------------------------
-- Node function
diff --git a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
index 573a6079895ca7ef706fb236e21e1974e26b1a85..fd3a9bcf4756f1fd6f5e240575dded80fec13aa5 100644
--- a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
@@ -148,7 +148,7 @@ BEGIN
)
PORT MAP (
-- GENERAL
- CLK => clk,
+ --CLK => clk,
PPS => pps,
WDI => WDI,
INTA => INTA,
@@ -179,8 +179,16 @@ BEGIN
SI_FN_2_TX => OPEN,
SI_FN_2_RX => (OTHERS=>'0'),
SI_FN_3_TX => OPEN,
- SI_FN_3_RX => (OTHERS=>'0')
-
+ SI_FN_3_RX => (OTHERS=>'0'),
+
+ BN_BI_0_TX => OPEN,
+ BN_BI_0_RX => (OTHERS=>'0'),
+ BN_BI_1_TX => OPEN,
+ BN_BI_1_RX => (OTHERS=>'0'),
+ BN_BI_2_TX => OPEN,
+ BN_BI_2_RX => (OTHERS=>'0'),
+ BN_BI_3_TX => OPEN,
+ BN_BI_3_RX => (OTHERS=>'0')
);
------------------------------------------------------------------------------