diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 74a150e78b3b1876fdf0ad8c23d5de54c90c067f..fe1ab80735950c2d1a3d70f8333a09133e28a974 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -32,6 +32,7 @@ synth_files =
$UNB/Firmware/modules/dp/src/vhdl/dp_fifo_fill.vhd
src/vhdl/dp_fifo_fill_core.vhd
src/vhdl/dp_fifo_fill_sc.vhd
+ src/vhdl/dp_fifo_fill_dc.vhd
$UNB/Firmware/modules/dp/src/vhdl/dp_fifo_dc.vhd
$UNB/Firmware/modules/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
$UNB/Firmware/modules/dp/src/vhdl/dp_fifo_to_mm.vhd
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b16f3ba2f095e5395ae96964d8a470d1c8dc9629
--- /dev/null
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
@@ -0,0 +1,110 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Purpose: The FIFO output is available until the next eop only after it has
+-- been filled with more than g_fifo_fill words.
+-- Description: See dp_fifo_fill_core.vhd.
+
+LIBRARY IEEE,common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+ENTITY dp_fifo_fill_dc IS
+ GENERIC (
+ g_data_w : NATURAL := 16;
+ g_bsn_w : NATURAL := 1;
+ g_empty_w : NATURAL := 1;
+ g_channel_w : NATURAL := 1;
+ g_error_w : NATURAL := 1;
+ g_use_bsn : BOOLEAN := FALSE;
+ g_use_empty : BOOLEAN := FALSE;
+ g_use_channel : BOOLEAN := FALSE;
+ g_use_error : BOOLEAN := FALSE;
+ g_use_sync : BOOLEAN := FALSE;
+ g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_fill : NATURAL := 0;
+ g_fifo_size : NATURAL := 256; -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_af_margin : NATURAL := 4; -- Nof words below max (full) at which fifo is considered almost full
+ g_fifo_rl : NATURAL := 1 -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ );
+ PORT (
+ wr_rst : IN STD_LOGIC;
+ wr_clk : IN STD_LOGIC;
+ rd_rst : IN STD_LOGIC;
+ rd_clk : IN STD_LOGIC;
+ -- Monitor FIFO filling
+ wr_ful : OUT STD_LOGIC; -- corresponds to the carry bit of wr_usedw when FIFO is full
+ wr_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2))-1 DOWNTO 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ rd_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2))-1 DOWNTO 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ rd_emp : OUT STD_LOGIC;
+ -- ST sink
+ snk_out : OUT t_dp_siso;
+ snk_in : IN t_dp_sosi;
+ -- ST source
+ src_in : IN t_dp_siso;
+ src_out : OUT t_dp_sosi
+ );
+END dp_fifo_fill_dc;
+
+
+ARCHITECTURE str OF dp_fifo_fill_dc IS
+BEGIN
+
+ u_dp_fifo_fill_core : ENTITY work.dp_fifo_fill_core
+ GENERIC MAP (
+ g_use_dual_clock => TRUE,
+ g_data_w => g_data_w,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_rl => g_fifo_rl
+ )
+ PORT MAP (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
+
+END str;