diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 9eac3c77087aa5177c70be38a59b5cf6b16f659a..fcfe63d670a3d26e43c144b7e4d60858f8ad8536 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -309,6 +309,7 @@ BEGIN
dvr_mosi => dvr_mosi,
dvr_miso => dvr_miso,
wr_sosi => wr_sosi,
+ wr_siso => c_dp_siso_rdy,
wr_fifo_usedw => wr_fifo_usedw,
rd_fifo_usedw => rd_fifo_usedw,
ctlr_wr_flush_en => ctlr_wr_flush_en,
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
index b46dd29e2790e3b1d4546050c82b2d1257864ee6..1cd44510b73c343c7f838fc1224a009a36618035 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
@@ -2302,7 +2302,7 @@
<ipxact:parameter parameterId="dataSlaveMapParam" type="string">
<ipxact:name>dataSlaveMapParam</ipxact:name>
<ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_eth1g_I_bsn_monitor_v2_rx.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_eth1g_I_strobe_total_count_rx.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='avs2_eth_coe_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs2_eth_coe_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_eth1g_I_bsn_monitor_v2_tx.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_eth1g_I_strobe_total_count_tx.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_eth1g_I_hdr_dat.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x18000' end='0x1A000' datawidth='32' /><slave name='avs2_eth_coe_1.mms_ram' start='0x1A000' end='0x1B000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x1B000' end='0x1C000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x1C800' end='0x1C900' datawidth='32' /><slave name='reg_eth1g_II_strobe_total_count_rx.mem' start='0x1C900' end='0x1C980' datawidth='32' /><slave name='reg_eth1g_II_strobe_total_count_tx.mem' start='0x1C980' end='0x1CA00' datawidth='32' /><slave name='reg_eth1g_II_hdr_dat.mem' start='0x1CA00' end='0x1CA80' datawidth='32' /><slave name='reg_eth1g_I_bg_ctrl.mem' start='0x1CA80' end='0x1CB00' datawidth='32' /><slave name='reg_heater.mem' start='0x1CB00' end='0x1CB80' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x1CB80' end='0x1CC00' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x1CC00' end='0x1CC80' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x1CC80' end='0x1CD00' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x1CD00' end='0x1CD40' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x1CD40' end='0x1CD80' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1CD80' end='0x1CDC0' datawidth='32' /><slave name='reg_eth1g_II_bg_ctrl.mem' start='0x1CDC0' end='0x1CDE0' datawidth='32' /><slave name='reg_eth1g_II_bsn_monitor_v2_rx.mem' start='0x1CDE0' end='0x1CE00' datawidth='32' /><slave name='reg_eth1g_II_bsn_monitor_v2_tx.mem' start='0x1CE00' end='0x1CE20' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x1CE20' end='0x1CE40' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x1CE40' end='0x1CE60' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x1CE60' end='0x1CE80' datawidth='32' /><slave name='reg_epcs.mem' start='0x1CE80' end='0x1CEA0' datawidth='32' /><slave name='reg_remu.mem' start='0x1CEA0' end='0x1CEC0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x1CEC0' end='0x1CEE0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x1CEE0' end='0x1CEF0' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x1CEF0' end='0x1CF00' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x1CF00' end='0x1CF10' datawidth='32' /><slave name='pio_pps.mem' start='0x1CF10' end='0x1CF20' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x1CF20' end='0x1CF28' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x1CF28' end='0x1CF30' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x1CF30' end='0x1CF38' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x1CF38' end='0x1CF40' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x1CF40' end='0x1CF48' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1CF48' end='0x1CF50' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_eth_0.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_strobe_total_count_rx_eth_0.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_tx_eth_0.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_strobe_total_count_tx_eth_0.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_hdr_dat_eth_0.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x18000' end='0x1A000' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0x1A000' end='0x1B000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x1B000' end='0x1C000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x1C800' end='0x1C900' datawidth='32' /><slave name='reg_strobe_total_count_rx_eth_1.mem' start='0x1C900' end='0x1C980' datawidth='32' /><slave name='reg_strobe_total_count_tx_eth_1.mem' start='0x1C980' end='0x1CA00' datawidth='32' /><slave name='reg_hdr_dat_eth_1.mem' start='0x1CA00' end='0x1CA80' datawidth='32' /><slave name='reg_diag_bg_eth_0.mem' start='0x1CA80' end='0x1CB00' datawidth='32' /><slave name='reg_heater.mem' start='0x1CB00' end='0x1CB80' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x1CB80' end='0x1CC00' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x1CC00' end='0x1CC80' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x1CC80' end='0x1CD00' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x1CD00' end='0x1CD40' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x1CD40' end='0x1CD80' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1CD80' end='0x1CDC0' datawidth='32' /><slave name='reg_diag_bg_eth_1.mem' start='0x1CDC0' end='0x1CDE0' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_eth_1.mem' start='0x1CDE0' end='0x1CE00' datawidth='32' /><slave name='reg_bsn_monitor_v2_tx_eth_1.mem' start='0x1CE00' end='0x1CE20' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x1CE20' end='0x1CE40' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x1CE40' end='0x1CE60' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x1CE60' end='0x1CE80' datawidth='32' /><slave name='reg_epcs.mem' start='0x1CE80' end='0x1CEA0' datawidth='32' /><slave name='reg_remu.mem' start='0x1CEA0' end='0x1CEC0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x1CEC0' end='0x1CEE0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x1CEE0' end='0x1CEF0' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x1CEF0' end='0x1CF00' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x1CF00' end='0x1CF10' datawidth='32' /><slave name='pio_pps.mem' start='0x1CF10' end='0x1CF20' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x1CF20' end='0x1CF28' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x1CF28' end='0x1CF30' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x1CF30' end='0x1CF38' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x1CF38' end='0x1CF40' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x1CF40' end='0x1CF48' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1CF48' end='0x1CF50' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
<ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -3584,7 +3584,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_bsn_monitor_v2_rx.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_strobe_total_count_rx.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='avs2_eth_coe_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs2_eth_coe_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_bsn_monitor_v2_tx.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_strobe_total_count_tx.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_hdr_dat.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_eth10g_qsfp_ring.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_10GbE.mem' start='0x18000' end='0x1A000' datawidth='32' /&gt;&lt;slave name='avs2_eth_coe_1.mms_ram' start='0x1A000' end='0x1B000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x1B000' end='0x1C000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /&gt;&lt;slave name='reg_eth10g_back0.mem' start='0x1C800' end='0x1C900' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_strobe_total_count_rx.mem' start='0x1C900' end='0x1C980' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_strobe_total_count_tx.mem' start='0x1C980' end='0x1CA00' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_hdr_dat.mem' start='0x1CA00' end='0x1CA80' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_bg_ctrl.mem' start='0x1CA80' end='0x1CB00' datawidth='32' /&gt;&lt;slave name='reg_heater.mem' start='0x1CB00' end='0x1CB80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x1CB80' end='0x1CC00' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x1CC00' end='0x1CC80' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_10gbe.mem' start='0x1CC80' end='0x1CD00' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x1CD00' end='0x1CD40' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_10gbe.mem' start='0x1CD40' end='0x1CD80' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x1CD80' end='0x1CDC0' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_bg_ctrl.mem' start='0x1CDC0' end='0x1CDE0' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_bsn_monitor_v2_rx.mem' start='0x1CDE0' end='0x1CE00' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_bsn_monitor_v2_tx.mem' start='0x1CE00' end='0x1CE20' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x1CE20' end='0x1CE40' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x1CE40' end='0x1CE60' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_10gbe.mem' start='0x1CE60' end='0x1CE80' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x1CE80' end='0x1CEA0' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x1CEA0' end='0x1CEC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x1CEC0' end='0x1CEE0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source.mem' start='0x1CEE0' end='0x1CEF0' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x1CEF0' end='0x1CF00' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x1CF00' end='0x1CF10' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x1CF10' end='0x1CF20' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x1CF20' end='0x1CF28' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x1CF28' end='0x1CF30' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x1CF30' end='0x1CF38' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x1CF38' end='0x1CF40' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x1CF40' end='0x1CF48' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x1CF48' end='0x1CF50' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /&gt;&lt;slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_eth_0.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_strobe_total_count_rx_eth_0.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='avs_eth_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_tx_eth_0.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_strobe_total_count_tx_eth_0.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat_eth_0.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_eth10g_qsfp_ring.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_10GbE.mem' start='0x18000' end='0x1A000' datawidth='32' /&gt;&lt;slave name='avs_eth_1.mms_ram' start='0x1A000' end='0x1B000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x1B000' end='0x1C000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /&gt;&lt;slave name='reg_eth10g_back0.mem' start='0x1C800' end='0x1C900' datawidth='32' /&gt;&lt;slave name='reg_strobe_total_count_rx_eth_1.mem' start='0x1C900' end='0x1C980' datawidth='32' /&gt;&lt;slave name='reg_strobe_total_count_tx_eth_1.mem' start='0x1C980' end='0x1CA00' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat_eth_1.mem' start='0x1CA00' end='0x1CA80' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_eth_0.mem' start='0x1CA80' end='0x1CB00' datawidth='32' /&gt;&lt;slave name='reg_heater.mem' start='0x1CB00' end='0x1CB80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x1CB80' end='0x1CC00' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x1CC00' end='0x1CC80' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_10gbe.mem' start='0x1CC80' end='0x1CD00' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x1CD00' end='0x1CD40' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_10gbe.mem' start='0x1CD40' end='0x1CD80' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x1CD80' end='0x1CDC0' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_eth_1.mem' start='0x1CDC0' end='0x1CDE0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_eth_1.mem' start='0x1CDE0' end='0x1CE00' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_tx_eth_1.mem' start='0x1CE00' end='0x1CE20' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x1CE20' end='0x1CE40' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x1CE40' end='0x1CE60' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_10gbe.mem' start='0x1CE60' end='0x1CE80' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x1CE80' end='0x1CEA0' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x1CEA0' end='0x1CEC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x1CEC0' end='0x1CEE0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source.mem' start='0x1CEE0' end='0x1CEF0' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x1CEF0' end='0x1CF00' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x1CF00' end='0x1CF10' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x1CF10' end='0x1CF20' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x1CF20' end='0x1CF28' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x1CF28' end='0x1CF30' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x1CF30' end='0x1CF38' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x1CF38' end='0x1CF40' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x1CF40' end='0x1CF48' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x1CF48' end='0x1CF50' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /&gt;&lt;slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
index 04e5061ee2e05437eb19b7999c3acf4500ae105d..a95f4dfded7eb4ebb19b70da0846fcf9c69d9eca 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx
+ element qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
index d2c116b0bd027b938feabf1cb356ba9d8134e463..c41940a264cf1e645565d62acd05a60502f90863 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx
+ element qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
index 969b7f6029a4ffef4df2a607493cf9649e3b5c1d..15913842ff54598fdab50bebb775bd2bd24f452a 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx
+ element qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
index e5c242e7222ee420cdc187d4acb42685392215ec..b309529a6dadafbbd2a8194f67742d8597f19e72 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx
+ element qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
index 8b5349883e8ed1ae3e5f11e4a8cee2b2f100db1e..dee194964b5948ed575ed3f841472d6a81e6b3db 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_diag_bg_eth_0</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_diag_bg_eth_0</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_diag_bg_eth_0</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_I_bg_ctrl
+ element qsys_unb2c_test_reg_diag_bg_eth_0
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
index dba9399a1b2de24b60fbdb14c7ff6935b74514f0..4145abee24649049c664d35a4ccf3285acb1b3dc 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_diag_bg_eth_1</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_diag_bg_eth_1</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_diag_bg_eth_1</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_II_bg_ctrl
+ element qsys_unb2c_test_reg_diag_bg_eth_1
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
deleted file mode 100644
index 60e87b376412f795566e2890e4c9a48217faa9a8..0000000000000000000000000000000000000000
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
+++ /dev/null
@@ -1,1535 +0,0 @@
-<?xml version="1.0" ?>
-<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
- <ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- <ipxact:busInterfaces>
- <ipxact:busInterface>
- <ipxact:name>system</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>csi_system_clk</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="clockRate" type="longint">
- <ipxact:name>clockRate</ipxact:name>
- <ipxact:displayName>Clock rate</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="externallyDriven" type="bit">
- <ipxact:name>externallyDriven</ipxact:name>
- <ipxact:displayName>Externally driven</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ptfSchematicName" type="string">
- <ipxact:name>ptfSchematicName</ipxact:name>
- <ipxact:displayName>PTF schematic name</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>system_reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>reset</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>csi_system_reset</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>system</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="synchronousEdges" type="string">
- <ipxact:name>synchronousEdges</ipxact:name>
- <ipxact:displayName>Synchronous edges</ipxact:displayName>
- <ipxact:value>DEASSERT</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>mem</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>address</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_address</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>write</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_write</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>writedata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_writedata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>read</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_read</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>readdata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_readdata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="addressAlignment" type="string">
- <ipxact:name>addressAlignment</ipxact:name>
- <ipxact:displayName>Slave addressing</ipxact:displayName>
- <ipxact:value>DYNAMIC</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressGroup" type="int">
- <ipxact:name>addressGroup</ipxact:name>
- <ipxact:displayName>Address group</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressSpan" type="string">
- <ipxact:name>addressSpan</ipxact:name>
- <ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>128</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressUnits" type="string">
- <ipxact:name>addressUnits</ipxact:name>
- <ipxact:displayName>Address units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
- <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
- <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>system</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>Associated reset</ipxact:displayName>
- <ipxact:value>system_reset</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bitsPerSymbol" type="int">
- <ipxact:name>bitsPerSymbol</ipxact:name>
- <ipxact:displayName>Bits per symbol</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
- <ipxact:name>bridgedAddressOffset</ipxact:name>
- <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgesToMaster" type="string">
- <ipxact:name>bridgesToMaster</ipxact:name>
- <ipxact:displayName>Bridges to master</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
- <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
- <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstcountUnits" type="string">
- <ipxact:name>burstcountUnits</ipxact:name>
- <ipxact:displayName>Burstcount units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
- <ipxact:name>constantBurstBehavior</ipxact:name>
- <ipxact:displayName>Constant burst behavior</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="explicitAddressSpan" type="string">
- <ipxact:name>explicitAddressSpan</ipxact:name>
- <ipxact:displayName>Explicit address span</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="holdTime" type="int">
- <ipxact:name>holdTime</ipxact:name>
- <ipxact:displayName>Hold</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="interleaveBursts" type="bit">
- <ipxact:name>interleaveBursts</ipxact:name>
- <ipxact:displayName>Interleave bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isBigEndian" type="bit">
- <ipxact:name>isBigEndian</ipxact:name>
- <ipxact:displayName>Big endian</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isFlash" type="bit">
- <ipxact:name>isFlash</ipxact:name>
- <ipxact:displayName>Flash memory</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isMemoryDevice" type="bit">
- <ipxact:name>isMemoryDevice</ipxact:name>
- <ipxact:displayName>Memory device</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
- <ipxact:name>isNonVolatileStorage</ipxact:name>
- <ipxact:displayName>Non-volatile storage</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="linewrapBursts" type="bit">
- <ipxact:name>linewrapBursts</ipxact:name>
- <ipxact:displayName>Linewrap bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
- <ipxact:name>maximumPendingReadTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
- <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumReadLatency" type="int">
- <ipxact:name>minimumReadLatency</ipxact:name>
- <ipxact:displayName>minimumReadLatency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumResponseLatency" type="int">
- <ipxact:name>minimumResponseLatency</ipxact:name>
- <ipxact:displayName>Minimum response latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
- <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
- <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="printableDevice" type="bit">
- <ipxact:name>printableDevice</ipxact:name>
- <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readLatency" type="int">
- <ipxact:name>readLatency</ipxact:name>
- <ipxact:displayName>Read latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitStates" type="int">
- <ipxact:name>readWaitStates</ipxact:name>
- <ipxact:displayName>Read wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitTime" type="int">
- <ipxact:name>readWaitTime</ipxact:name>
- <ipxact:displayName>Read wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
- <ipxact:name>registerIncomingSignals</ipxact:name>
- <ipxact:displayName>Register incoming signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
- <ipxact:name>registerOutgoingSignals</ipxact:name>
- <ipxact:displayName>Register outgoing signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="setupTime" type="int">
- <ipxact:name>setupTime</ipxact:name>
- <ipxact:displayName>Setup</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="timingUnits" type="string">
- <ipxact:name>timingUnits</ipxact:name>
- <ipxact:displayName>Timing units</ipxact:displayName>
- <ipxact:value>Cycles</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="transparentBridge" type="bit">
- <ipxact:name>transparentBridge</ipxact:name>
- <ipxact:displayName>Transparent bridge</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="waitrequestAllowance" type="int">
- <ipxact:name>waitrequestAllowance</ipxact:name>
- <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
- <ipxact:name>wellBehavedWaitrequest</ipxact:name>
- <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeLatency" type="int">
- <ipxact:name>writeLatency</ipxact:name>
- <ipxact:displayName>Write latency</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitStates" type="int">
- <ipxact:name>writeWaitStates</ipxact:name>
- <ipxact:displayName>Write wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitTime" type="int">
- <ipxact:name>writeWaitTime</ipxact:name>
- <ipxact:displayName>Write wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- <ipxact:vendorExtensions>
- <altera:altera_assignments>
- <ipxact:parameters>
- <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
- <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
- <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_assignments>
- </ipxact:vendorExtensions>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_reset_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>clk</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_clk_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>address</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_address_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>write</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_write_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>writedata</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_writedata_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>read</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_read_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>readdata</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_readdata_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- </ipxact:busInterfaces>
- <ipxact:model>
- <ipxact:views>
- <ipxact:view>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
- <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
- </ipxact:view>
- </ipxact:views>
- <ipxact:instantiations>
- <ipxact:componentInstantiation>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
- <ipxact:fileSetRef>
- <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
- </ipxact:fileSetRef>
- <ipxact:parameters></ipxact:parameters>
- </ipxact:componentInstantiation>
- </ipxact:instantiations>
- <ipxact:ports>
- <ipxact:port>
- <ipxact:name>csi_system_clk</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>csi_system_reset</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_address</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>4</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_write</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_writedata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_read</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_readdata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_reset_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_clk_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_address_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>4</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_write_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_writedata_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_read_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_readdata_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- </ipxact:ports>
- </ipxact:model>
- <ipxact:vendorExtensions>
- <altera:entity_info>
- <ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</ipxact:library>
- <ipxact:name>avs_common_mm</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="g_adr_w" type="int">
- <ipxact:name>g_adr_w</ipxact:name>
- <ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>5</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="g_dat_w" type="int">
- <ipxact:name>g_dat_w</ipxact:name>
- <ipxact:displayName>g_dat_w</ipxact:displayName>
- <ipxact:value>32</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
- <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
- <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
- <ipxact:value>125000000</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="device" type="string">
- <ipxact:name>device</ipxact:name>
- <ipxact:displayName>Device</ipxact:displayName>
- <ipxact:value>10AX115U3F45E2SG</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFamily" type="string">
- <ipxact:name>deviceFamily</ipxact:name>
- <ipxact:displayName>Device family</ipxact:displayName>
- <ipxact:value>Arria 10</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
- <ipxact:name>deviceSpeedGrade</ipxact:name>
- <ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>2</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="generationId" type="int">
- <ipxact:name>generationId</ipxact:name>
- <ipxact:displayName>Generation Id</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bonusData" type="string">
- <ipxact:name>bonusData</ipxact:name>
- <ipxact:displayName>bonusData</ipxact:displayName>
- <ipxact:value>bonusData
-{
- element $system
- {
- datum _originalDeviceFamily
- {
- value = "Arria 10";
- type = "String";
- }
- }
- element qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx
- {
- }
-}
-</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
- <ipxact:name>hideFromIPCatalog</ipxact:name>
- <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
- <ipxact:name>lockedInterfaceDefinition</ipxact:name>
- <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
- <ipxact:value><boundaryDefinition>
- <interfaces>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>5</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>128</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>5</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="systemInfos" type="string">
- <ipxact:name>systemInfos</ipxact:name>
- <ipxact:displayName>systemInfos</ipxact:displayName>
- <ipxact:value><systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>7</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>125000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.address" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.clk" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.mem" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.read" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.readdata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.reset" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.system" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.system_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.write" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.writedata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </ipxact:vendorExtensions>
-</ipxact:component>
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
deleted file mode 100644
index 0e21ab78fc7b77fd77d223d96837fc0542686ef5..0000000000000000000000000000000000000000
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
+++ /dev/null
@@ -1,1535 +0,0 @@
-<?xml version="1.0" ?>
-<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
- <ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- <ipxact:busInterfaces>
- <ipxact:busInterface>
- <ipxact:name>system</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>csi_system_clk</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="clockRate" type="longint">
- <ipxact:name>clockRate</ipxact:name>
- <ipxact:displayName>Clock rate</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="externallyDriven" type="bit">
- <ipxact:name>externallyDriven</ipxact:name>
- <ipxact:displayName>Externally driven</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ptfSchematicName" type="string">
- <ipxact:name>ptfSchematicName</ipxact:name>
- <ipxact:displayName>PTF schematic name</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>system_reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>reset</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>csi_system_reset</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>system</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="synchronousEdges" type="string">
- <ipxact:name>synchronousEdges</ipxact:name>
- <ipxact:displayName>Synchronous edges</ipxact:displayName>
- <ipxact:value>DEASSERT</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>mem</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>address</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_address</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>write</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_write</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>writedata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_writedata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>read</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_read</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>readdata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_readdata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="addressAlignment" type="string">
- <ipxact:name>addressAlignment</ipxact:name>
- <ipxact:displayName>Slave addressing</ipxact:displayName>
- <ipxact:value>DYNAMIC</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressGroup" type="int">
- <ipxact:name>addressGroup</ipxact:name>
- <ipxact:displayName>Address group</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressSpan" type="string">
- <ipxact:name>addressSpan</ipxact:name>
- <ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>128</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressUnits" type="string">
- <ipxact:name>addressUnits</ipxact:name>
- <ipxact:displayName>Address units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
- <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
- <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>system</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>Associated reset</ipxact:displayName>
- <ipxact:value>system_reset</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bitsPerSymbol" type="int">
- <ipxact:name>bitsPerSymbol</ipxact:name>
- <ipxact:displayName>Bits per symbol</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
- <ipxact:name>bridgedAddressOffset</ipxact:name>
- <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgesToMaster" type="string">
- <ipxact:name>bridgesToMaster</ipxact:name>
- <ipxact:displayName>Bridges to master</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
- <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
- <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstcountUnits" type="string">
- <ipxact:name>burstcountUnits</ipxact:name>
- <ipxact:displayName>Burstcount units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
- <ipxact:name>constantBurstBehavior</ipxact:name>
- <ipxact:displayName>Constant burst behavior</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="explicitAddressSpan" type="string">
- <ipxact:name>explicitAddressSpan</ipxact:name>
- <ipxact:displayName>Explicit address span</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="holdTime" type="int">
- <ipxact:name>holdTime</ipxact:name>
- <ipxact:displayName>Hold</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="interleaveBursts" type="bit">
- <ipxact:name>interleaveBursts</ipxact:name>
- <ipxact:displayName>Interleave bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isBigEndian" type="bit">
- <ipxact:name>isBigEndian</ipxact:name>
- <ipxact:displayName>Big endian</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isFlash" type="bit">
- <ipxact:name>isFlash</ipxact:name>
- <ipxact:displayName>Flash memory</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isMemoryDevice" type="bit">
- <ipxact:name>isMemoryDevice</ipxact:name>
- <ipxact:displayName>Memory device</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
- <ipxact:name>isNonVolatileStorage</ipxact:name>
- <ipxact:displayName>Non-volatile storage</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="linewrapBursts" type="bit">
- <ipxact:name>linewrapBursts</ipxact:name>
- <ipxact:displayName>Linewrap bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
- <ipxact:name>maximumPendingReadTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
- <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumReadLatency" type="int">
- <ipxact:name>minimumReadLatency</ipxact:name>
- <ipxact:displayName>minimumReadLatency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumResponseLatency" type="int">
- <ipxact:name>minimumResponseLatency</ipxact:name>
- <ipxact:displayName>Minimum response latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
- <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
- <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="printableDevice" type="bit">
- <ipxact:name>printableDevice</ipxact:name>
- <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readLatency" type="int">
- <ipxact:name>readLatency</ipxact:name>
- <ipxact:displayName>Read latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitStates" type="int">
- <ipxact:name>readWaitStates</ipxact:name>
- <ipxact:displayName>Read wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitTime" type="int">
- <ipxact:name>readWaitTime</ipxact:name>
- <ipxact:displayName>Read wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
- <ipxact:name>registerIncomingSignals</ipxact:name>
- <ipxact:displayName>Register incoming signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
- <ipxact:name>registerOutgoingSignals</ipxact:name>
- <ipxact:displayName>Register outgoing signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="setupTime" type="int">
- <ipxact:name>setupTime</ipxact:name>
- <ipxact:displayName>Setup</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="timingUnits" type="string">
- <ipxact:name>timingUnits</ipxact:name>
- <ipxact:displayName>Timing units</ipxact:displayName>
- <ipxact:value>Cycles</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="transparentBridge" type="bit">
- <ipxact:name>transparentBridge</ipxact:name>
- <ipxact:displayName>Transparent bridge</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="waitrequestAllowance" type="int">
- <ipxact:name>waitrequestAllowance</ipxact:name>
- <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
- <ipxact:name>wellBehavedWaitrequest</ipxact:name>
- <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeLatency" type="int">
- <ipxact:name>writeLatency</ipxact:name>
- <ipxact:displayName>Write latency</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitStates" type="int">
- <ipxact:name>writeWaitStates</ipxact:name>
- <ipxact:displayName>Write wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitTime" type="int">
- <ipxact:name>writeWaitTime</ipxact:name>
- <ipxact:displayName>Write wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- <ipxact:vendorExtensions>
- <altera:altera_assignments>
- <ipxact:parameters>
- <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
- <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
- <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_assignments>
- </ipxact:vendorExtensions>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_reset_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>clk</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_clk_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>address</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_address_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>write</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_write_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>writedata</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_writedata_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>read</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_read_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>readdata</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_readdata_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- </ipxact:busInterfaces>
- <ipxact:model>
- <ipxact:views>
- <ipxact:view>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
- <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
- </ipxact:view>
- </ipxact:views>
- <ipxact:instantiations>
- <ipxact:componentInstantiation>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
- <ipxact:fileSetRef>
- <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
- </ipxact:fileSetRef>
- <ipxact:parameters></ipxact:parameters>
- </ipxact:componentInstantiation>
- </ipxact:instantiations>
- <ipxact:ports>
- <ipxact:port>
- <ipxact:name>csi_system_clk</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>csi_system_reset</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_address</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>4</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_write</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_writedata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_read</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_readdata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_reset_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_clk_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_address_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>4</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_write_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_writedata_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_read_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_readdata_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- </ipxact:ports>
- </ipxact:model>
- <ipxact:vendorExtensions>
- <altera:entity_info>
- <ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</ipxact:library>
- <ipxact:name>avs_common_mm</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="g_adr_w" type="int">
- <ipxact:name>g_adr_w</ipxact:name>
- <ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>5</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="g_dat_w" type="int">
- <ipxact:name>g_dat_w</ipxact:name>
- <ipxact:displayName>g_dat_w</ipxact:displayName>
- <ipxact:value>32</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
- <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
- <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
- <ipxact:value>125000000</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="device" type="string">
- <ipxact:name>device</ipxact:name>
- <ipxact:displayName>Device</ipxact:displayName>
- <ipxact:value>10AX115U3F45E2SG</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFamily" type="string">
- <ipxact:name>deviceFamily</ipxact:name>
- <ipxact:displayName>Device family</ipxact:displayName>
- <ipxact:value>Arria 10</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
- <ipxact:name>deviceSpeedGrade</ipxact:name>
- <ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>2</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="generationId" type="int">
- <ipxact:name>generationId</ipxact:name>
- <ipxact:displayName>Generation Id</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bonusData" type="string">
- <ipxact:name>bonusData</ipxact:name>
- <ipxact:displayName>bonusData</ipxact:displayName>
- <ipxact:value>bonusData
-{
- element $system
- {
- datum _originalDeviceFamily
- {
- value = "Arria 10";
- type = "String";
- }
- }
- element qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx
- {
- }
-}
-</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
- <ipxact:name>hideFromIPCatalog</ipxact:name>
- <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
- <ipxact:name>lockedInterfaceDefinition</ipxact:name>
- <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
- <ipxact:value><boundaryDefinition>
- <interfaces>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>5</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>128</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>5</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="systemInfos" type="string">
- <ipxact:name>systemInfos</ipxact:name>
- <ipxact:displayName>systemInfos</ipxact:displayName>
- <ipxact:value><systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>7</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>125000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.address" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.clk" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.mem" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.read" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.readdata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.reset" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.system" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.system_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.write" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.writedata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </ipxact:vendorExtensions>
-</ipxact:component>
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
index 0e9f2b1f5b8adc9145686dcd761143048bbeeca5..971f53f6c728c725da3451332ba7c9c112f5730b 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_hdr_dat</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_I_hdr_dat</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_hdr_dat_eth_0</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_hdr_dat_eth_0</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_hdr_dat</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_hdr_dat_eth_0</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_I_hdr_dat
+ element qsys_unb2c_test_reg_hdr_dat_eth_0
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
index d352a73115098dc4e0143ee126981738369ffc0e..8ecb89c83d9b31c3347ea372db0eeb0ffe8b807d 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_hdr_dat</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_II_hdr_dat</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_hdr_dat_eth_1</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_hdr_dat_eth_1</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_hdr_dat</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_hdr_dat_eth_1</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_II_hdr_dat
+ element qsys_unb2c_test_reg_hdr_dat_eth_1
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
index d2b0b772d7e6cdfb315ef6e107e7b160abce9372..6673af2cc982e2ffe9670a9fc936b9074e0362b9 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx
+ element qsys_unb2c_test_reg_strobe_total_count_rx_eth_0
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
new file mode 100644
index 0000000000000000000000000000000000000000..2f553a7b5a5aab9b0231350f3df1b293ff9e8f92
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>128</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>5</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>125000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_unb2c_test_reg_strobe_total_count_rx_eth_1
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>128</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>7</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
index 1cc106178b974d387b36f88acd458bf7fc4ce2a9..736faa5cf084658c3701c199c50f7a0432000ff3 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx
+ element qsys_unb2c_test_reg_strobe_total_count_tx_eth_0
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
new file mode 100644
index 0000000000000000000000000000000000000000..516f092e7852710c5b5149a154de8c0d9f2a8b51
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>128</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>5</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>125000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_unb2c_test_reg_strobe_total_count_tx_eth_1
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>128</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>7</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/qsys_unb2c_test.qsys b/boards/uniboard2c/designs/unb2c_test/quartus/qsys_unb2c_test.qsys
index 39f5d5f8ed1479c10720f85597925dbaa40dadc9..1995aff20a88107325e1c35e4b662f24800afb73 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/qsys_unb2c_test.qsys
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/qsys_unb2c_test.qsys
@@ -10,67 +10,67 @@
tool="QsysPro" />
<parameter name="bonusData"><![CDATA[bonusData
{
- element avs2_eth_coe_1
+ element avs_eth_0
{
datum _sortIndex
{
- value = "7";
+ value = "6";
type = "int";
}
}
- element avs2_eth_coe_1.mms_ram
+ element avs_eth_0.mms_ram
{
datum baseAddress
{
- value = "106496";
+ value = "110592";
type = "String";
}
}
- element avs2_eth_coe_1.mms_reg
+ element avs_eth_0.mms_reg
{
datum baseAddress
{
- value = "12352";
+ value = "118016";
type = "String";
}
}
- element avs2_eth_coe_1.mms_tse
+ element avs_eth_0.mms_tse
{
datum baseAddress
{
- value = "4096";
+ value = "8192";
type = "String";
}
}
- element avs_eth_0
+ element avs_eth_1
{
datum _sortIndex
{
- value = "6";
+ value = "7";
type = "int";
}
}
- element avs_eth_0.mms_ram
+ element avs_eth_1.mms_ram
{
datum baseAddress
{
- value = "110592";
+ value = "106496";
type = "String";
}
}
- element avs_eth_0.mms_reg
+ element avs_eth_1.mms_reg
{
datum baseAddress
{
- value = "118016";
+ value = "12352";
type = "String";
}
}
- element avs_eth_0.mms_tse
+ element avs_eth_1.mms_tse
{
datum baseAddress
{
- value = "8192";
+ value = "4096";
type = "String";
}
}
@@ -348,6 +348,70 @@
type = "String";
}
}
+ element reg_bsn_monitor_v2_rx_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "61";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_rx_eth_0.mem
+ {
+ datum baseAddress
+ {
+ value = "128";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_rx_eth_1
+ {
+ datum _sortIndex
+ {
+ value = "56";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_rx_eth_1.mem
+ {
+ datum baseAddress
+ {
+ value = "118240";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_tx_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "59";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_tx_eth_0.mem
+ {
+ datum baseAddress
+ {
+ value = "12416";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_tx_eth_1
+ {
+ datum _sortIndex
+ {
+ value = "54";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_tx_eth_1.mem
+ {
+ datum baseAddress
+ {
+ value = "118272";
+ type = "String";
+ }
+ }
element reg_bsn_scheduler
{
datum _sortIndex
@@ -396,6 +460,38 @@
type = "String";
}
}
+ element reg_diag_bg_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "52";
+ type = "int";
+ }
+ }
+ element reg_diag_bg_eth_0.mem
+ {
+ datum baseAddress
+ {
+ value = "117376";
+ type = "String";
+ }
+ }
+ element reg_diag_bg_eth_1
+ {
+ datum _sortIndex
+ {
+ value = "63";
+ type = "int";
+ }
+ }
+ element reg_diag_bg_eth_1.mem
+ {
+ datum baseAddress
+ {
+ value = "118208";
+ type = "String";
+ }
+ }
element reg_diag_data_buffer_10gbe
{
datum _sortIndex
@@ -652,151 +748,39 @@
type = "String";
}
}
- element reg_eth1g_II_bg_ctrl
- {
- datum _sortIndex
- {
- value = "63";
- type = "int";
- }
- }
- element reg_eth1g_II_bg_ctrl.mem
- {
- datum baseAddress
- {
- value = "118208";
- type = "String";
- }
- }
- element reg_eth1g_II_bsn_monitor_v2_rx
- {
- datum _sortIndex
- {
- value = "56";
- type = "int";
- }
- }
- element reg_eth1g_II_bsn_monitor_v2_rx.mem
- {
- datum baseAddress
- {
- value = "118240";
- type = "String";
- }
- }
- element reg_eth1g_II_bsn_monitor_v2_tx
- {
- datum _sortIndex
- {
- value = "54";
- type = "int";
- }
- }
- element reg_eth1g_II_bsn_monitor_v2_tx.mem
- {
- datum baseAddress
- {
- value = "118272";
- type = "String";
- }
- }
- element reg_eth1g_II_hdr_dat
- {
- datum _sortIndex
- {
- value = "53";
- type = "int";
- }
- }
- element reg_eth1g_II_hdr_dat.mem
- {
- datum baseAddress
- {
- value = "117248";
- type = "String";
- }
- }
- element reg_eth1g_II_strobe_total_count_rx
- {
- datum _sortIndex
- {
- value = "57";
- type = "int";
- }
- }
- element reg_eth1g_II_strobe_total_count_rx.mem
- {
- datum baseAddress
- {
- value = "116992";
- type = "String";
- }
- }
- element reg_eth1g_II_strobe_total_count_tx
- {
- datum _sortIndex
- {
- value = "55";
- type = "int";
- }
- }
- element reg_eth1g_II_strobe_total_count_tx.mem
- {
- datum baseAddress
- {
- value = "117120";
- type = "String";
- }
- }
- element reg_eth1g_I_bg_ctrl
- {
- datum _sortIndex
- {
- value = "52";
- type = "int";
- }
- }
- element reg_eth1g_I_bg_ctrl.mem
- {
- datum baseAddress
- {
- value = "117376";
- type = "String";
- }
- }
- element reg_eth1g_I_bsn_monitor_v2_rx
+ element reg_fpga_temp_sens
{
datum _sortIndex
{
- value = "61";
+ value = "8";
type = "int";
}
}
- element reg_eth1g_I_bsn_monitor_v2_rx.mem
+ element reg_fpga_temp_sens.mem
{
datum baseAddress
{
- value = "128";
+ value = "118464";
type = "String";
}
}
- element reg_eth1g_I_bsn_monitor_v2_tx
+ element reg_fpga_voltage_sens
{
datum _sortIndex
{
- value = "59";
+ value = "19";
type = "int";
}
}
- element reg_eth1g_I_bsn_monitor_v2_tx.mem
+ element reg_fpga_voltage_sens.mem
{
datum baseAddress
{
- value = "12416";
+ value = "118144";
type = "String";
}
}
- element reg_eth1g_I_hdr_dat
+ element reg_hdr_dat_eth_0
{
datum _sortIndex
{
@@ -804,7 +788,7 @@
type = "int";
}
}
- element reg_eth1g_I_hdr_dat.mem
+ element reg_hdr_dat_eth_0.mem
{
datum baseAddress
{
@@ -812,67 +796,19 @@
type = "String";
}
}
- element reg_eth1g_I_strobe_total_count_rx
+ element reg_hdr_dat_eth_1
{
datum _sortIndex
{
- value = "62";
- type = "int";
- }
- }
- element reg_eth1g_I_strobe_total_count_rx.mem
- {
- datum baseAddress
- {
- value = "512";
- type = "String";
- }
- }
- element reg_eth1g_I_strobe_total_count_tx
- {
- datum _sortIndex
- {
- value = "60";
- type = "int";
- }
- }
- element reg_eth1g_I_strobe_total_count_tx.mem
- {
- datum baseAddress
- {
- value = "12800";
- type = "String";
- }
- }
- element reg_fpga_temp_sens
- {
- datum _sortIndex
- {
- value = "8";
- type = "int";
- }
- }
- element reg_fpga_temp_sens.mem
- {
- datum baseAddress
- {
- value = "118464";
- type = "String";
- }
- }
- element reg_fpga_voltage_sens
- {
- datum _sortIndex
- {
- value = "19";
+ value = "53";
type = "int";
}
}
- element reg_fpga_voltage_sens.mem
+ element reg_hdr_dat_eth_1.mem
{
datum baseAddress
{
- value = "118144";
+ value = "117248";
type = "String";
}
}
@@ -972,6 +908,70 @@
type = "String";
}
}
+ element reg_strobe_total_count_rx_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "62";
+ type = "int";
+ }
+ }
+ element reg_strobe_total_count_rx_eth_0.mem
+ {
+ datum baseAddress
+ {
+ value = "512";
+ type = "String";
+ }
+ }
+ element reg_strobe_total_count_rx_eth_1
+ {
+ datum _sortIndex
+ {
+ value = "57";
+ type = "int";
+ }
+ }
+ element reg_strobe_total_count_rx_eth_1.mem
+ {
+ datum baseAddress
+ {
+ value = "116992";
+ type = "String";
+ }
+ }
+ element reg_strobe_total_count_tx_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "60";
+ type = "int";
+ }
+ }
+ element reg_strobe_total_count_tx_eth_0.mem
+ {
+ datum baseAddress
+ {
+ value = "12800";
+ type = "String";
+ }
+ }
+ element reg_strobe_total_count_tx_eth_1
+ {
+ datum _sortIndex
+ {
+ value = "55";
+ type = "int";
+ }
+ }
+ element reg_strobe_total_count_tx_eth_1.mem
+ {
+ datum baseAddress
+ {
+ value = "117120";
+ type = "String";
+ }
+ }
element reg_tr_10GbE_back0
{
datum _sortIndex
@@ -1114,193 +1114,193 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
- name="avs2_eth_coe_1_clk"
- internal="avs2_eth_coe_1.clk"
+ name="avs_eth_0_clk"
+ internal="avs_eth_0.clk"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_irq"
- internal="avs2_eth_coe_1.irq"
+ name="avs_eth_0_irq"
+ internal="avs_eth_0.irq"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_ram_address"
- internal="avs2_eth_coe_1.ram_address"
+ name="avs_eth_0_ram_address"
+ internal="avs_eth_0.ram_address"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_ram_read"
- internal="avs2_eth_coe_1.ram_read"
+ name="avs_eth_0_ram_read"
+ internal="avs_eth_0.ram_read"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_ram_readdata"
- internal="avs2_eth_coe_1.ram_readdata"
+ name="avs_eth_0_ram_readdata"
+ internal="avs_eth_0.ram_readdata"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_ram_write"
- internal="avs2_eth_coe_1.ram_write"
+ name="avs_eth_0_ram_write"
+ internal="avs_eth_0.ram_write"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_ram_writedata"
- internal="avs2_eth_coe_1.ram_writedata"
+ name="avs_eth_0_ram_writedata"
+ internal="avs_eth_0.ram_writedata"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_reg_address"
- internal="avs2_eth_coe_1.reg_address"
+ name="avs_eth_0_reg_address"
+ internal="avs_eth_0.reg_address"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_reg_read"
- internal="avs2_eth_coe_1.reg_read"
+ name="avs_eth_0_reg_read"
+ internal="avs_eth_0.reg_read"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_reg_readdata"
- internal="avs2_eth_coe_1.reg_readdata"
+ name="avs_eth_0_reg_readdata"
+ internal="avs_eth_0.reg_readdata"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_reg_write"
- internal="avs2_eth_coe_1.reg_write"
+ name="avs_eth_0_reg_write"
+ internal="avs_eth_0.reg_write"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_reg_writedata"
- internal="avs2_eth_coe_1.reg_writedata"
+ name="avs_eth_0_reg_writedata"
+ internal="avs_eth_0.reg_writedata"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_reset"
- internal="avs2_eth_coe_1.reset"
+ name="avs_eth_0_reset"
+ internal="avs_eth_0.reset"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_tse_address"
- internal="avs2_eth_coe_1.tse_address"
+ name="avs_eth_0_tse_address"
+ internal="avs_eth_0.tse_address"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_tse_read"
- internal="avs2_eth_coe_1.tse_read"
+ name="avs_eth_0_tse_read"
+ internal="avs_eth_0.tse_read"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_tse_readdata"
- internal="avs2_eth_coe_1.tse_readdata"
+ name="avs_eth_0_tse_readdata"
+ internal="avs_eth_0.tse_readdata"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_tse_waitrequest"
- internal="avs2_eth_coe_1.tse_waitrequest"
+ name="avs_eth_0_tse_waitrequest"
+ internal="avs_eth_0.tse_waitrequest"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_tse_write"
- internal="avs2_eth_coe_1.tse_write"
+ name="avs_eth_0_tse_write"
+ internal="avs_eth_0.tse_write"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_tse_writedata"
- internal="avs2_eth_coe_1.tse_writedata"
+ name="avs_eth_0_tse_writedata"
+ internal="avs_eth_0.tse_writedata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_clk"
- internal="avs_eth_0.clk"
+ name="avs_eth_1_clk"
+ internal="avs_eth_1.clk"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_irq"
- internal="avs_eth_0.irq"
+ name="avs_eth_1_irq"
+ internal="avs_eth_1.irq"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_ram_address"
- internal="avs_eth_0.ram_address"
+ name="avs_eth_1_ram_address"
+ internal="avs_eth_1.ram_address"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_ram_read"
- internal="avs_eth_0.ram_read"
+ name="avs_eth_1_ram_read"
+ internal="avs_eth_1.ram_read"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_ram_readdata"
- internal="avs_eth_0.ram_readdata"
+ name="avs_eth_1_ram_readdata"
+ internal="avs_eth_1.ram_readdata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_ram_write"
- internal="avs_eth_0.ram_write"
+ name="avs_eth_1_ram_write"
+ internal="avs_eth_1.ram_write"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_ram_writedata"
- internal="avs_eth_0.ram_writedata"
+ name="avs_eth_1_ram_writedata"
+ internal="avs_eth_1.ram_writedata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_reg_address"
- internal="avs_eth_0.reg_address"
+ name="avs_eth_1_reg_address"
+ internal="avs_eth_1.reg_address"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_reg_read"
- internal="avs_eth_0.reg_read"
+ name="avs_eth_1_reg_read"
+ internal="avs_eth_1.reg_read"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_reg_readdata"
- internal="avs_eth_0.reg_readdata"
+ name="avs_eth_1_reg_readdata"
+ internal="avs_eth_1.reg_readdata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_reg_write"
- internal="avs_eth_0.reg_write"
+ name="avs_eth_1_reg_write"
+ internal="avs_eth_1.reg_write"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_reg_writedata"
- internal="avs_eth_0.reg_writedata"
+ name="avs_eth_1_reg_writedata"
+ internal="avs_eth_1.reg_writedata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_reset"
- internal="avs_eth_0.reset"
+ name="avs_eth_1_reset"
+ internal="avs_eth_1.reset"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_address"
- internal="avs_eth_0.tse_address"
+ name="avs_eth_1_tse_address"
+ internal="avs_eth_1.tse_address"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_read"
- internal="avs_eth_0.tse_read"
+ name="avs_eth_1_tse_read"
+ internal="avs_eth_1.tse_read"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_readdata"
- internal="avs_eth_0.tse_readdata"
+ name="avs_eth_1_tse_readdata"
+ internal="avs_eth_1.tse_readdata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_waitrequest"
- internal="avs_eth_0.tse_waitrequest"
+ name="avs_eth_1_tse_waitrequest"
+ internal="avs_eth_1.tse_waitrequest"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_write"
- internal="avs_eth_0.tse_write"
+ name="avs_eth_1_tse_write"
+ internal="avs_eth_1.tse_write"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_writedata"
- internal="avs_eth_0.tse_writedata"
+ name="avs_eth_1_tse_writedata"
+ internal="avs_eth_1.tse_writedata"
type="conduit"
dir="end" />
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
@@ -1717,6 +1717,141 @@
internal="reg_bsn_monitor_input.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_0_address"
+ internal="reg_bsn_monitor_v2_rx_eth_0.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_0_clk"
+ internal="reg_bsn_monitor_v2_rx_eth_0.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_0_read"
+ internal="reg_bsn_monitor_v2_rx_eth_0.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_0_readdata"
+ internal="reg_bsn_monitor_v2_rx_eth_0.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_0_reset"
+ internal="reg_bsn_monitor_v2_rx_eth_0.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_0_write"
+ internal="reg_bsn_monitor_v2_rx_eth_0.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_0_writedata"
+ internal="reg_bsn_monitor_v2_rx_eth_0.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_1_address"
+ internal="reg_bsn_monitor_v2_rx_eth_1.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_1_clk"
+ internal="reg_bsn_monitor_v2_rx_eth_1.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_1_read"
+ internal="reg_bsn_monitor_v2_rx_eth_1.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_1_readdata"
+ internal="reg_bsn_monitor_v2_rx_eth_1.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_1_reset"
+ internal="reg_bsn_monitor_v2_rx_eth_1.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_1_write"
+ internal="reg_bsn_monitor_v2_rx_eth_1.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_1_writedata"
+ internal="reg_bsn_monitor_v2_rx_eth_1.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_0_address"
+ internal="reg_bsn_monitor_v2_tx_eth_0.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_0_clk"
+ internal="reg_bsn_monitor_v2_tx_eth_0.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_0_read"
+ internal="reg_bsn_monitor_v2_tx_eth_0.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_0_reset"
+ internal="reg_bsn_monitor_v2_tx_eth_0.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_0_write"
+ internal="reg_bsn_monitor_v2_tx_eth_0.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_0_writedata"
+ internal="reg_bsn_monitor_v2_tx_eth_0.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_1_address"
+ internal="reg_bsn_monitor_v2_tx_eth_1.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_1_clk"
+ internal="reg_bsn_monitor_v2_tx_eth_1.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_1_read"
+ internal="reg_bsn_monitor_v2_tx_eth_1.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_1_readdata"
+ internal="reg_bsn_monitor_v2_tx_eth_1.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_1_reset"
+ internal="reg_bsn_monitor_v2_tx_eth_1.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_1_write"
+ internal="reg_bsn_monitor_v2_tx_eth_1.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_1_writedata"
+ internal="reg_bsn_monitor_v2_tx_eth_1.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_bsn_scheduler_address"
internal="reg_bsn_scheduler.address"
@@ -1822,6 +1957,76 @@
internal="reg_diag_bg_10gbe.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_diag_bg_eth_0_address"
+ internal="reg_diag_bg_eth_0.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_0_clk"
+ internal="reg_diag_bg_eth_0.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_0_read"
+ internal="reg_diag_bg_eth_0.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_0_readdata"
+ internal="reg_diag_bg_eth_0.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_0_reset"
+ internal="reg_diag_bg_eth_0.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_0_write"
+ internal="reg_diag_bg_eth_0.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_0_writedata"
+ internal="reg_diag_bg_eth_0.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_1_address"
+ internal="reg_diag_bg_eth_1.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_1_clk"
+ internal="reg_diag_bg_eth_1.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_1_read"
+ internal="reg_diag_bg_eth_1.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_1_readdata"
+ internal="reg_diag_bg_eth_1.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_1_reset"
+ internal="reg_diag_bg_eth_1.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_1_write"
+ internal="reg_diag_bg_eth_1.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_1_writedata"
+ internal="reg_diag_bg_eth_1.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_diag_data_buffer_10gbe_address"
internal="reg_diag_data_buffer_10gbe.address"
@@ -2379,699 +2584,494 @@
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_i_bg_ctrl_address"
- internal="reg_eth1g_I_bg_ctrl.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bg_ctrl_clk"
- internal="reg_eth1g_I_bg_ctrl.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bg_ctrl_read"
- internal="reg_eth1g_I_bg_ctrl.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bg_ctrl_readdata"
- internal="reg_eth1g_I_bg_ctrl.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bg_ctrl_reset"
- internal="reg_eth1g_I_bg_ctrl.reset"
+ name="reg_bsn_monitor_v2_tx_eth_0_readdata"
+ internal="reg_bsn_monitor_v2_tx_eth_0.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_i_bg_ctrl_write"
- internal="reg_eth1g_I_bg_ctrl.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bg_ctrl_writedata"
- internal="reg_eth1g_I_bg_ctrl.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_rx_address"
- internal="reg_eth1g_I_bsn_monitor_v2_rx.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_rx_clk"
- internal="reg_eth1g_I_bsn_monitor_v2_rx.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_rx_read"
- internal="reg_eth1g_I_bsn_monitor_v2_rx.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_rx_readdata"
- internal="reg_eth1g_I_bsn_monitor_v2_rx.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_rx_reset"
- internal="reg_eth1g_I_bsn_monitor_v2_rx.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_rx_write"
- internal="reg_eth1g_I_bsn_monitor_v2_rx.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_rx_writedata"
- internal="reg_eth1g_I_bsn_monitor_v2_rx.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_tx_address"
- internal="reg_eth1g_I_bsn_monitor_v2_tx.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_tx_clk"
- internal="reg_eth1g_I_bsn_monitor_v2_tx.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_tx_read"
- internal="reg_eth1g_I_bsn_monitor_v2_tx.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_tx_readdata"
- internal="reg_eth1g_I_bsn_monitor_v2_tx.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_tx_reset"
- internal="reg_eth1g_I_bsn_monitor_v2_tx.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_tx_write"
- internal="reg_eth1g_I_bsn_monitor_v2_tx.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_tx_writedata"
- internal="reg_eth1g_I_bsn_monitor_v2_tx.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_hdr_dat_address"
- internal="reg_eth1g_I_hdr_dat.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_hdr_dat_clk"
- internal="reg_eth1g_I_hdr_dat.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_hdr_dat_read"
- internal="reg_eth1g_I_hdr_dat.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_hdr_dat_readdata"
- internal="reg_eth1g_I_hdr_dat.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_hdr_dat_reset"
- internal="reg_eth1g_I_hdr_dat.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_hdr_dat_write"
- internal="reg_eth1g_I_hdr_dat.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_hdr_dat_writedata"
- internal="reg_eth1g_I_hdr_dat.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_rx_address"
- internal="reg_eth1g_I_strobe_total_count_rx.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_rx_clk"
- internal="reg_eth1g_I_strobe_total_count_rx.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_rx_read"
- internal="reg_eth1g_I_strobe_total_count_rx.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_rx_readdata"
- internal="reg_eth1g_I_strobe_total_count_rx.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_rx_reset"
- internal="reg_eth1g_I_strobe_total_count_rx.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_rx_write"
- internal="reg_eth1g_I_strobe_total_count_rx.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_rx_writedata"
- internal="reg_eth1g_I_strobe_total_count_rx.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_tx_address"
- internal="reg_eth1g_I_strobe_total_count_tx.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_tx_clk"
- internal="reg_eth1g_I_strobe_total_count_tx.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_tx_read"
- internal="reg_eth1g_I_strobe_total_count_tx.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_tx_readdata"
- internal="reg_eth1g_I_strobe_total_count_tx.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_tx_reset"
- internal="reg_eth1g_I_strobe_total_count_tx.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_tx_write"
- internal="reg_eth1g_I_strobe_total_count_tx.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_tx_writedata"
- internal="reg_eth1g_I_strobe_total_count_tx.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_ii_bg_ctrl_address"
- internal="reg_eth1g_II_bg_ctrl.address"
+ name="reg_fpga_temp_sens_address"
+ internal="reg_fpga_temp_sens.address"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bg_ctrl_clk"
- internal="reg_eth1g_II_bg_ctrl.clk"
+ name="reg_fpga_temp_sens_clk"
+ internal="reg_fpga_temp_sens.clk"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bg_ctrl_read"
- internal="reg_eth1g_II_bg_ctrl.read"
+ name="reg_fpga_temp_sens_read"
+ internal="reg_fpga_temp_sens.read"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bg_ctrl_readdata"
- internal="reg_eth1g_II_bg_ctrl.readdata"
+ name="reg_fpga_temp_sens_readdata"
+ internal="reg_fpga_temp_sens.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bg_ctrl_reset"
- internal="reg_eth1g_II_bg_ctrl.reset"
+ name="reg_fpga_temp_sens_reset"
+ internal="reg_fpga_temp_sens.reset"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bg_ctrl_write"
- internal="reg_eth1g_II_bg_ctrl.write"
+ name="reg_fpga_temp_sens_write"
+ internal="reg_fpga_temp_sens.write"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bg_ctrl_writedata"
- internal="reg_eth1g_II_bg_ctrl.writedata"
+ name="reg_fpga_temp_sens_writedata"
+ internal="reg_fpga_temp_sens.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_rx_address"
- internal="reg_eth1g_II_bsn_monitor_v2_rx.address"
+ name="reg_fpga_voltage_sens_address"
+ internal="reg_fpga_voltage_sens.address"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_rx_clk"
- internal="reg_eth1g_II_bsn_monitor_v2_rx.clk"
+ name="reg_fpga_voltage_sens_clk"
+ internal="reg_fpga_voltage_sens.clk"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_rx_read"
- internal="reg_eth1g_II_bsn_monitor_v2_rx.read"
+ name="reg_fpga_voltage_sens_read"
+ internal="reg_fpga_voltage_sens.read"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_rx_readdata"
- internal="reg_eth1g_II_bsn_monitor_v2_rx.readdata"
+ name="reg_fpga_voltage_sens_readdata"
+ internal="reg_fpga_voltage_sens.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_rx_reset"
- internal="reg_eth1g_II_bsn_monitor_v2_rx.reset"
+ name="reg_fpga_voltage_sens_reset"
+ internal="reg_fpga_voltage_sens.reset"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_rx_write"
- internal="reg_eth1g_II_bsn_monitor_v2_rx.write"
+ name="reg_fpga_voltage_sens_write"
+ internal="reg_fpga_voltage_sens.write"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_rx_writedata"
- internal="reg_eth1g_II_bsn_monitor_v2_rx.writedata"
+ name="reg_fpga_voltage_sens_writedata"
+ internal="reg_fpga_voltage_sens.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_tx_address"
- internal="reg_eth1g_II_bsn_monitor_v2_tx.address"
+ name="reg_hdr_dat_eth_0_address"
+ internal="reg_hdr_dat_eth_0.address"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_tx_clk"
- internal="reg_eth1g_II_bsn_monitor_v2_tx.clk"
+ name="reg_hdr_dat_eth_0_clk"
+ internal="reg_hdr_dat_eth_0.clk"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_tx_read"
- internal="reg_eth1g_II_bsn_monitor_v2_tx.read"
+ name="reg_hdr_dat_eth_0_read"
+ internal="reg_hdr_dat_eth_0.read"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_tx_readdata"
- internal="reg_eth1g_II_bsn_monitor_v2_tx.readdata"
+ name="reg_hdr_dat_eth_0_readdata"
+ internal="reg_hdr_dat_eth_0.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_tx_reset"
- internal="reg_eth1g_II_bsn_monitor_v2_tx.reset"
+ name="reg_hdr_dat_eth_0_reset"
+ internal="reg_hdr_dat_eth_0.reset"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_tx_write"
- internal="reg_eth1g_II_bsn_monitor_v2_tx.write"
+ name="reg_hdr_dat_eth_0_write"
+ internal="reg_hdr_dat_eth_0.write"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_tx_writedata"
- internal="reg_eth1g_II_bsn_monitor_v2_tx.writedata"
+ name="reg_hdr_dat_eth_0_writedata"
+ internal="reg_hdr_dat_eth_0.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_hdr_dat_address"
- internal="reg_eth1g_II_hdr_dat.address"
+ name="reg_hdr_dat_eth_1_address"
+ internal="reg_hdr_dat_eth_1.address"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_hdr_dat_clk"
- internal="reg_eth1g_II_hdr_dat.clk"
+ name="reg_hdr_dat_eth_1_clk"
+ internal="reg_hdr_dat_eth_1.clk"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_hdr_dat_read"
- internal="reg_eth1g_II_hdr_dat.read"
+ name="reg_hdr_dat_eth_1_read"
+ internal="reg_hdr_dat_eth_1.read"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_hdr_dat_readdata"
- internal="reg_eth1g_II_hdr_dat.readdata"
+ name="reg_hdr_dat_eth_1_readdata"
+ internal="reg_hdr_dat_eth_1.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_hdr_dat_reset"
- internal="reg_eth1g_II_hdr_dat.reset"
+ name="reg_hdr_dat_eth_1_reset"
+ internal="reg_hdr_dat_eth_1.reset"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_hdr_dat_write"
- internal="reg_eth1g_II_hdr_dat.write"
+ name="reg_hdr_dat_eth_1_write"
+ internal="reg_hdr_dat_eth_1.write"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_hdr_dat_writedata"
- internal="reg_eth1g_II_hdr_dat.writedata"
+ name="reg_hdr_dat_eth_1_writedata"
+ internal="reg_hdr_dat_eth_1.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_rx_address"
- internal="reg_eth1g_II_strobe_total_count_rx.address"
+ name="reg_heater_address"
+ internal="reg_heater.address"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_rx_clk"
- internal="reg_eth1g_II_strobe_total_count_rx.clk"
+ name="reg_heater_clk"
+ internal="reg_heater.clk"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_rx_read"
- internal="reg_eth1g_II_strobe_total_count_rx.read"
+ name="reg_heater_read"
+ internal="reg_heater.read"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_rx_readdata"
- internal="reg_eth1g_II_strobe_total_count_rx.readdata"
+ name="reg_heater_readdata"
+ internal="reg_heater.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_rx_reset"
- internal="reg_eth1g_II_strobe_total_count_rx.reset"
+ name="reg_heater_reset"
+ internal="reg_heater.reset"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_rx_write"
- internal="reg_eth1g_II_strobe_total_count_rx.write"
+ name="reg_heater_write"
+ internal="reg_heater.write"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_rx_writedata"
- internal="reg_eth1g_II_strobe_total_count_rx.writedata"
+ name="reg_heater_writedata"
+ internal="reg_heater.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_tx_address"
- internal="reg_eth1g_II_strobe_total_count_tx.address"
+ name="reg_io_ddr_mb_i_address"
+ internal="reg_io_ddr_MB_I.address"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_tx_clk"
- internal="reg_eth1g_II_strobe_total_count_tx.clk"
+ name="reg_io_ddr_mb_i_clk"
+ internal="reg_io_ddr_MB_I.clk"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_tx_read"
- internal="reg_eth1g_II_strobe_total_count_tx.read"
+ name="reg_io_ddr_mb_i_read"
+ internal="reg_io_ddr_MB_I.read"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_tx_readdata"
- internal="reg_eth1g_II_strobe_total_count_tx.readdata"
+ name="reg_io_ddr_mb_i_readdata"
+ internal="reg_io_ddr_MB_I.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_tx_reset"
- internal="reg_eth1g_II_strobe_total_count_tx.reset"
+ name="reg_io_ddr_mb_i_reset"
+ internal="reg_io_ddr_MB_I.reset"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_tx_write"
- internal="reg_eth1g_II_strobe_total_count_tx.write"
+ name="reg_io_ddr_mb_i_write"
+ internal="reg_io_ddr_MB_I.write"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_tx_writedata"
- internal="reg_eth1g_II_strobe_total_count_tx.writedata"
+ name="reg_io_ddr_mb_i_writedata"
+ internal="reg_io_ddr_MB_I.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_temp_sens_address"
- internal="reg_fpga_temp_sens.address"
+ name="reg_io_ddr_mb_ii_address"
+ internal="reg_io_ddr_MB_II.address"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_temp_sens_clk"
- internal="reg_fpga_temp_sens.clk"
+ name="reg_io_ddr_mb_ii_clk"
+ internal="reg_io_ddr_MB_II.clk"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_temp_sens_read"
- internal="reg_fpga_temp_sens.read"
+ name="reg_io_ddr_mb_ii_read"
+ internal="reg_io_ddr_MB_II.read"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_temp_sens_readdata"
- internal="reg_fpga_temp_sens.readdata"
+ name="reg_io_ddr_mb_ii_readdata"
+ internal="reg_io_ddr_MB_II.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_temp_sens_reset"
- internal="reg_fpga_temp_sens.reset"
+ name="reg_io_ddr_mb_ii_reset"
+ internal="reg_io_ddr_MB_II.reset"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_temp_sens_write"
- internal="reg_fpga_temp_sens.write"
+ name="reg_io_ddr_mb_ii_write"
+ internal="reg_io_ddr_MB_II.write"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_temp_sens_writedata"
- internal="reg_fpga_temp_sens.writedata"
+ name="reg_io_ddr_mb_ii_writedata"
+ internal="reg_io_ddr_MB_II.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_voltage_sens_address"
- internal="reg_fpga_voltage_sens.address"
+ name="reg_mmdp_ctrl_address"
+ internal="reg_mmdp_ctrl.address"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_voltage_sens_clk"
- internal="reg_fpga_voltage_sens.clk"
+ name="reg_mmdp_ctrl_clk"
+ internal="reg_mmdp_ctrl.clk"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_voltage_sens_read"
- internal="reg_fpga_voltage_sens.read"
+ name="reg_mmdp_ctrl_read"
+ internal="reg_mmdp_ctrl.read"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_voltage_sens_readdata"
- internal="reg_fpga_voltage_sens.readdata"
+ name="reg_mmdp_ctrl_readdata"
+ internal="reg_mmdp_ctrl.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_voltage_sens_reset"
- internal="reg_fpga_voltage_sens.reset"
+ name="reg_mmdp_ctrl_reset"
+ internal="reg_mmdp_ctrl.reset"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_voltage_sens_write"
- internal="reg_fpga_voltage_sens.write"
+ name="reg_mmdp_ctrl_write"
+ internal="reg_mmdp_ctrl.write"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_voltage_sens_writedata"
- internal="reg_fpga_voltage_sens.writedata"
+ name="reg_mmdp_ctrl_writedata"
+ internal="reg_mmdp_ctrl.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_heater_address"
- internal="reg_heater.address"
+ name="reg_mmdp_data_address"
+ internal="reg_mmdp_data.address"
type="conduit"
dir="end" />
<interface
- name="reg_heater_clk"
- internal="reg_heater.clk"
+ name="reg_mmdp_data_clk"
+ internal="reg_mmdp_data.clk"
type="conduit"
dir="end" />
<interface
- name="reg_heater_read"
- internal="reg_heater.read"
+ name="reg_mmdp_data_read"
+ internal="reg_mmdp_data.read"
type="conduit"
dir="end" />
<interface
- name="reg_heater_readdata"
- internal="reg_heater.readdata"
+ name="reg_mmdp_data_readdata"
+ internal="reg_mmdp_data.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_heater_reset"
- internal="reg_heater.reset"
+ name="reg_mmdp_data_reset"
+ internal="reg_mmdp_data.reset"
type="conduit"
dir="end" />
<interface
- name="reg_heater_write"
- internal="reg_heater.write"
+ name="reg_mmdp_data_write"
+ internal="reg_mmdp_data.write"
type="conduit"
dir="end" />
<interface
- name="reg_heater_writedata"
- internal="reg_heater.writedata"
+ name="reg_mmdp_data_writedata"
+ internal="reg_mmdp_data.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_i_address"
- internal="reg_io_ddr_MB_I.address"
+ name="reg_remu_address"
+ internal="reg_remu.address"
type="conduit"
dir="end" />
+ <interface name="reg_remu_clk" internal="reg_remu.clk" type="conduit" dir="end" />
<interface
- name="reg_io_ddr_mb_i_clk"
- internal="reg_io_ddr_MB_I.clk"
+ name="reg_remu_read"
+ internal="reg_remu.read"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_i_read"
- internal="reg_io_ddr_MB_I.read"
+ name="reg_remu_readdata"
+ internal="reg_remu.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_i_readdata"
- internal="reg_io_ddr_MB_I.readdata"
+ name="reg_remu_reset"
+ internal="reg_remu.reset"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_i_reset"
- internal="reg_io_ddr_MB_I.reset"
+ name="reg_remu_write"
+ internal="reg_remu.write"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_i_write"
- internal="reg_io_ddr_MB_I.write"
+ name="reg_remu_writedata"
+ internal="reg_remu.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_i_writedata"
- internal="reg_io_ddr_MB_I.writedata"
+ name="reg_strobe_total_count_rx_eth_0_address"
+ internal="reg_strobe_total_count_rx_eth_0.address"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_ii_address"
- internal="reg_io_ddr_MB_II.address"
+ name="reg_strobe_total_count_rx_eth_0_clk"
+ internal="reg_strobe_total_count_rx_eth_0.clk"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_ii_clk"
- internal="reg_io_ddr_MB_II.clk"
+ name="reg_strobe_total_count_rx_eth_0_read"
+ internal="reg_strobe_total_count_rx_eth_0.read"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_ii_read"
- internal="reg_io_ddr_MB_II.read"
+ name="reg_strobe_total_count_rx_eth_0_readdata"
+ internal="reg_strobe_total_count_rx_eth_0.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_ii_readdata"
- internal="reg_io_ddr_MB_II.readdata"
+ name="reg_strobe_total_count_rx_eth_0_reset"
+ internal="reg_strobe_total_count_rx_eth_0.reset"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_ii_reset"
- internal="reg_io_ddr_MB_II.reset"
+ name="reg_strobe_total_count_rx_eth_0_write"
+ internal="reg_strobe_total_count_rx_eth_0.write"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_ii_write"
- internal="reg_io_ddr_MB_II.write"
+ name="reg_strobe_total_count_rx_eth_0_writedata"
+ internal="reg_strobe_total_count_rx_eth_0.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_ii_writedata"
- internal="reg_io_ddr_MB_II.writedata"
+ name="reg_strobe_total_count_rx_eth_1_address"
+ internal="reg_strobe_total_count_rx_eth_1.address"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_address"
- internal="reg_mmdp_ctrl.address"
+ name="reg_strobe_total_count_rx_eth_1_clk"
+ internal="reg_strobe_total_count_rx_eth_1.clk"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_clk"
- internal="reg_mmdp_ctrl.clk"
+ name="reg_strobe_total_count_rx_eth_1_read"
+ internal="reg_strobe_total_count_rx_eth_1.read"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_read"
- internal="reg_mmdp_ctrl.read"
+ name="reg_strobe_total_count_rx_eth_1_readdata"
+ internal="reg_strobe_total_count_rx_eth_1.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_readdata"
- internal="reg_mmdp_ctrl.readdata"
+ name="reg_strobe_total_count_rx_eth_1_reset"
+ internal="reg_strobe_total_count_rx_eth_1.reset"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_reset"
- internal="reg_mmdp_ctrl.reset"
+ name="reg_strobe_total_count_rx_eth_1_write"
+ internal="reg_strobe_total_count_rx_eth_1.write"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_write"
- internal="reg_mmdp_ctrl.write"
+ name="reg_strobe_total_count_rx_eth_1_writedata"
+ internal="reg_strobe_total_count_rx_eth_1.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_writedata"
- internal="reg_mmdp_ctrl.writedata"
+ name="reg_strobe_total_count_tx_eth_0_address"
+ internal="reg_strobe_total_count_tx_eth_0.address"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_address"
- internal="reg_mmdp_data.address"
+ name="reg_strobe_total_count_tx_eth_0_clk"
+ internal="reg_strobe_total_count_tx_eth_0.clk"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_clk"
- internal="reg_mmdp_data.clk"
+ name="reg_strobe_total_count_tx_eth_0_read"
+ internal="reg_strobe_total_count_tx_eth_0.read"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_read"
- internal="reg_mmdp_data.read"
+ name="reg_strobe_total_count_tx_eth_0_readdata"
+ internal="reg_strobe_total_count_tx_eth_0.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_readdata"
- internal="reg_mmdp_data.readdata"
+ name="reg_strobe_total_count_tx_eth_0_reset"
+ internal="reg_strobe_total_count_tx_eth_0.reset"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_reset"
- internal="reg_mmdp_data.reset"
+ name="reg_strobe_total_count_tx_eth_0_write"
+ internal="reg_strobe_total_count_tx_eth_0.write"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_write"
- internal="reg_mmdp_data.write"
+ name="reg_strobe_total_count_tx_eth_0_writedata"
+ internal="reg_strobe_total_count_tx_eth_0.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_writedata"
- internal="reg_mmdp_data.writedata"
+ name="reg_strobe_total_count_tx_eth_1_address"
+ internal="reg_strobe_total_count_tx_eth_1.address"
type="conduit"
dir="end" />
<interface
- name="reg_remu_address"
- internal="reg_remu.address"
+ name="reg_strobe_total_count_tx_eth_1_clk"
+ internal="reg_strobe_total_count_tx_eth_1.clk"
type="conduit"
dir="end" />
- <interface name="reg_remu_clk" internal="reg_remu.clk" type="conduit" dir="end" />
<interface
- name="reg_remu_read"
- internal="reg_remu.read"
+ name="reg_strobe_total_count_tx_eth_1_read"
+ internal="reg_strobe_total_count_tx_eth_1.read"
type="conduit"
dir="end" />
<interface
- name="reg_remu_readdata"
- internal="reg_remu.readdata"
+ name="reg_strobe_total_count_tx_eth_1_readdata"
+ internal="reg_strobe_total_count_tx_eth_1.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_remu_reset"
- internal="reg_remu.reset"
+ name="reg_strobe_total_count_tx_eth_1_reset"
+ internal="reg_strobe_total_count_tx_eth_1.reset"
type="conduit"
dir="end" />
<interface
- name="reg_remu_write"
- internal="reg_remu.write"
+ name="reg_strobe_total_count_tx_eth_1_write"
+ internal="reg_strobe_total_count_tx_eth_1.write"
type="conduit"
dir="end" />
<interface
- name="reg_remu_writedata"
- internal="reg_remu.writedata"
+ name="reg_strobe_total_count_tx_eth_1_writedata"
+ internal="reg_strobe_total_count_tx_eth_1.writedata"
type="conduit"
dir="end" />
<interface
@@ -3258,7 +3258,7 @@
type="conduit"
dir="end" />
<module
- name="avs2_eth_coe_1"
+ name="avs_eth_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -4059,7 +4059,7 @@
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
- <value>avs2_eth_coe_1.mms_reg</value>
+ <value>avs_eth_0.mms_reg</value>
</entry>
<entry>
<key>associatedClock</key>
@@ -5565,7 +5565,7 @@
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
- <value>avs2_eth_coe_1.mms_reg</value>
+ <value>avs_eth_0.mms_reg</value>
</entry>
<entry>
<key>associatedClock</key>
@@ -6200,37 +6200,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_avs2_eth_coe_1</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_avs2_eth_coe_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_avs2_eth_coe_1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_avs2_eth_coe_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_avs2_eth_coe_1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_avs2_eth_coe_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_avs2_eth_coe_1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_avs2_eth_coe_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="avs_eth_0"
+ name="avs_eth_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -7031,7 +7031,7 @@
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
- <value>avs_eth_0.mms_reg</value>
+ <value>avs_eth_1.mms_reg</value>
</entry>
<entry>
<key>associatedClock</key>
@@ -8537,7 +8537,7 @@
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
- <value>avs_eth_0.mms_reg</value>
+ <value>avs_eth_1.mms_reg</value>
</entry>
<entry>
<key>associatedClock</key>
@@ -9172,30 +9172,30 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_avs2_eth_coe_0</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_avs2_eth_coe_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_avs2_eth_coe_0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_avs2_eth_coe_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_avs2_eth_coe_0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_avs2_eth_coe_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_avs2_eth_coe_0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_avs2_eth_coe_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -10780,11 +10780,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_eth_0.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_strobe_total_count_rx_eth_0.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_tx_eth_0.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_strobe_total_count_tx_eth_0.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_hdr_dat_eth_0.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x18000' end='0x1A000' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0x1A000' end='0x1B000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x1B000' end='0x1C000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x1C800' end='0x1C900' datawidth='32' /><slave name='reg_strobe_total_count_rx_eth_1.mem' start='0x1C900' end='0x1C980' datawidth='32' /><slave name='reg_strobe_total_count_tx_eth_1.mem' start='0x1C980' end='0x1CA00' datawidth='32' /><slave name='reg_hdr_dat_eth_1.mem' start='0x1CA00' end='0x1CA80' datawidth='32' /><slave name='reg_diag_bg_eth_0.mem' start='0x1CA80' end='0x1CB00' datawidth='32' /><slave name='reg_heater.mem' start='0x1CB00' end='0x1CB80' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x1CB80' end='0x1CC00' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x1CC00' end='0x1CC80' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x1CC80' end='0x1CD00' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x1CD00' end='0x1CD40' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x1CD40' end='0x1CD80' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1CD80' end='0x1CDC0' datawidth='32' /><slave name='reg_diag_bg_eth_1.mem' start='0x1CDC0' end='0x1CDE0' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_eth_1.mem' start='0x1CDE0' end='0x1CE00' datawidth='32' /><slave name='reg_bsn_monitor_v2_tx_eth_1.mem' start='0x1CE00' end='0x1CE20' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x1CE20' end='0x1CE40' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x1CE40' end='0x1CE60' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x1CE60' end='0x1CE80' datawidth='32' /><slave name='reg_epcs.mem' start='0x1CE80' end='0x1CEA0' datawidth='32' /><slave name='reg_remu.mem' start='0x1CEA0' end='0x1CEC0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x1CEC0' end='0x1CEE0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x1CEE0' end='0x1CEF0' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x1CEF0' end='0x1CF00' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x1CF00' end='0x1CF10' datawidth='32' /><slave name='pio_pps.mem' start='0x1CF10' end='0x1CF20' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x1CF20' end='0x1CF28' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x1CF28' end='0x1CF30' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x1CF30' end='0x1CF38' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x1CF38' end='0x1CF40' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x1CF40' end='0x1CF48' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1CF48' end='0x1CF50' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>1</value>
+ <value>24</value>
</entry>
</consumedSystemInfos>
</value>
@@ -10818,11 +10818,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value></value>
+ <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>1</value>
+ <value>18</value>
</entry>
</consumedSystemInfos>
</value>
@@ -11336,7 +11336,7 @@
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
- <value>nios2_gen2_0.data_master</value>
+ <value>cpu_0.data_master</value>
</entry>
<entry>
<key>associatedClock</key>
@@ -11469,9 +11469,21 @@
<key>embeddedsw.configuration.hideDevice</key>
<value>1</value>
</entry>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>true</value>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
</entry>
<entry>
<key>qsys.ui.connect</key>
@@ -28595,7 +28607,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_bsn_monitor_v2_rx_eth_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -28674,7 +28686,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28743,7 +28755,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28972,7 +28984,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29150,11 +29162,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -29254,7 +29266,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29293,21 +29305,17 @@
</ports>
<assignments>
<assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -29323,7 +29331,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29347,7 +29355,6 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
- <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -29552,7 +29559,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29706,37 +29713,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_source"
+ name="reg_bsn_monitor_v2_rx_eth_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29815,7 +29822,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29884,7 +29891,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30113,7 +30120,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30291,11 +30298,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -30395,7 +30402,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30464,7 +30471,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30693,7 +30700,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30847,37 +30854,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_bsn_source</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_bg_10gbe"
+ name="reg_bsn_monitor_v2_tx_eth_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30956,7 +30963,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31025,7 +31032,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31254,7 +31261,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31432,11 +31439,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -31536,7 +31543,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31605,7 +31612,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31834,7 +31841,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31988,37 +31995,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_bg_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_10gbe"
+ name="reg_bsn_monitor_v2_tx_eth_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -32097,7 +32104,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32166,7 +32173,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32395,7 +32402,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32573,11 +32580,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -32677,7 +32684,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32746,7 +32753,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32975,7 +32982,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33129,37 +33136,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_bsn"
+ name="reg_bsn_scheduler"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33238,7 +33245,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33307,7 +33314,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16384</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -33536,7 +33543,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33714,11 +33721,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>14</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -33818,7 +33825,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33887,7 +33894,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16384</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34116,7 +34123,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34270,37 +34277,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_ddr_MB_I"
+ name="reg_bsn_source"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34379,7 +34386,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34448,7 +34455,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34677,7 +34684,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34855,11 +34862,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -34959,7 +34966,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35028,7 +35035,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35257,7 +35264,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35411,37 +35418,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_source</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_ddr_MB_II"
+ name="reg_diag_bg_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -35520,7 +35527,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35589,7 +35596,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35818,7 +35825,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35996,11 +36003,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -36100,7 +36107,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36169,7 +36176,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36398,7 +36405,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36552,37 +36559,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_bg_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_rx_seq_10gbe"
+ name="reg_diag_bg_eth_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -37693,37 +37700,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_bg_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_rx_seq_ddr_MB_I"
+ name="reg_diag_bg_eth_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -38834,37 +38841,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_bg_eth_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_eth_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_eth_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_eth_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_rx_seq_ddr_MB_II"
+ name="reg_diag_data_buffer_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -38943,7 +38950,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39012,7 +39019,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39241,7 +39248,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39419,11 +39426,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -39523,7 +39530,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39592,7 +39599,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39821,7 +39828,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39975,37 +39982,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_tx_seq_10gbe"
+ name="reg_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -40084,7 +40091,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40153,7 +40160,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>16384</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -40382,7 +40389,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40560,11 +40567,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>14</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -40664,7 +40671,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40733,7 +40740,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>16384</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -40962,7 +40969,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41116,37 +41123,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_tx_seq_ddr_MB_I"
+ name="reg_diag_data_buffer_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -41225,7 +41232,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41294,7 +41301,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -41523,7 +41530,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41701,11 +41708,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -41805,7 +41812,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41874,7 +41881,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -42103,7 +42110,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42257,37 +42264,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_tx_seq_ddr_MB_II"
+ name="reg_diag_data_buffer_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -42366,7 +42373,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42435,7 +42442,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -42664,7 +42671,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42842,11 +42849,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -42946,7 +42953,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43015,7 +43022,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -43244,7 +43251,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43398,37 +43405,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_diag_rx_seq_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -43507,7 +43514,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43576,7 +43583,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -43805,7 +43812,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43983,11 +43990,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -44087,7 +44094,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44156,7 +44163,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -44385,7 +44392,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44539,37 +44546,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_diag_rx_seq_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -44648,7 +44655,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44717,7 +44724,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -44946,7 +44953,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -45124,11 +45131,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -45228,7 +45235,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -45297,7 +45304,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -45526,7 +45533,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -45680,37 +45687,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_diag_rx_seq_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -46821,37 +46828,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth10g_back0"
+ name="reg_diag_tx_seq_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -46930,7 +46937,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -46999,7 +47006,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -47228,7 +47235,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47406,11 +47413,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -47510,7 +47517,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47579,7 +47586,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -47808,7 +47815,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47962,37 +47969,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth10g_back0</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth10g_back1"
+ name="reg_diag_tx_seq_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -48071,7 +48078,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48140,7 +48147,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -48369,7 +48376,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48547,11 +48554,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -48651,7 +48658,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48720,7 +48727,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -48949,7 +48956,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49103,37 +49110,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth10g_back1</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth10g_qsfp_ring"
+ name="reg_diag_tx_seq_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -49212,7 +49219,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49281,7 +49288,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -49510,7 +49517,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49688,11 +49695,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -49792,7 +49799,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49861,7 +49868,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -50090,7 +50097,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -50244,37 +50251,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth10g_qsfp_ring</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_II_bg_ctrl"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -50353,7 +50360,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -50422,7 +50429,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -50651,7 +50658,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -50829,11 +50836,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -50933,7 +50940,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51002,7 +51009,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -51231,7 +51238,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51385,37 +51392,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_II_bsn_monitor_v2_rx"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -51494,7 +51501,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51563,7 +51570,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -51792,7 +51799,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51970,11 +51977,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -52074,7 +52081,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52143,7 +52150,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -52372,7 +52379,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52526,37 +52533,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_II_bsn_monitor_v2_tx"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -53667,37 +53674,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_II_hdr_dat"
+ name="reg_eth10g_back0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -53776,7 +53783,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -53845,7 +53852,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -54074,7 +54081,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54252,11 +54259,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -54356,7 +54363,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54425,7 +54432,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -54654,7 +54661,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54808,37 +54815,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth10g_back0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_II_strobe_total_count_rx"
+ name="reg_eth10g_back1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -54917,7 +54924,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54986,7 +54993,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -55215,7 +55222,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55393,11 +55400,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -55497,7 +55504,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55566,7 +55573,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -55795,7 +55802,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55949,37 +55956,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth10g_back1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_II_strobe_total_count_tx"
+ name="reg_eth10g_qsfp_ring"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -56058,7 +56065,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -56127,7 +56134,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -56356,7 +56363,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -56534,11 +56541,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -56638,7 +56645,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -56707,7 +56714,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -56936,7 +56943,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -57090,37 +57097,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth10g_qsfp_ring</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_I_bg_ctrl"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -57199,7 +57206,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -57268,7 +57275,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -57497,7 +57504,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -57675,11 +57682,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -57779,7 +57786,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -57848,7 +57855,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -58077,7 +58084,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -58231,37 +58238,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_I_bsn_monitor_v2_rx"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -58340,7 +58347,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -58409,7 +58416,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -58638,7 +58645,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -58816,11 +58823,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -58920,7 +58927,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -58989,7 +58996,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -59218,7 +59225,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -59372,37 +59379,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_I_bsn_monitor_v2_tx"
+ name="reg_hdr_dat_eth_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -59481,7 +59488,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -59550,7 +59557,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -59779,7 +59786,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -59957,11 +59964,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -60061,7 +60068,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -60130,7 +60137,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -60359,7 +60366,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -60513,37 +60520,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_hdr_dat_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_hdr_dat_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_hdr_dat_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_hdr_dat_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_hdr_dat_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_hdr_dat_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_hdr_dat_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_I_hdr_dat"
+ name="reg_hdr_dat_eth_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -60622,7 +60629,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -60691,7 +60698,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -60920,7 +60927,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61098,11 +61105,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -61202,7 +61209,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61271,7 +61278,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -61500,7 +61507,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61654,37 +61661,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_hdr_dat_eth_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_hdr_dat_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_hdr_dat_eth_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_hdr_dat_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_hdr_dat_eth_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_hdr_dat_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_hdr_dat_eth_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_I_strobe_total_count_rx"
+ name="reg_heater"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -61763,7 +61770,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61832,7 +61839,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -62061,7 +62068,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -62239,11 +62246,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -62343,7 +62350,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -62412,7 +62419,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -62641,7 +62648,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -62795,37 +62802,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_heater</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_heater</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_heater</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_heater</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_heater</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_heater</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_heater</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_I_strobe_total_count_tx"
+ name="reg_io_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -62904,7 +62911,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -62973,7 +62980,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -63202,7 +63209,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -63380,11 +63387,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>18</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -63484,7 +63491,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -63553,7 +63560,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -63782,7 +63789,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -63936,37 +63943,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_io_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_io_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -64045,7 +64052,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -64114,7 +64121,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -64343,7 +64350,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -64521,11 +64528,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>18</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -64625,7 +64632,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -64694,7 +64701,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -64923,7 +64930,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -65077,37 +65084,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_io_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -65186,7 +65193,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -65255,7 +65262,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -65484,7 +65491,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -65662,11 +65669,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -65766,7 +65773,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -65835,7 +65842,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -66064,7 +66071,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -66218,37 +66225,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_heater"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -66327,7 +66334,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -66396,7 +66403,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -66625,7 +66632,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -66803,11 +66810,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -66907,7 +66914,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -66976,7 +66983,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -67205,7 +67212,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -67359,37 +67366,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_heater</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_heater</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_heater</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_heater</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_heater</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_heater</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_heater</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_io_ddr_MB_I"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -67468,7 +67475,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>16</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -67537,7 +67544,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>262144</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -67766,7 +67773,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -67944,11 +67951,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>18</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -68048,7 +68055,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>16</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -68117,7 +68124,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>262144</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -68346,7 +68353,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -68500,37 +68507,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_io_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_io_ddr_MB_II"
+ name="reg_strobe_total_count_rx_eth_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -68609,7 +68616,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>16</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -68678,7 +68685,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>262144</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -68907,7 +68914,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69085,11 +69092,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>18</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -69189,7 +69196,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>16</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69258,7 +69265,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>262144</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -69487,7 +69494,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69641,37 +69648,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_io_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_strobe_total_count_rx_eth_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -69750,7 +69757,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69819,7 +69826,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -70048,7 +70055,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -70226,11 +70233,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -70330,7 +70337,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -70399,7 +70406,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -70628,7 +70635,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -70782,37 +70789,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_strobe_total_count_tx_eth_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -70891,7 +70898,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -70960,7 +70967,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -71189,7 +71196,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -71367,11 +71374,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -71471,7 +71478,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -71540,7 +71547,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -71769,7 +71776,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -71923,37 +71930,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_strobe_total_count_tx_eth_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -72032,7 +72039,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -72101,7 +72108,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -72330,7 +72337,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -72508,11 +72515,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -72612,7 +72619,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -72681,7 +72688,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -72910,7 +72917,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -73064,30 +73071,30 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -81266,7 +81273,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_I_bg_ctrl.mem">
+ end="reg_diag_bg_eth_0.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001ca80" />
<parameter name="defaultConnection" value="false" />
@@ -81286,7 +81293,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_II_hdr_dat.mem">
+ end="reg_hdr_dat_eth_1.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001ca00" />
<parameter name="defaultConnection" value="false" />
@@ -81306,7 +81313,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_II_bsn_monitor_v2_tx.mem">
+ end="reg_bsn_monitor_v2_tx_eth_1.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001ce00" />
<parameter name="defaultConnection" value="false" />
@@ -81326,7 +81333,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_II_strobe_total_count_tx.mem">
+ end="reg_strobe_total_count_tx_eth_1.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001c980" />
<parameter name="defaultConnection" value="false" />
@@ -81346,7 +81353,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_II_bsn_monitor_v2_rx.mem">
+ end="reg_bsn_monitor_v2_rx_eth_1.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001cde0" />
<parameter name="defaultConnection" value="false" />
@@ -81366,7 +81373,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_II_strobe_total_count_rx.mem">
+ end="reg_strobe_total_count_rx_eth_1.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001c900" />
<parameter name="defaultConnection" value="false" />
@@ -81386,7 +81393,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_I_hdr_dat.mem">
+ end="reg_hdr_dat_eth_0.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3400" />
<parameter name="defaultConnection" value="false" />
@@ -81406,7 +81413,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_I_bsn_monitor_v2_tx.mem">
+ end="reg_bsn_monitor_v2_tx_eth_0.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3080" />
<parameter name="defaultConnection" value="false" />
@@ -81426,7 +81433,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_I_strobe_total_count_tx.mem">
+ end="reg_strobe_total_count_tx_eth_0.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3200" />
<parameter name="defaultConnection" value="false" />
@@ -81446,7 +81453,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_I_bsn_monitor_v2_rx.mem">
+ end="reg_bsn_monitor_v2_rx_eth_0.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0080" />
<parameter name="defaultConnection" value="false" />
@@ -81466,7 +81473,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_I_strobe_total_count_rx.mem">
+ end="reg_strobe_total_count_rx_eth_0.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0200" />
<parameter name="defaultConnection" value="false" />
@@ -81486,7 +81493,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_II_bg_ctrl.mem">
+ end="reg_diag_bg_eth_1.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001cdc0" />
<parameter name="defaultConnection" value="false" />
@@ -81526,7 +81533,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="avs2_eth_coe_1.mms_ram">
+ end="avs_eth_1.mms_ram">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001a000" />
<parameter name="defaultConnection" value="false" />
@@ -81566,7 +81573,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="avs2_eth_coe_1.mms_reg">
+ end="avs_eth_1.mms_reg">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3040" />
<parameter name="defaultConnection" value="false" />
@@ -81606,7 +81613,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="avs2_eth_coe_1.mms_tse">
+ end="avs_eth_1.mms_tse">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x1000" />
<parameter name="defaultConnection" value="false" />
@@ -81732,7 +81739,7 @@
start="clk_0.clk"
end="onchip_memory2_0.clk1" />
<connection kind="clock" version="19.4" start="clk_0.clk" end="avs_eth_0.mm" />
- <connection kind="clock" version="19.4" start="clk_0.clk" end="avs2_eth_coe_1.mm" />
+ <connection kind="clock" version="19.4" start="clk_0.clk" end="avs_eth_1.mm" />
<connection
kind="clock"
version="19.4"
@@ -81929,62 +81936,62 @@
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_I_bg_ctrl.system" />
+ end="reg_diag_bg_eth_0.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_II_hdr_dat.system" />
+ end="reg_hdr_dat_eth_1.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_II_bsn_monitor_v2_tx.system" />
+ end="reg_bsn_monitor_v2_tx_eth_1.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_II_strobe_total_count_tx.system" />
+ end="reg_strobe_total_count_tx_eth_1.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_II_bsn_monitor_v2_rx.system" />
+ end="reg_bsn_monitor_v2_rx_eth_1.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_II_strobe_total_count_rx.system" />
+ end="reg_strobe_total_count_rx_eth_1.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_I_hdr_dat.system" />
+ end="reg_hdr_dat_eth_0.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_I_bsn_monitor_v2_tx.system" />
+ end="reg_bsn_monitor_v2_tx_eth_0.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_I_strobe_total_count_tx.system" />
+ end="reg_strobe_total_count_tx_eth_0.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_I_bsn_monitor_v2_rx.system" />
+ end="reg_bsn_monitor_v2_rx_eth_0.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_I_strobe_total_count_rx.system" />
+ end="reg_strobe_total_count_rx_eth_0.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_II_bg_ctrl.system" />
+ end="reg_diag_bg_eth_1.system" />
<connection
kind="interrupt"
version="19.4"
@@ -81996,7 +82003,7 @@
kind="interrupt"
version="19.4"
start="cpu_0.irq"
- end="avs2_eth_coe_1.interrupt">
+ end="avs_eth_1.interrupt">
<parameter name="irqNumber" value="1" />
</connection>
<connection
@@ -82018,7 +82025,7 @@
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="avs2_eth_coe_1.mm_reset" />
+ end="avs_eth_1.mm_reset" />
<connection kind="reset" version="19.4" start="clk_0.clk_reset" end="cpu_0.reset" />
<connection
kind="reset"
@@ -82264,62 +82271,62 @@
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_I_bg_ctrl.system_reset" />
+ end="reg_diag_bg_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_II_hdr_dat.system_reset" />
+ end="reg_hdr_dat_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_II_bsn_monitor_v2_tx.system_reset" />
+ end="reg_bsn_monitor_v2_tx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_II_strobe_total_count_tx.system_reset" />
+ end="reg_strobe_total_count_tx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_II_bsn_monitor_v2_rx.system_reset" />
+ end="reg_bsn_monitor_v2_rx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_II_strobe_total_count_rx.system_reset" />
+ end="reg_strobe_total_count_rx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_I_hdr_dat.system_reset" />
+ end="reg_hdr_dat_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_I_bsn_monitor_v2_tx.system_reset" />
+ end="reg_bsn_monitor_v2_tx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_I_strobe_total_count_tx.system_reset" />
+ end="reg_strobe_total_count_tx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_I_bsn_monitor_v2_rx.system_reset" />
+ end="reg_bsn_monitor_v2_rx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_I_strobe_total_count_rx.system_reset" />
+ end="reg_strobe_total_count_rx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_II_bg_ctrl.system_reset" />
+ end="reg_diag_bg_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
@@ -82329,7 +82336,7 @@
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="avs2_eth_coe_1.mm_reset" />
+ end="avs_eth_1.mm_reset" />
<connection
kind="reset"
version="19.4"
@@ -82579,60 +82586,60 @@
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_I_bg_ctrl.system_reset" />
+ end="reg_diag_bg_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_II_hdr_dat.system_reset" />
+ end="reg_hdr_dat_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_II_bsn_monitor_v2_tx.system_reset" />
+ end="reg_bsn_monitor_v2_tx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_II_strobe_total_count_tx.system_reset" />
+ end="reg_strobe_total_count_tx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_II_bsn_monitor_v2_rx.system_reset" />
+ end="reg_bsn_monitor_v2_rx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_II_strobe_total_count_rx.system_reset" />
+ end="reg_strobe_total_count_rx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_I_hdr_dat.system_reset" />
+ end="reg_hdr_dat_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_I_bsn_monitor_v2_tx.system_reset" />
+ end="reg_bsn_monitor_v2_tx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_I_strobe_total_count_tx.system_reset" />
+ end="reg_strobe_total_count_tx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_I_bsn_monitor_v2_rx.system_reset" />
+ end="reg_bsn_monitor_v2_rx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_I_strobe_total_count_rx.system_reset" />
+ end="reg_strobe_total_count_rx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_II_bg_ctrl.system_reset" />
+ end="reg_diag_bg_eth_1.system_reset" />
</system>
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
index 51e59be80c8c12360df285c66c21e97d1814cead..9ef2e859c0b40381b7be2f658235b69743ad4207 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
@@ -116,17 +116,17 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg
index 75e63c809b3dc59ff7d8244e6b00077e122c918b..5e52adba61d3d532022099791d3595e85c91e66c 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg
@@ -95,17 +95,17 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
index 098b2f766dd700f483cc27ecb5f6c62d4fcbb321..cb60b74884f4f480984fcbd7e617ff210149f83a 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
@@ -26,6 +26,12 @@
-- Description:
-- Usage:
-- > run 1 us.
+--
+-- Or try some MM:
+-- > run -a (or run 100 us)
+-- On command line do:
+-- > python $UPE_GEAR/peripherals/util_system_info.py --gn 0 -n 0 -v 5 --sim
+--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
index 5df27443699abb821c26211f077555e86edcc8fd..5934694d5e7e56168d235f222d8088c79145f18f 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2015
+-- Copyright (C) 2022
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -20,6 +20,10 @@
--
-------------------------------------------------------------------------------
+-- Author: Eric Kooistra
+-- Purpose: Test 1GbE-I port using eth_tester
+-- Description:
+
LIBRARY IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
@@ -31,7 +35,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY unb2c_test_1GbE_I IS
GENERIC (
g_design_name : STRING := "unb2c_test_1GbE_I";
- g_design_note : STRING := "Uses only Eth0";
+ g_design_note : STRING := "Uses only eth_0";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..cbeea04e78c6229e6df47973b2e8fd103c8ba85d
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/hdllib.cfg
@@ -0,0 +1,111 @@
+hdl_lib_name = unb2c_test_1GbE_II
+hdl_library_clause_name = unb2c_test_1GbE_II_lib
+hdl_lib_uses_synth = common mm technology unb2c_board unb2c_test
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+hdl_lib_include_ip =
+
+synth_files =
+ unb2c_test_1GbE_II.vhd
+
+test_bench_files =
+ tb_unb2c_test_1GbE_II.vhd
+
+regression_test_vhdl =
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus .
+ ../../quartus .
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+
+quartus_sdc_pre_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+
+quartus_sdc_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+
+quartus_tcl_files =
+ quartus/unb2c_test_1GbE_II_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/qsys_unb2c_test/qsys_unb2c_test.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/quartus/unb2c_test_1GbE_II_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/quartus/unb2c_test_1GbE_II_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ae417258f888c910d593c6ab6e5117615ebbd36f
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/quartus/unb2c_test_1GbE_II_pins.tcl
@@ -0,0 +1,22 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..42010cc38b4233a6194b5154a7aab5c2a65c6881
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
@@ -0,0 +1,89 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author: E. Kooistra
+-- Purpose: Tb to try loading design in simulator
+-- Description:
+-- Usage:
+-- > run 1 us.
+--
+-- Or try some MM:
+-- > run -a (or run 100 us)
+-- On command line do:
+-- > python $UPE_GEAR/peripherals/util_system_info.py --gn 0 -n 0 -v 5 --sim
+--
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_unb2c_test_1GbE_II IS
+END tb_unb2c_test_1GbE_II;
+
+
+ARCHITECTURE tb OF tb_unb2c_test_1GbE_II IS
+
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL wdi : STD_LOGIC := '0';
+
+ SIGNAL eth_clk : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ SIGNAL eth_sgin : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL eth_sgout : STD_LOGIC_VECTOR(1 DOWNTO 0);
+
+BEGIN
+
+ clk <= NOT clk AFTER 5 ns;
+ eth_clk(0) <= NOT eth_clk(0) AFTER 8 ns;
+ eth_clk(1) <= NOT eth_clk(1) AFTER 8 ns;
+
+ eth_sgin <= eth_sgout; -- loopback eth0 and eth1
+
+ u_unb2c_test_1GbE_II : ENTITY work.unb2c_test_1GbE_II
+ GENERIC MAP (
+ g_sim => TRUE
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => wdi,
+ INTA => OPEN,
+ INTB => OPEN,
+
+ -- Others
+ VERSION => "00",
+ ID => "00000000",
+ TESTIO => OPEN,
+
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_sgin,
+ ETH_SGOUT => eth_sgout,
+
+ QSFP_LED => OPEN
+ );
+
+END tb;
+
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d23b4d0257cb230206438a4d81a99aa7d08e452e
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
@@ -0,0 +1,105 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author: Eric Kooistra
+-- Purpose: Test both 1GbE-I and 1GbE-II ports using eth_tester
+-- Description:
+
+LIBRARY IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+
+ENTITY unb2c_test_1GbE_II IS
+ GENERIC (
+ g_design_name : STRING := "unb2c_test_1GbE_II";
+ g_design_note : STRING := "Use eth_0 and eth_1";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
+
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2c_test_1GbE_II;
+
+
+ARCHITECTURE str OF unb2c_test_1GbE_II IS
+
+BEGIN
+ u_revision : ENTITY unb2c_test_lib.unb2c_test
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ QSFP_LED => QSFP_LED
+ );
+END str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
index 10ffc4483c97397219a94129b88720b74fc04850..e922d19d8950ad51c21407c22aa116d21a268f8b 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
@@ -102,17 +102,17 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
index 37ef2d46ea0f70174e026d3a599edd876b4d4768..fea6d6b87148f98902e699b2ad2468291d33d716 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
@@ -100,17 +100,17 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
index 1153dfd5a421d1dce0114c2cca595bd94ed4c2d5..2e6ecb15828c5f04dbf13c536134b4ed36a24ae9 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
@@ -99,19 +99,17 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
-
-
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
index b2e2e2545cca716c0f6c7554fc9e3faad2a32763..ebf094c08a24bdc31eb9c18e7bb52bacde00a331 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
@@ -94,17 +94,17 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index cb6ec2cfe0e446e3715c51d3fca55246da38d3f8..7b42c2b491ba2baa846a7ee47d990590d3d10ea2 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -79,52 +79,52 @@ ENTITY mmm_unb2c_test IS
reg_ppsh_miso : IN t_mem_miso;
-- eth1g ch0
- eth1g_eth0_mm_rst : OUT STD_LOGIC;
- eth1g_eth0_tse_mosi : OUT t_mem_mosi;
- eth1g_eth0_tse_miso : IN t_mem_miso;
- eth1g_eth0_reg_mosi : OUT t_mem_mosi;
- eth1g_eth0_reg_miso : IN t_mem_miso;
- eth1g_eth0_reg_interrupt : IN STD_LOGIC;
- eth1g_eth0_ram_mosi : OUT t_mem_mosi;
- eth1g_eth0_ram_miso : IN t_mem_miso;
-
- reg_eth1g_I_bg_ctrl_copi : OUT t_mem_copi;
- reg_eth1g_I_bg_ctrl_cipo : IN t_mem_cipo;
- reg_eth1g_I_hdr_dat_copi : OUT t_mem_copi;
- reg_eth1g_I_hdr_dat_cipo : IN t_mem_cipo;
- reg_eth1g_I_bsn_monitor_v2_tx_copi : OUT t_mem_copi;
- reg_eth1g_I_bsn_monitor_v2_tx_cipo : IN t_mem_cipo;
- reg_eth1g_I_strobe_total_count_tx_copi : OUT t_mem_copi;
- reg_eth1g_I_strobe_total_count_tx_cipo : IN t_mem_cipo;
-
- reg_eth1g_I_bsn_monitor_v2_rx_copi : OUT t_mem_copi;
- reg_eth1g_I_bsn_monitor_v2_rx_cipo : IN t_mem_cipo;
- reg_eth1g_I_strobe_total_count_rx_copi : OUT t_mem_copi;
- reg_eth1g_I_strobe_total_count_rx_cipo : IN t_mem_cipo;
+ eth_0_mm_rst : OUT STD_LOGIC;
+ eth_0_tse_mosi : OUT t_mem_mosi;
+ eth_0_tse_miso : IN t_mem_miso;
+ eth_0_reg_mosi : OUT t_mem_mosi;
+ eth_0_reg_miso : IN t_mem_miso;
+ eth_0_reg_interrupt : IN STD_LOGIC;
+ eth_0_ram_mosi : OUT t_mem_mosi;
+ eth_0_ram_miso : IN t_mem_miso;
+
+ reg_diag_bg_eth_0_copi : OUT t_mem_copi;
+ reg_diag_bg_eth_0_cipo : IN t_mem_cipo;
+ reg_hdr_dat_eth_0_copi : OUT t_mem_copi;
+ reg_hdr_dat_eth_0_cipo : IN t_mem_cipo;
+ reg_bsn_monitor_v2_tx_eth_0_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_tx_eth_0_cipo : IN t_mem_cipo;
+ reg_strobe_total_count_tx_eth_0_copi : OUT t_mem_copi;
+ reg_strobe_total_count_tx_eth_0_cipo : IN t_mem_cipo;
+
+ reg_bsn_monitor_v2_rx_eth_0_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_rx_eth_0_cipo : IN t_mem_cipo;
+ reg_strobe_total_count_rx_eth_0_copi : OUT t_mem_copi;
+ reg_strobe_total_count_rx_eth_0_cipo : IN t_mem_cipo;
-- eth1g ch1
- eth1g_eth1_mm_rst : OUT STD_LOGIC;
- eth1g_eth1_tse_mosi : OUT t_mem_mosi;
- eth1g_eth1_tse_miso : IN t_mem_miso;
- eth1g_eth1_reg_mosi : OUT t_mem_mosi;
- eth1g_eth1_reg_miso : IN t_mem_miso;
- eth1g_eth1_reg_interrupt : IN STD_LOGIC;
- eth1g_eth1_ram_mosi : OUT t_mem_mosi;
- eth1g_eth1_ram_miso : IN t_mem_miso;
-
- reg_eth1g_II_bg_ctrl_copi : OUT t_mem_copi;
- reg_eth1g_II_bg_ctrl_cipo : IN t_mem_cipo;
- reg_eth1g_II_hdr_dat_copi : OUT t_mem_copi;
- reg_eth1g_II_hdr_dat_cipo : IN t_mem_cipo;
- reg_eth1g_II_bsn_monitor_v2_tx_copi : OUT t_mem_copi;
- reg_eth1g_II_bsn_monitor_v2_tx_cipo : IN t_mem_cipo;
- reg_eth1g_II_strobe_total_count_tx_copi : OUT t_mem_copi;
- reg_eth1g_II_strobe_total_count_tx_cipo : IN t_mem_cipo;
-
- reg_eth1g_II_bsn_monitor_v2_rx_copi : OUT t_mem_copi;
- reg_eth1g_II_bsn_monitor_v2_rx_cipo : IN t_mem_cipo;
- reg_eth1g_II_strobe_total_count_rx_copi : OUT t_mem_copi;
- reg_eth1g_II_strobe_total_count_rx_cipo : IN t_mem_cipo;
+ eth_1_mm_rst : OUT STD_LOGIC;
+ eth_1_tse_mosi : OUT t_mem_mosi;
+ eth_1_tse_miso : IN t_mem_miso;
+ eth_1_reg_mosi : OUT t_mem_mosi;
+ eth_1_reg_miso : IN t_mem_miso;
+ eth_1_reg_interrupt : IN STD_LOGIC;
+ eth_1_ram_mosi : OUT t_mem_mosi;
+ eth_1_ram_miso : IN t_mem_miso;
+
+ reg_diag_bg_eth_1_copi : OUT t_mem_copi;
+ reg_diag_bg_eth_1_cipo : IN t_mem_cipo;
+ reg_hdr_dat_eth_1_copi : OUT t_mem_copi;
+ reg_hdr_dat_eth_1_cipo : IN t_mem_cipo;
+ reg_bsn_monitor_v2_tx_eth_1_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_tx_eth_1_cipo : IN t_mem_cipo;
+ reg_strobe_total_count_tx_eth_1_copi : OUT t_mem_copi;
+ reg_strobe_total_count_tx_eth_1_cipo : IN t_mem_cipo;
+
+ reg_bsn_monitor_v2_rx_eth_1_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_rx_eth_1_cipo : IN t_mem_cipo;
+ reg_strobe_total_count_rx_eth_1_copi : OUT t_mem_copi;
+ reg_strobe_total_count_rx_eth_1_cipo : IN t_mem_cipo;
-- EPCS read
reg_dpmm_data_mosi : OUT t_mem_mosi;
@@ -267,13 +267,13 @@ ARCHITECTURE str OF mmm_unb2c_test IS
SIGNAL sim_eth_mm_bus_switch : STD_LOGIC;
SIGNAL sim_eth_psc_access : STD_LOGIC;
- SIGNAL i_eth1g_eth0_reg_mosi : t_mem_mosi;
- SIGNAL i_eth1g_eth0_reg_miso : t_mem_miso;
- SIGNAL i_eth1g_eth1_reg_mosi : t_mem_mosi;
- SIGNAL i_eth1g_eth1_reg_miso : t_mem_miso;
+ SIGNAL i_eth_0_reg_mosi : t_mem_mosi;
+ SIGNAL i_eth_0_reg_miso : t_mem_miso;
+ SIGNAL i_eth_1_reg_mosi : t_mem_mosi;
+ SIGNAL i_eth_1_reg_miso : t_mem_miso;
- SIGNAL sim_eth1g_eth0_reg_mosi : t_mem_mosi;
- SIGNAL sim_eth1g_eth1_reg_mosi : t_mem_mosi;
+ SIGNAL sim_eth_0_reg_mosi : t_mem_mosi;
+ SIGNAL sim_eth_1_reg_mosi : t_mem_mosi;
SIGNAL i_reset_n : STD_LOGIC;
BEGIN
@@ -283,8 +283,8 @@ BEGIN
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
- eth1g_eth0_mm_rst <= mm_rst;
- eth1g_eth1_mm_rst <= mm_rst;
+ eth_0_mm_rst <= mm_rst;
+ eth_1_mm_rst <= mm_rst;
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -344,11 +344,17 @@ BEGIN
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- PORT MAP(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
- u_mm_file_reg_eth1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
- PORT MAP(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
-
+ -- . 1GbE_I with TSE setup by NiosII
+ u_mm_file_reg_eth_0_tse : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_TSE")
+ PORT MAP(mm_rst, mm_clk, eth_0_tse_mosi, eth_0_tse_miso);
+ u_mm_file_reg_eth_0_reg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_REG")
+ PORT MAP(mm_rst, mm_clk, i_eth_0_reg_mosi, eth_0_reg_miso);
+ u_mm_file_reg_eth_0_ram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_RAM")
+ PORT MAP(mm_rst, mm_clk, eth_0_ram_mosi, eth_0_ram_miso);
+ -- . 1GbE_II with TSE setup in VHDL
+ u_mm_file_reg_eth_1_tse : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_TSE")
+ PORT MAP(mm_rst, mm_clk, eth_1_tse_mosi, eth_1_tse_miso);
+
u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
u_mm_file_reg_tr_10GbE_back0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
@@ -364,31 +370,31 @@ BEGIN
u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
PORT MAP(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
- u_mm_file_reg_eth1g_I_bg_ctrl : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_BG_CTRL")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_I_bg_ctrl_copi, reg_eth1g_I_bg_ctrl_cipo );
- u_mm_file_reg_eth1g_I_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_I_hdr_dat_copi, reg_eth1g_I_hdr_dat_cipo );
- u_mm_file_reg_eth1g_I_bsn_monitor_v2_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_BSN_MONITOR_V2_TX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_I_bsn_monitor_v2_tx_copi, reg_eth1g_I_bsn_monitor_v2_tx_cipo );
- u_mm_file_reg_eth1g_I_strobe_total_count_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_STROBE_TOTAL_COUNT_TX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_I_strobe_total_count_tx_copi, reg_eth1g_I_strobe_total_count_tx_cipo );
- u_mm_file_reg_eth1g_I_bsn_monitor_v2_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_BSN_MONITOR_V2_RX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_I_bsn_monitor_v2_rx_copi, reg_eth1g_I_bsn_monitor_v2_rx_cipo );
- u_mm_file_reg_eth1g_I_strobe_total_count_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_STROBE_TOTAL_COUNT_RX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_I_strobe_total_count_rx_copi, reg_eth1g_I_strobe_total_count_rx_cipo );
-
- u_mm_file_reg_eth1g_II_bg_ctrl : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_BG_CTRL")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_II_bg_ctrl_copi, reg_eth1g_II_bg_ctrl_cipo );
- u_mm_file_reg_eth1g_II_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_II_hdr_dat_copi, reg_eth1g_II_hdr_dat_cipo );
- u_mm_file_reg_eth1g_II_bsn_monitor_v2_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_BSN_MONITOR_V2_TX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_II_bsn_monitor_v2_tx_copi, reg_eth1g_II_bsn_monitor_v2_tx_cipo );
- u_mm_file_reg_eth1g_II_strobe_total_count_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_STROBE_TOTAL_COUNT_TX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_II_strobe_total_count_tx_copi, reg_eth1g_II_strobe_total_count_tx_cipo );
- u_mm_file_reg_eth1g_II_bsn_monitor_v2_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_BSN_MONITOR_V2_RX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_II_bsn_monitor_v2_rx_copi, reg_eth1g_II_bsn_monitor_v2_rx_cipo );
- u_mm_file_reg_eth1g_II_strobe_total_count_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_STROBE_TOTAL_COUNT_RX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_II_strobe_total_count_rx_copi, reg_eth1g_II_strobe_total_count_rx_cipo );
+ u_mm_file_reg_reg_diag_bg_eth_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_ETH_0")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_eth_0_copi, reg_diag_bg_eth_0_cipo );
+ u_mm_file_reg_hdr_dat_eth_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT_ETH_0")
+ PORT MAP(mm_rst, mm_clk, reg_hdr_dat_eth_0_copi, reg_hdr_dat_eth_0_cipo );
+ u_mm_file_reg_bsn_monitor_v2_tx_eth_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX_ETH_0")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_0_copi, reg_bsn_monitor_v2_tx_eth_0_cipo );
+ u_mm_file_reg_strobe_total_count_tx_eth_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_TX_ETH_0")
+ PORT MAP(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_0_copi, reg_strobe_total_count_tx_eth_0_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_eth_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ETH_0")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_0_copi, reg_bsn_monitor_v2_rx_eth_0_cipo );
+ u_mm_file_reg_strobe_total_count_rx_eth_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_RX_ETH_0")
+ PORT MAP(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_0_copi, reg_strobe_total_count_rx_eth_0_cipo );
+
+ u_mm_file_reg_reg_diag_bg_eth_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_ETH_1")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_eth_1_copi, reg_diag_bg_eth_1_cipo );
+ u_mm_file_reg_hdr_dat_eth_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT_ETH_1")
+ PORT MAP(mm_rst, mm_clk, reg_hdr_dat_eth_1_copi, reg_hdr_dat_eth_1_cipo );
+ u_mm_file_reg_bsn_monitor_v2_tx_eth_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX_ETH_1")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_1_copi, reg_bsn_monitor_v2_tx_eth_1_cipo );
+ u_mm_file_reg_strobe_total_count_tx_eth_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_TX_ETH_1")
+ PORT MAP(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_1_copi, reg_strobe_total_count_tx_eth_1_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_eth_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ETH_1")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_1_copi, reg_bsn_monitor_v2_rx_eth_1_cipo );
+ u_mm_file_reg_strobe_total_count_rx_eth_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_RX_ETH_1")
+ PORT MAP(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_1_copi, reg_strobe_total_count_rx_eth_1_cipo );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -397,25 +403,25 @@ BEGIN
BEGIN
sim_eth_mm_bus_switch <= '1';
- eth1g_eth0_tse_mosi.wr <= '0';
- eth1g_eth0_tse_mosi.rd <= '0';
+ eth_0_tse_mosi.wr <= '0';
+ eth_0_tse_mosi.rd <= '0';
WAIT FOR 400 ns;
WAIT UNTIL rising_edge(mm_clk);
- proc_tech_tse_setup(c_tech_arria10_e1sg, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth0_tse_miso, eth1g_eth0_tse_mosi);
+ proc_tech_tse_setup(c_tech_arria10_e1sg, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth_0_tse_miso, eth_0_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth0_reg_miso, sim_eth1g_eth0_reg_mosi); -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth_0_reg_miso, sim_eth_0_reg_mosi); -- control rx en
sim_eth_mm_bus_switch <= '0';
WAIT;
END PROCESS;
- p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_eth0_reg_mosi, i_eth1g_eth0_reg_mosi)
+ p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth_0_reg_mosi, i_eth_0_reg_mosi)
BEGIN
IF sim_eth_mm_bus_switch = '1' THEN
- eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
+ eth_0_reg_mosi <= sim_eth_0_reg_mosi;
ELSE
- eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
+ eth_0_reg_mosi <= i_eth_0_reg_mosi;
END IF;
END PROCESS;
@@ -443,45 +449,45 @@ BEGIN
-- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2c_board.
pio_wdi_external_connection_export => pout_wdi,
- avs_eth_0_reset_export => eth1g_eth0_mm_rst,
+ avs_eth_0_reset_export => eth_0_mm_rst,
avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_eth0_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
- avs_eth_0_tse_write_export => eth1g_eth0_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_eth0_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_eth0_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_tse_readdata_export => eth1g_eth0_tse_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_tse_waitrequest_export => eth1g_eth0_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_eth0_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
- avs_eth_0_reg_write_export => eth1g_eth0_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_eth0_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_eth0_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_reg_readdata_export => eth1g_eth0_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_address_export => eth1g_eth0_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
- avs_eth_0_ram_write_export => eth1g_eth0_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_eth0_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_eth0_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_readdata_export => eth1g_eth0_ram_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_irq_export => eth1g_eth0_reg_interrupt,
-
- avs2_eth_coe_1_reset_export => eth1g_eth1_mm_rst,
- avs2_eth_coe_1_clk_export => OPEN,
- avs2_eth_coe_1_tse_address_export => eth1g_eth1_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
- avs2_eth_coe_1_tse_write_export => eth1g_eth1_tse_mosi.wr,
- avs2_eth_coe_1_tse_read_export => eth1g_eth1_tse_mosi.rd,
- avs2_eth_coe_1_tse_writedata_export => eth1g_eth1_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs2_eth_coe_1_tse_readdata_export => eth1g_eth1_tse_miso.rddata(c_word_w-1 DOWNTO 0),
- avs2_eth_coe_1_tse_waitrequest_export => eth1g_eth1_tse_miso.waitrequest,
- avs2_eth_coe_1_reg_address_export => eth1g_eth1_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
- avs2_eth_coe_1_reg_write_export => eth1g_eth1_reg_mosi.wr,
- avs2_eth_coe_1_reg_read_export => eth1g_eth1_reg_mosi.rd,
- avs2_eth_coe_1_reg_writedata_export => eth1g_eth1_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs2_eth_coe_1_reg_readdata_export => eth1g_eth1_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs2_eth_coe_1_ram_address_export => eth1g_eth1_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
- avs2_eth_coe_1_ram_write_export => eth1g_eth1_ram_mosi.wr,
- avs2_eth_coe_1_ram_read_export => eth1g_eth1_ram_mosi.rd,
- avs2_eth_coe_1_ram_writedata_export => eth1g_eth1_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs2_eth_coe_1_ram_readdata_export => eth1g_eth1_ram_miso.rddata(c_word_w-1 DOWNTO 0),
- avs2_eth_coe_1_irq_export => eth1g_eth1_reg_interrupt,
+ avs_eth_0_tse_address_export => eth_0_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_0_tse_write_export => eth_0_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth_0_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth_0_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_readdata_export => eth_0_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_waitrequest_export => eth_0_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth_0_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_reg_write_export => eth_0_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth_0_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth_0_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_reg_readdata_export => eth_0_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_address_export => eth_0_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_ram_write_export => eth_0_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth_0_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth_0_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_readdata_export => eth_0_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_irq_export => eth_0_reg_interrupt,
+
+ avs_eth_1_reset_export => eth_1_mm_rst,
+ avs_eth_1_clk_export => OPEN,
+ avs_eth_1_tse_address_export => eth_1_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_1_tse_write_export => eth_1_tse_mosi.wr,
+ avs_eth_1_tse_read_export => eth_1_tse_mosi.rd,
+ avs_eth_1_tse_writedata_export => eth_1_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_tse_readdata_export => eth_1_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_tse_waitrequest_export => eth_1_tse_miso.waitrequest,
+ avs_eth_1_reg_address_export => eth_1_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_1_reg_write_export => eth_1_reg_mosi.wr,
+ avs_eth_1_reg_read_export => eth_1_reg_mosi.rd,
+ avs_eth_1_reg_writedata_export => eth_1_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_reg_readdata_export => eth_1_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_ram_address_export => eth_1_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_1_ram_write_export => eth_1_ram_mosi.wr,
+ avs_eth_1_ram_read_export => eth_1_ram_mosi.rd,
+ avs_eth_1_ram_writedata_export => eth_1_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_ram_readdata_export => eth_1_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_irq_export => eth_1_reg_interrupt,
reg_fpga_temp_sens_reset_export => OPEN,
reg_fpga_temp_sens_clk_export => OPEN,
@@ -733,101 +739,101 @@ BEGIN
ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_eth1g_I_bg_ctrl_reset_export => OPEN,
- reg_eth1g_I_bg_ctrl_clk_export => OPEN,
- reg_eth1g_I_bg_ctrl_address_export => reg_eth1g_I_bg_ctrl_copi.address(4 downto 0),
- reg_eth1g_I_bg_ctrl_write_export => reg_eth1g_I_bg_ctrl_copi.wr,
- reg_eth1g_I_bg_ctrl_writedata_export => reg_eth1g_I_bg_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_I_bg_ctrl_read_export => reg_eth1g_I_bg_ctrl_copi.rd,
- reg_eth1g_I_bg_ctrl_readdata_export => reg_eth1g_I_bg_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_I_hdr_dat_reset_export => OPEN,
- reg_eth1g_I_hdr_dat_clk_export => OPEN,
- reg_eth1g_I_hdr_dat_address_export => reg_eth1g_I_hdr_dat_copi.address(6 downto 0),
- reg_eth1g_I_hdr_dat_write_export => reg_eth1g_I_hdr_dat_copi.wr,
- reg_eth1g_I_hdr_dat_writedata_export => reg_eth1g_I_hdr_dat_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_I_hdr_dat_read_export => reg_eth1g_I_hdr_dat_copi.rd,
- reg_eth1g_I_hdr_dat_readdata_export => reg_eth1g_I_hdr_dat_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_I_bsn_monitor_v2_tx_reset_export => OPEN,
- reg_eth1g_I_bsn_monitor_v2_tx_clk_export => OPEN,
- reg_eth1g_I_bsn_monitor_v2_tx_address_export => reg_eth1g_I_bsn_monitor_v2_tx_copi.address(4 downto 0),
- reg_eth1g_I_bsn_monitor_v2_tx_write_export => reg_eth1g_I_bsn_monitor_v2_tx_copi.wr,
- reg_eth1g_I_bsn_monitor_v2_tx_writedata_export => reg_eth1g_I_bsn_monitor_v2_tx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_I_bsn_monitor_v2_tx_read_export => reg_eth1g_I_bsn_monitor_v2_tx_copi.rd,
- reg_eth1g_I_bsn_monitor_v2_tx_readdata_export => reg_eth1g_I_bsn_monitor_v2_tx_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_I_strobe_total_count_tx_reset_export => OPEN,
- reg_eth1g_I_strobe_total_count_tx_clk_export => OPEN,
- reg_eth1g_I_strobe_total_count_tx_address_export => reg_eth1g_I_strobe_total_count_tx_copi.address(6 downto 0),
- reg_eth1g_I_strobe_total_count_tx_write_export => reg_eth1g_I_strobe_total_count_tx_copi.wr,
- reg_eth1g_I_strobe_total_count_tx_writedata_export => reg_eth1g_I_strobe_total_count_tx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_I_strobe_total_count_tx_read_export => reg_eth1g_I_strobe_total_count_tx_copi.rd,
- reg_eth1g_I_strobe_total_count_tx_readdata_export => reg_eth1g_I_strobe_total_count_tx_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_I_bsn_monitor_v2_rx_reset_export => OPEN,
- reg_eth1g_I_bsn_monitor_v2_rx_clk_export => OPEN,
- reg_eth1g_I_bsn_monitor_v2_rx_address_export => reg_eth1g_I_bsn_monitor_v2_rx_copi.address(4 downto 0),
- reg_eth1g_I_bsn_monitor_v2_rx_write_export => reg_eth1g_I_bsn_monitor_v2_rx_copi.wr,
- reg_eth1g_I_bsn_monitor_v2_rx_writedata_export => reg_eth1g_I_bsn_monitor_v2_rx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_I_bsn_monitor_v2_rx_read_export => reg_eth1g_I_bsn_monitor_v2_rx_copi.rd,
- reg_eth1g_I_bsn_monitor_v2_rx_readdata_export => reg_eth1g_I_bsn_monitor_v2_rx_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_I_strobe_total_count_rx_reset_export => OPEN,
- reg_eth1g_I_strobe_total_count_rx_clk_export => OPEN,
- reg_eth1g_I_strobe_total_count_rx_address_export => reg_eth1g_I_strobe_total_count_rx_copi.address(6 downto 0),
- reg_eth1g_I_strobe_total_count_rx_write_export => reg_eth1g_I_strobe_total_count_rx_copi.wr,
- reg_eth1g_I_strobe_total_count_rx_writedata_export => reg_eth1g_I_strobe_total_count_rx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_I_strobe_total_count_rx_read_export => reg_eth1g_I_strobe_total_count_rx_copi.rd,
- reg_eth1g_I_strobe_total_count_rx_readdata_export => reg_eth1g_I_strobe_total_count_rx_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_II_bg_ctrl_reset_export => OPEN,
- reg_eth1g_II_bg_ctrl_clk_export => OPEN,
- reg_eth1g_II_bg_ctrl_address_export => reg_eth1g_II_bg_ctrl_copi.address(2 downto 0),
- reg_eth1g_II_bg_ctrl_write_export => reg_eth1g_II_bg_ctrl_copi.wr,
- reg_eth1g_II_bg_ctrl_writedata_export => reg_eth1g_II_bg_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_II_bg_ctrl_read_export => reg_eth1g_II_bg_ctrl_copi.rd,
- reg_eth1g_II_bg_ctrl_readdata_export => reg_eth1g_II_bg_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_II_hdr_dat_reset_export => OPEN,
- reg_eth1g_II_hdr_dat_clk_export => OPEN,
- reg_eth1g_II_hdr_dat_address_export => reg_eth1g_II_hdr_dat_copi.address(4 downto 0),
- reg_eth1g_II_hdr_dat_write_export => reg_eth1g_II_hdr_dat_copi.wr,
- reg_eth1g_II_hdr_dat_writedata_export => reg_eth1g_II_hdr_dat_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_II_hdr_dat_read_export => reg_eth1g_II_hdr_dat_copi.rd,
- reg_eth1g_II_hdr_dat_readdata_export => reg_eth1g_II_hdr_dat_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_II_bsn_monitor_v2_tx_reset_export => OPEN,
- reg_eth1g_II_bsn_monitor_v2_tx_clk_export => OPEN,
- reg_eth1g_II_bsn_monitor_v2_tx_address_export => reg_eth1g_II_bsn_monitor_v2_tx_copi.address(2 downto 0),
- reg_eth1g_II_bsn_monitor_v2_tx_write_export => reg_eth1g_II_bsn_monitor_v2_tx_copi.wr,
- reg_eth1g_II_bsn_monitor_v2_tx_writedata_export => reg_eth1g_II_bsn_monitor_v2_tx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_II_bsn_monitor_v2_tx_read_export => reg_eth1g_II_bsn_monitor_v2_tx_copi.rd,
- reg_eth1g_II_bsn_monitor_v2_tx_readdata_export => reg_eth1g_II_bsn_monitor_v2_tx_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_II_strobe_total_count_tx_reset_export => OPEN,
- reg_eth1g_II_strobe_total_count_tx_clk_export => OPEN,
- reg_eth1g_II_strobe_total_count_tx_address_export => reg_eth1g_II_strobe_total_count_tx_copi.address(4 downto 0),
- reg_eth1g_II_strobe_total_count_tx_write_export => reg_eth1g_II_strobe_total_count_tx_copi.wr,
- reg_eth1g_II_strobe_total_count_tx_writedata_export => reg_eth1g_II_strobe_total_count_tx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_II_strobe_total_count_tx_read_export => reg_eth1g_II_strobe_total_count_tx_copi.rd,
- reg_eth1g_II_strobe_total_count_tx_readdata_export => reg_eth1g_II_strobe_total_count_tx_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_II_bsn_monitor_v2_rx_reset_export => OPEN,
- reg_eth1g_II_bsn_monitor_v2_rx_clk_export => OPEN,
- reg_eth1g_II_bsn_monitor_v2_rx_address_export => reg_eth1g_II_bsn_monitor_v2_rx_copi.address(2 downto 0),
- reg_eth1g_II_bsn_monitor_v2_rx_write_export => reg_eth1g_II_bsn_monitor_v2_rx_copi.wr,
- reg_eth1g_II_bsn_monitor_v2_rx_writedata_export => reg_eth1g_II_bsn_monitor_v2_rx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_II_bsn_monitor_v2_rx_read_export => reg_eth1g_II_bsn_monitor_v2_rx_copi.rd,
- reg_eth1g_II_bsn_monitor_v2_rx_readdata_export => reg_eth1g_II_bsn_monitor_v2_rx_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_II_strobe_total_count_rx_reset_export => OPEN,
- reg_eth1g_II_strobe_total_count_rx_clk_export => OPEN,
- reg_eth1g_II_strobe_total_count_rx_address_export => reg_eth1g_II_strobe_total_count_rx_copi.address(4 downto 0),
- reg_eth1g_II_strobe_total_count_rx_write_export => reg_eth1g_II_strobe_total_count_rx_copi.wr,
- reg_eth1g_II_strobe_total_count_rx_writedata_export => reg_eth1g_II_strobe_total_count_rx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_II_strobe_total_count_rx_read_export => reg_eth1g_II_strobe_total_count_rx_copi.rd,
- reg_eth1g_II_strobe_total_count_rx_readdata_export => reg_eth1g_II_strobe_total_count_rx_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_eth_0_reset_export => OPEN,
+ reg_diag_bg_eth_0_clk_export => OPEN,
+ reg_diag_bg_eth_0_address_export => reg_diag_bg_eth_0_copi.address(4 downto 0),
+ reg_diag_bg_eth_0_write_export => reg_diag_bg_eth_0_copi.wr,
+ reg_diag_bg_eth_0_writedata_export => reg_diag_bg_eth_0_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_eth_0_read_export => reg_diag_bg_eth_0_copi.rd,
+ reg_diag_bg_eth_0_readdata_export => reg_diag_bg_eth_0_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_hdr_dat_eth_0_reset_export => OPEN,
+ reg_hdr_dat_eth_0_clk_export => OPEN,
+ reg_hdr_dat_eth_0_address_export => reg_hdr_dat_eth_0_copi.address(6 downto 0),
+ reg_hdr_dat_eth_0_write_export => reg_hdr_dat_eth_0_copi.wr,
+ reg_hdr_dat_eth_0_writedata_export => reg_hdr_dat_eth_0_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_hdr_dat_eth_0_read_export => reg_hdr_dat_eth_0_copi.rd,
+ reg_hdr_dat_eth_0_readdata_export => reg_hdr_dat_eth_0_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_tx_eth_0_reset_export => OPEN,
+ reg_bsn_monitor_v2_tx_eth_0_clk_export => OPEN,
+ reg_bsn_monitor_v2_tx_eth_0_address_export => reg_bsn_monitor_v2_tx_eth_0_copi.address(4 downto 0),
+ reg_bsn_monitor_v2_tx_eth_0_write_export => reg_bsn_monitor_v2_tx_eth_0_copi.wr,
+ reg_bsn_monitor_v2_tx_eth_0_writedata_export => reg_bsn_monitor_v2_tx_eth_0_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_tx_eth_0_read_export => reg_bsn_monitor_v2_tx_eth_0_copi.rd,
+ reg_bsn_monitor_v2_tx_eth_0_readdata_export => reg_bsn_monitor_v2_tx_eth_0_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_strobe_total_count_tx_eth_0_reset_export => OPEN,
+ reg_strobe_total_count_tx_eth_0_clk_export => OPEN,
+ reg_strobe_total_count_tx_eth_0_address_export => reg_strobe_total_count_tx_eth_0_copi.address(6 downto 0),
+ reg_strobe_total_count_tx_eth_0_write_export => reg_strobe_total_count_tx_eth_0_copi.wr,
+ reg_strobe_total_count_tx_eth_0_writedata_export => reg_strobe_total_count_tx_eth_0_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_strobe_total_count_tx_eth_0_read_export => reg_strobe_total_count_tx_eth_0_copi.rd,
+ reg_strobe_total_count_tx_eth_0_readdata_export => reg_strobe_total_count_tx_eth_0_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_rx_eth_0_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_eth_0_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_eth_0_address_export => reg_bsn_monitor_v2_rx_eth_0_copi.address(4 downto 0),
+ reg_bsn_monitor_v2_rx_eth_0_write_export => reg_bsn_monitor_v2_rx_eth_0_copi.wr,
+ reg_bsn_monitor_v2_rx_eth_0_writedata_export => reg_bsn_monitor_v2_rx_eth_0_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_eth_0_read_export => reg_bsn_monitor_v2_rx_eth_0_copi.rd,
+ reg_bsn_monitor_v2_rx_eth_0_readdata_export => reg_bsn_monitor_v2_rx_eth_0_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_strobe_total_count_rx_eth_0_reset_export => OPEN,
+ reg_strobe_total_count_rx_eth_0_clk_export => OPEN,
+ reg_strobe_total_count_rx_eth_0_address_export => reg_strobe_total_count_rx_eth_0_copi.address(6 downto 0),
+ reg_strobe_total_count_rx_eth_0_write_export => reg_strobe_total_count_rx_eth_0_copi.wr,
+ reg_strobe_total_count_rx_eth_0_writedata_export => reg_strobe_total_count_rx_eth_0_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_strobe_total_count_rx_eth_0_read_export => reg_strobe_total_count_rx_eth_0_copi.rd,
+ reg_strobe_total_count_rx_eth_0_readdata_export => reg_strobe_total_count_rx_eth_0_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_diag_bg_eth_1_reset_export => OPEN,
+ reg_diag_bg_eth_1_clk_export => OPEN,
+ reg_diag_bg_eth_1_address_export => reg_diag_bg_eth_1_copi.address(2 downto 0),
+ reg_diag_bg_eth_1_write_export => reg_diag_bg_eth_1_copi.wr,
+ reg_diag_bg_eth_1_writedata_export => reg_diag_bg_eth_1_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_eth_1_read_export => reg_diag_bg_eth_1_copi.rd,
+ reg_diag_bg_eth_1_readdata_export => reg_diag_bg_eth_1_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_hdr_dat_eth_1_reset_export => OPEN,
+ reg_hdr_dat_eth_1_clk_export => OPEN,
+ reg_hdr_dat_eth_1_address_export => reg_hdr_dat_eth_1_copi.address(4 downto 0),
+ reg_hdr_dat_eth_1_write_export => reg_hdr_dat_eth_1_copi.wr,
+ reg_hdr_dat_eth_1_writedata_export => reg_hdr_dat_eth_1_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_hdr_dat_eth_1_read_export => reg_hdr_dat_eth_1_copi.rd,
+ reg_hdr_dat_eth_1_readdata_export => reg_hdr_dat_eth_1_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_tx_eth_1_reset_export => OPEN,
+ reg_bsn_monitor_v2_tx_eth_1_clk_export => OPEN,
+ reg_bsn_monitor_v2_tx_eth_1_address_export => reg_bsn_monitor_v2_tx_eth_1_copi.address(2 downto 0),
+ reg_bsn_monitor_v2_tx_eth_1_write_export => reg_bsn_monitor_v2_tx_eth_1_copi.wr,
+ reg_bsn_monitor_v2_tx_eth_1_writedata_export => reg_bsn_monitor_v2_tx_eth_1_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_tx_eth_1_read_export => reg_bsn_monitor_v2_tx_eth_1_copi.rd,
+ reg_bsn_monitor_v2_tx_eth_1_readdata_export => reg_bsn_monitor_v2_tx_eth_1_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_strobe_total_count_tx_eth_1_reset_export => OPEN,
+ reg_strobe_total_count_tx_eth_1_clk_export => OPEN,
+ reg_strobe_total_count_tx_eth_1_address_export => reg_strobe_total_count_tx_eth_1_copi.address(4 downto 0),
+ reg_strobe_total_count_tx_eth_1_write_export => reg_strobe_total_count_tx_eth_1_copi.wr,
+ reg_strobe_total_count_tx_eth_1_writedata_export => reg_strobe_total_count_tx_eth_1_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_strobe_total_count_tx_eth_1_read_export => reg_strobe_total_count_tx_eth_1_copi.rd,
+ reg_strobe_total_count_tx_eth_1_readdata_export => reg_strobe_total_count_tx_eth_1_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_rx_eth_1_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_eth_1_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_eth_1_address_export => reg_bsn_monitor_v2_rx_eth_1_copi.address(2 downto 0),
+ reg_bsn_monitor_v2_rx_eth_1_write_export => reg_bsn_monitor_v2_rx_eth_1_copi.wr,
+ reg_bsn_monitor_v2_rx_eth_1_writedata_export => reg_bsn_monitor_v2_rx_eth_1_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_eth_1_read_export => reg_bsn_monitor_v2_rx_eth_1_copi.rd,
+ reg_bsn_monitor_v2_rx_eth_1_readdata_export => reg_bsn_monitor_v2_rx_eth_1_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_strobe_total_count_rx_eth_1_reset_export => OPEN,
+ reg_strobe_total_count_rx_eth_1_clk_export => OPEN,
+ reg_strobe_total_count_rx_eth_1_address_export => reg_strobe_total_count_rx_eth_1_copi.address(4 downto 0),
+ reg_strobe_total_count_rx_eth_1_write_export => reg_strobe_total_count_rx_eth_1_copi.wr,
+ reg_strobe_total_count_rx_eth_1_writedata_export => reg_strobe_total_count_rx_eth_1_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_strobe_total_count_rx_eth_1_read_export => reg_strobe_total_count_rx_eth_1_copi.rd,
+ reg_strobe_total_count_rx_eth_1_readdata_export => reg_strobe_total_count_rx_eth_1_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_heater_reset_export => OPEN,
reg_heater_clk_export => OPEN,
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
index 4751e53edb6523fd1646ef7622c75a18de9d4821..e61e1499a2288285f38f0d552a1d3fcc9915609b 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
@@ -26,442 +26,442 @@ PACKAGE qsys_unb2c_test_pkg IS
component qsys_unb2c_test is
port (
- avs2_eth_coe_1_reset_export : out std_logic; -- export
- avs2_eth_coe_1_clk_export : out std_logic; -- export
- avs2_eth_coe_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs2_eth_coe_1_tse_write_export : out std_logic; -- export
- avs2_eth_coe_1_tse_read_export : out std_logic; -- export
- avs2_eth_coe_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs2_eth_coe_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs2_eth_coe_1_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs2_eth_coe_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs2_eth_coe_1_reg_write_export : out std_logic; -- export
- avs2_eth_coe_1_reg_read_export : out std_logic; -- export
- avs2_eth_coe_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs2_eth_coe_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs2_eth_coe_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs2_eth_coe_1_ram_write_export : out std_logic; -- export
- avs2_eth_coe_1_ram_read_export : out std_logic; -- export
- avs2_eth_coe_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs2_eth_coe_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs2_eth_coe_1_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back0_reset_export : out std_logic; -- export
- reg_eth10g_back0_clk_export : out std_logic; -- export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back0_write_export : out std_logic; -- export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back0_read_export : out std_logic; -- export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back1_reset_export : out std_logic; -- export
- reg_eth10g_back1_clk_export : out std_logic; -- export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back1_write_export : out std_logic; -- export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back1_read_export : out std_logic; -- export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_ii_bg_ctrl_reset_export : out std_logic; -- export
- reg_eth1g_ii_bg_ctrl_clk_export : out std_logic; -- export
- reg_eth1g_ii_bg_ctrl_address_export : out std_logic_vector(2 downto 0); -- export
- reg_eth1g_ii_bg_ctrl_write_export : out std_logic; -- export
- reg_eth1g_ii_bg_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_ii_bg_ctrl_read_export : out std_logic; -- export
- reg_eth1g_ii_bg_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_ii_bsn_monitor_v2_rx_reset_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_rx_clk_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_rx_address_export : out std_logic_vector(2 downto 0); -- export
- reg_eth1g_ii_bsn_monitor_v2_rx_write_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_ii_bsn_monitor_v2_rx_read_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_ii_bsn_monitor_v2_tx_reset_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_tx_clk_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_tx_address_export : out std_logic_vector(2 downto 0); -- export
- reg_eth1g_ii_bsn_monitor_v2_tx_write_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_ii_bsn_monitor_v2_tx_read_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_ii_hdr_dat_reset_export : out std_logic; -- export
- reg_eth1g_ii_hdr_dat_clk_export : out std_logic; -- export
- reg_eth1g_ii_hdr_dat_address_export : out std_logic_vector(4 downto 0); -- export
- reg_eth1g_ii_hdr_dat_write_export : out std_logic; -- export
- reg_eth1g_ii_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_ii_hdr_dat_read_export : out std_logic; -- export
- reg_eth1g_ii_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_ii_strobe_total_count_rx_reset_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_rx_clk_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_rx_address_export : out std_logic_vector(4 downto 0); -- export
- reg_eth1g_ii_strobe_total_count_rx_write_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_ii_strobe_total_count_rx_read_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_ii_strobe_total_count_tx_reset_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_tx_clk_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_tx_address_export : out std_logic_vector(4 downto 0); -- export
- reg_eth1g_ii_strobe_total_count_tx_write_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_ii_strobe_total_count_tx_read_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_i_bg_ctrl_reset_export : out std_logic; -- export
- reg_eth1g_i_bg_ctrl_clk_export : out std_logic; -- export
- reg_eth1g_i_bg_ctrl_address_export : out std_logic_vector(4 downto 0); -- export
- reg_eth1g_i_bg_ctrl_write_export : out std_logic; -- export
- reg_eth1g_i_bg_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_i_bg_ctrl_read_export : out std_logic; -- export
- reg_eth1g_i_bg_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_i_bsn_monitor_v2_rx_reset_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_rx_clk_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_rx_address_export : out std_logic_vector(4 downto 0); -- export
- reg_eth1g_i_bsn_monitor_v2_rx_write_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_i_bsn_monitor_v2_rx_read_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_i_bsn_monitor_v2_tx_reset_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_tx_clk_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_tx_address_export : out std_logic_vector(4 downto 0); -- export
- reg_eth1g_i_bsn_monitor_v2_tx_write_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_i_bsn_monitor_v2_tx_read_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_i_hdr_dat_reset_export : out std_logic; -- export
- reg_eth1g_i_hdr_dat_clk_export : out std_logic; -- export
- reg_eth1g_i_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth1g_i_hdr_dat_write_export : out std_logic; -- export
- reg_eth1g_i_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_i_hdr_dat_read_export : out std_logic; -- export
- reg_eth1g_i_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_i_strobe_total_count_rx_reset_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_rx_clk_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_rx_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth1g_i_strobe_total_count_rx_write_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_i_strobe_total_count_rx_read_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_i_strobe_total_count_tx_reset_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_tx_clk_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_tx_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth1g_i_strobe_total_count_tx_write_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_i_strobe_total_count_tx_read_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_reset_export : out std_logic; -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back0_write_export : out std_logic; -- export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back0_read_export : out std_logic; -- export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back1_write_export : out std_logic; -- export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back1_read_export : out std_logic; -- export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_1_reset_export : out std_logic; -- export
+ avs_eth_1_clk_export : out std_logic; -- export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_tse_write_export : out std_logic; -- export
+ avs_eth_1_tse_read_export : out std_logic; -- export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_1_reg_write_export : out std_logic; -- export
+ avs_eth_1_reg_read_export : out std_logic; -- export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_ram_write_export : out std_logic; -- export
+ avs_eth_1_ram_read_export : out std_logic; -- export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_irq_export : in std_logic := 'X'; -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_eth_0_reset_export : out std_logic; -- export
+ reg_diag_bg_eth_0_clk_export : out std_logic; -- export
+ reg_diag_bg_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_bg_eth_0_write_export : out std_logic; -- export
+ reg_diag_bg_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_eth_0_read_export : out std_logic; -- export
+ reg_diag_bg_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_eth_1_reset_export : out std_logic; -- export
+ reg_diag_bg_eth_1_clk_export : out std_logic; -- export
+ reg_diag_bg_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_eth_1_write_export : out std_logic; -- export
+ reg_diag_bg_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_eth_1_read_export : out std_logic; -- export
+ reg_diag_bg_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back0_reset_export : out std_logic; -- export
+ reg_eth10g_back0_clk_export : out std_logic; -- export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back0_write_export : out std_logic; -- export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back0_read_export : out std_logic; -- export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back1_reset_export : out std_logic; -- export
+ reg_eth10g_back1_clk_export : out std_logic; -- export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back1_write_export : out std_logic; -- export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back1_read_export : out std_logic; -- export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_eth_1_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_1_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_1_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_tx_eth_1_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_1_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_1_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_eth_1_reset_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_clk_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_hdr_dat_eth_1_write_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_eth_1_read_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_rx_eth_1_reset_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_clk_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_strobe_total_count_rx_eth_1_write_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_rx_eth_1_read_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_tx_eth_1_reset_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_clk_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_strobe_total_count_tx_eth_1_write_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_tx_eth_1_read_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_eth_0_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_0_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_0_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_tx_eth_0_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_0_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_0_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_eth_0_reset_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_clk_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_eth_0_write_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_eth_0_read_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_rx_eth_0_reset_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_clk_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_strobe_total_count_rx_eth_0_write_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_rx_eth_0_read_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_tx_eth_0_reset_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_clk_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_strobe_total_count_tx_eth_0_write_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_tx_eth_0_read_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_reset_export : out std_logic; -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
);
end component qsys_unb2c_test;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index 82df8854f7404d26fe25ce577a2eb6be4ce7a9a3..f584a6c375feb7ab4694d7e6fb1af511a3083148 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -135,8 +135,8 @@ ARCHITECTURE str OF unb2c_test IS
-- Revision controlled constants
CONSTANT c_revision_select : t_unb2c_test_config := func_sel_revision_rec(g_design_name);
CONSTANT c_use_loopback : BOOLEAN := c_revision_select.use_loopback;
- CONSTANT c_use_1GbE_I_UDP : BOOLEAN := c_revision_select.use_1GbE_I_UDP; -- Enable the UDP offload ports on eth0, eth0 is always enabled for control
- CONSTANT c_use_1GbE_II : BOOLEAN := c_revision_select.use_1GbE_II; -- Enable the second 1GbE eth1
+ CONSTANT c_use_eth_0_UDP : BOOLEAN := c_revision_select.use_1GbE_I_UDP; -- Enable the UDP offload ports on 1GbE-I = eth_0, eth_0 is always enabled for control
+ CONSTANT c_use_eth_1 : BOOLEAN := c_revision_select.use_1GbE_II; -- Enable the second 1GbE-II = eth_1
CONSTANT c_use_10GbE_qsfp : BOOLEAN := c_revision_select.use_10GbE_qsfp;
CONSTANT c_use_10GbE_ring : BOOLEAN := c_revision_select.use_10GbE_ring;
CONSTANT c_use_10GbE_back0 : BOOLEAN := c_revision_select.use_10GbE_back0;
@@ -155,10 +155,10 @@ ARCHITECTURE str OF unb2c_test IS
CONSTANT c_nof_jesd204b : NATURAL := c_unb2c_board_tr_jesd204b.nof_bus * c_unb2c_board_tr_jesd204b.bus_w;
-- 1GbE
- CONSTANT c_nof_udp_streams_1GbE_I : NATURAL := 4; -- <= c_eth_nof_udp_ports = 4, shared with M&C stream
- CONSTANT c_nof_udp_streams_1GbE_I_w : NATURAL := 2; -- = true_log2(c_nof_udp_streams_1GbE_I), fixed reserve 2 bit extra MM address space
- CONSTANT c_nof_udp_streams_1GbE_II : NATURAL := 1; -- fixed 1 UDP stream, so no need for dp_mux
- CONSTANT c_nof_udp_streams_1GbE_II_w : NATURAL := 0; -- = true_log2(c_nof_udp_streams_1GbE_II), fixed reserve no extra MM address space
+ CONSTANT c_nof_udp_streams_eth_0 : NATURAL := 4; -- <= c_eth_nof_udp_ports = 4, shared with M&C stream
+ CONSTANT c_nof_udp_streams_eth_0_w : NATURAL := 2; -- = true_log2(c_nof_udp_streams_eth_0), fixed reserve 2 bit extra MM address space
+ CONSTANT c_nof_udp_streams_eth_1 : NATURAL := 1; -- fixed 1 UDP stream, so no need for dp_mux
+ CONSTANT c_nof_udp_streams_eth_1_w : NATURAL := 0; -- = true_log2(c_nof_udp_streams_eth_1), fixed reserve no extra MM address space
CONSTANT c_base_mac : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := c_eth_tester_eth_src_mac_47_16; -- = X"00228608"
CONSTANT c_base_ip : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := c_eth_tester_ip_src_addr_31_16; -- = X"0A63"
CONSTANT c_base_udp : STD_LOGIC_VECTOR(8-1 DOWNTO 0) := c_eth_tester_udp_src_port_15_8; -- = X"E0"
@@ -259,24 +259,19 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso;
-- eth1g ch0
- SIGNAL eth1g_eth0_mm_rst : STD_LOGIC;
- SIGNAL eth1g_eth0_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
- SIGNAL eth1g_eth0_tse_miso : t_mem_miso;
- SIGNAL eth1g_eth0_reg_mosi : t_mem_mosi; -- ETH control and status registers
- SIGNAL eth1g_eth0_reg_miso : t_mem_miso;
- SIGNAL eth1g_eth0_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_eth0_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_eth0_ram_miso : t_mem_miso;
-
- -- eth1g ch1
- SIGNAL eth1g_eth1_mm_rst : STD_LOGIC;
- SIGNAL eth1g_eth1_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
- SIGNAL eth1g_eth1_tse_miso : t_mem_miso;
- SIGNAL eth1g_eth1_reg_mosi : t_mem_mosi; -- ETH control and status registers
- SIGNAL eth1g_eth1_reg_miso : t_mem_miso;
- SIGNAL eth1g_eth1_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_eth1_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_eth1_ram_miso : t_mem_miso;
+ SIGNAL eth_0_mm_rst : STD_LOGIC;
+ SIGNAL eth_0_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth_0_tse_miso : t_mem_miso;
+ SIGNAL eth_0_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ SIGNAL eth_0_reg_miso : t_mem_miso;
+ SIGNAL eth_0_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth_0_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ SIGNAL eth_0_ram_miso : t_mem_miso;
+
+ -- eth1g ch1 (eth_stream only has MM for TSE MAC)
+ SIGNAL eth_1_mm_rst : STD_LOGIC;
+ SIGNAL eth_1_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth_1_tse_miso : t_mem_miso;
-- EPCS read
SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
@@ -360,37 +355,37 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL reg_eth10g_back0_mosi : t_mem_mosi;
SIGNAL reg_eth10g_back0_miso : t_mem_miso;
- -- 1GbE I eth_tester (c_nof_udp_streams_1GbE_I_w = 2 bit)
+ -- 1GbE I eth_tester (c_nof_udp_streams_eth_0_w = 2 bit)
-- . Tx
- SIGNAL reg_eth1g_I_bg_ctrl_copi : t_mem_copi := c_mem_copi_rst; -- c_diag_bg_reg_adr_w = 3 --> w = 5
- SIGNAL reg_eth1g_I_bg_ctrl_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_I_hdr_dat_copi : t_mem_copi := c_mem_copi_rst; -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 7
- SIGNAL reg_eth1g_I_hdr_dat_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_I_bsn_monitor_v2_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
- SIGNAL reg_eth1g_I_bsn_monitor_v2_tx_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_I_strobe_total_count_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
- SIGNAL reg_eth1g_I_strobe_total_count_tx_cipo : t_mem_cipo;
+ SIGNAL reg_diag_bg_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_diag_bg_reg_adr_w = 3 --> w = 5
+ SIGNAL reg_diag_bg_eth_0_cipo : t_mem_cipo;
+ SIGNAL reg_hdr_dat_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 7
+ SIGNAL reg_hdr_dat_eth_0_cipo : t_mem_cipo;
+ SIGNAL reg_bsn_monitor_v2_tx_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
+ SIGNAL reg_bsn_monitor_v2_tx_eth_0_cipo : t_mem_cipo;
+ SIGNAL reg_strobe_total_count_tx_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
+ SIGNAL reg_strobe_total_count_tx_eth_0_cipo : t_mem_cipo;
-- . Rx
- SIGNAL reg_eth1g_I_bsn_monitor_v2_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
- SIGNAL reg_eth1g_I_bsn_monitor_v2_rx_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_I_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
- SIGNAL reg_eth1g_I_strobe_total_count_rx_cipo : t_mem_cipo;
+ SIGNAL reg_bsn_monitor_v2_rx_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
+ SIGNAL reg_bsn_monitor_v2_rx_eth_0_cipo : t_mem_cipo;
+ SIGNAL reg_strobe_total_count_rx_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
+ SIGNAL reg_strobe_total_count_rx_eth_0_cipo : t_mem_cipo;
- -- 1GbE II eth_tester (c_nof_udp_streams_1GbE_I_w = 0 bit)
+ -- 1GbE II eth_tester (c_nof_udp_streams_eth_1_w = 0 bit)
-- . Tx
- SIGNAL reg_eth1g_II_bg_ctrl_copi : t_mem_copi := c_mem_copi_rst; -- c_diag_bg_reg_adr_w = 3 --> w = 3
- SIGNAL reg_eth1g_II_bg_ctrl_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_II_hdr_dat_copi : t_mem_copi := c_mem_copi_rst; -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 5
- SIGNAL reg_eth1g_II_hdr_dat_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_II_bsn_monitor_v2_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
- SIGNAL reg_eth1g_II_bsn_monitor_v2_tx_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_II_strobe_total_count_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
- SIGNAL reg_eth1g_II_strobe_total_count_tx_cipo : t_mem_cipo;
+ SIGNAL reg_diag_bg_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_diag_bg_reg_adr_w = 3 --> w = 3
+ SIGNAL reg_diag_bg_eth_1_cipo : t_mem_cipo;
+ SIGNAL reg_hdr_dat_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 5
+ SIGNAL reg_hdr_dat_eth_1_cipo : t_mem_cipo;
+ SIGNAL reg_bsn_monitor_v2_tx_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
+ SIGNAL reg_bsn_monitor_v2_tx_eth_1_cipo : t_mem_cipo;
+ SIGNAL reg_strobe_total_count_tx_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
+ SIGNAL reg_strobe_total_count_tx_eth_1_cipo : t_mem_cipo;
-- . Rx
- SIGNAL reg_eth1g_II_bsn_monitor_v2_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
- SIGNAL reg_eth1g_II_bsn_monitor_v2_rx_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_II_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
- SIGNAL reg_eth1g_II_strobe_total_count_rx_cipo : t_mem_cipo;
+ SIGNAL reg_bsn_monitor_v2_rx_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
+ SIGNAL reg_bsn_monitor_v2_rx_eth_1_cipo : t_mem_cipo;
+ SIGNAL reg_strobe_total_count_rx_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
+ SIGNAL reg_strobe_total_count_rx_eth_1_cipo : t_mem_cipo;
-- 10GbE
SIGNAL reg_diag_bg_10GbE_mosi : t_mem_mosi;
@@ -447,25 +442,25 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL ram_diag_data_buf_ddr_MB_II_miso : t_mem_miso;
-- UDP streaming ports for 1GbE I and 1GbE II
- -- . 1GbE I
+ -- . eth_0 = 1GbE I
SIGNAL gn_eth_src_mac_I : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
SIGNAL gn_ip_src_addr_I : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
SIGNAL gn_udp_src_port_I : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
- SIGNAL eth1g_I_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0);
- SIGNAL eth1g_I_udp_tx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0);
- SIGNAL eth1g_I_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0);
- SIGNAL eth1g_I_udp_rx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL eth_0_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_eth_0-1 DOWNTO 0);
+ SIGNAL eth_0_udp_tx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_eth_0-1 DOWNTO 0);
+ SIGNAL eth_0_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_eth_0-1 DOWNTO 0);
+ SIGNAL eth_0_udp_rx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_eth_0-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
- -- . 1GbE II
+ -- . eth_1 = 1GbE II
SIGNAL gn_eth_src_mac_II : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
SIGNAL gn_ip_src_addr_II : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
SIGNAL gn_udp_src_port_II : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
- SIGNAL eth1g_II_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0);
- SIGNAL eth1g_II_udp_tx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0);
- SIGNAL eth1g_II_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0);
- SIGNAL eth1g_II_udp_rx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL eth_1_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_eth_1-1 DOWNTO 0);
+ SIGNAL eth_1_udp_tx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_eth_1-1 DOWNTO 0);
+ SIGNAL eth_1_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_eth_1-1 DOWNTO 0);
+ SIGNAL eth_1_udp_rx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_eth_1-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-- QSFP leds
SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.nof_bus-1 DOWNTO 0);
@@ -494,8 +489,8 @@ BEGIN
g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
g_aux => c_unb2c_board_aux,
g_base_ip => c_base_ip, -- = X"0A63" is base IP address used by unb_osy: 10.99.xx.yy
- g_udp_offload => c_use_1GbE_I_UDP,
- g_udp_offload_nof_streams => c_nof_udp_streams_1GbE_I,
+ g_udp_offload => c_use_eth_0_UDP,
+ g_udp_offload_nof_streams => c_nof_udp_streams_eth_0,
g_factory_image => g_factory_image,
g_protect_addr_range => g_protect_addr_range
)
@@ -566,20 +561,20 @@ BEGIN
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g ch0
- eth1g_mm_rst => eth1g_eth0_mm_rst,
- eth1g_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_tse_miso => eth1g_eth0_tse_miso,
- eth1g_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_reg_miso => eth1g_eth0_reg_miso,
- eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_ram_miso => eth1g_eth0_ram_miso,
+ eth1g_mm_rst => eth_0_mm_rst,
+ eth1g_tse_mosi => eth_0_tse_mosi,
+ eth1g_tse_miso => eth_0_tse_miso,
+ eth1g_reg_mosi => eth_0_reg_mosi,
+ eth1g_reg_miso => eth_0_reg_miso,
+ eth1g_reg_interrupt => eth_0_reg_interrupt,
+ eth1g_ram_mosi => eth_0_ram_mosi,
+ eth1g_ram_miso => eth_0_ram_miso,
-- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_I_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_I_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_I_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_I_udp_rx_siso_arr,
+ udp_tx_sosi_arr => eth_0_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth_0_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth_0_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth_0_udp_rx_siso_arr,
-- scrap ram
ram_scrap_mosi => ram_scrap_mosi,
@@ -649,52 +644,52 @@ BEGIN
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g ch0
- eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
- eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
- eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
- eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
-
- reg_eth1g_I_bg_ctrl_copi => reg_eth1g_I_bg_ctrl_copi,
- reg_eth1g_I_bg_ctrl_cipo => reg_eth1g_I_bg_ctrl_cipo,
- reg_eth1g_I_hdr_dat_copi => reg_eth1g_I_hdr_dat_copi,
- reg_eth1g_I_hdr_dat_cipo => reg_eth1g_I_hdr_dat_cipo,
- reg_eth1g_I_bsn_monitor_v2_tx_copi => reg_eth1g_I_bsn_monitor_v2_tx_copi,
- reg_eth1g_I_bsn_monitor_v2_tx_cipo => reg_eth1g_I_bsn_monitor_v2_tx_cipo,
- reg_eth1g_I_strobe_total_count_tx_copi => reg_eth1g_I_strobe_total_count_tx_copi,
- reg_eth1g_I_strobe_total_count_tx_cipo => reg_eth1g_I_strobe_total_count_tx_cipo,
-
- reg_eth1g_I_bsn_monitor_v2_rx_copi => reg_eth1g_I_bsn_monitor_v2_rx_copi,
- reg_eth1g_I_bsn_monitor_v2_rx_cipo => reg_eth1g_I_bsn_monitor_v2_rx_cipo,
- reg_eth1g_I_strobe_total_count_rx_copi => reg_eth1g_I_strobe_total_count_rx_copi,
- reg_eth1g_I_strobe_total_count_rx_cipo => reg_eth1g_I_strobe_total_count_rx_cipo,
+ eth_0_mm_rst => eth_0_mm_rst,
+ eth_0_tse_mosi => eth_0_tse_mosi,
+ eth_0_tse_miso => eth_0_tse_miso,
+ eth_0_reg_mosi => eth_0_reg_mosi,
+ eth_0_reg_miso => eth_0_reg_miso,
+ eth_0_reg_interrupt => eth_0_reg_interrupt,
+ eth_0_ram_mosi => eth_0_ram_mosi,
+ eth_0_ram_miso => eth_0_ram_miso,
+
+ reg_diag_bg_eth_0_copi => reg_diag_bg_eth_0_copi,
+ reg_diag_bg_eth_0_cipo => reg_diag_bg_eth_0_cipo,
+ reg_hdr_dat_eth_0_copi => reg_hdr_dat_eth_0_copi,
+ reg_hdr_dat_eth_0_cipo => reg_hdr_dat_eth_0_cipo,
+ reg_bsn_monitor_v2_tx_eth_0_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
+ reg_bsn_monitor_v2_tx_eth_0_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
+ reg_strobe_total_count_tx_eth_0_copi => reg_strobe_total_count_tx_eth_0_copi,
+ reg_strobe_total_count_tx_eth_0_cipo => reg_strobe_total_count_tx_eth_0_cipo,
+
+ reg_bsn_monitor_v2_rx_eth_0_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
+ reg_bsn_monitor_v2_rx_eth_0_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
+ reg_strobe_total_count_rx_eth_0_copi => reg_strobe_total_count_rx_eth_0_copi,
+ reg_strobe_total_count_rx_eth_0_cipo => reg_strobe_total_count_rx_eth_0_cipo,
-- eth1g ch1
- eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
- eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
- eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
- eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
- eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
- eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
- eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
- eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
-
- reg_eth1g_II_bg_ctrl_copi => reg_eth1g_II_bg_ctrl_copi,
- reg_eth1g_II_bg_ctrl_cipo => reg_eth1g_II_bg_ctrl_cipo,
- reg_eth1g_II_hdr_dat_copi => reg_eth1g_II_hdr_dat_copi,
- reg_eth1g_II_hdr_dat_cipo => reg_eth1g_II_hdr_dat_cipo,
- reg_eth1g_II_bsn_monitor_v2_tx_copi => reg_eth1g_II_bsn_monitor_v2_tx_copi,
- reg_eth1g_II_bsn_monitor_v2_tx_cipo => reg_eth1g_II_bsn_monitor_v2_tx_cipo,
- reg_eth1g_II_strobe_total_count_tx_copi => reg_eth1g_II_strobe_total_count_tx_copi,
- reg_eth1g_II_strobe_total_count_tx_cipo => reg_eth1g_II_strobe_total_count_tx_cipo,
-
- reg_eth1g_II_bsn_monitor_v2_rx_copi => reg_eth1g_II_bsn_monitor_v2_rx_copi,
- reg_eth1g_II_bsn_monitor_v2_rx_cipo => reg_eth1g_II_bsn_monitor_v2_rx_cipo,
- reg_eth1g_II_strobe_total_count_rx_copi => reg_eth1g_II_strobe_total_count_rx_copi,
- reg_eth1g_II_strobe_total_count_rx_cipo => reg_eth1g_II_strobe_total_count_rx_cipo,
+ eth_1_mm_rst => eth_1_mm_rst,
+ eth_1_tse_mosi => eth_1_tse_mosi,
+ eth_1_tse_miso => eth_1_tse_miso,
+ eth_1_reg_mosi => OPEN,
+ eth_1_reg_miso => c_mem_cipo_rst,
+ eth_1_reg_interrupt => '0',
+ eth_1_ram_mosi => OPEN,
+ eth_1_ram_miso => c_mem_cipo_rst,
+
+ reg_diag_bg_eth_1_copi => reg_diag_bg_eth_1_copi,
+ reg_diag_bg_eth_1_cipo => reg_diag_bg_eth_1_cipo,
+ reg_hdr_dat_eth_1_copi => reg_hdr_dat_eth_1_copi,
+ reg_hdr_dat_eth_1_cipo => reg_hdr_dat_eth_1_cipo,
+ reg_bsn_monitor_v2_tx_eth_1_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
+ reg_bsn_monitor_v2_tx_eth_1_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
+ reg_strobe_total_count_tx_eth_1_copi => reg_strobe_total_count_tx_eth_1_copi,
+ reg_strobe_total_count_tx_eth_1_cipo => reg_strobe_total_count_tx_eth_1_cipo,
+
+ reg_bsn_monitor_v2_rx_eth_1_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
+ reg_bsn_monitor_v2_rx_eth_1_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
+ reg_strobe_total_count_rx_eth_1_copi => reg_strobe_total_count_rx_eth_1_copi,
+ reg_strobe_total_count_rx_eth_1_cipo => reg_strobe_total_count_rx_eth_1_cipo,
-- EPCS read
reg_dpmm_data_mosi => reg_dpmm_data_mosi,
@@ -804,14 +799,16 @@ BEGIN
);
- gen_udp_stream_1GbE : IF c_use_1GbE_I_UDP = TRUE GENERATE
+ gen_eth_0_udp : IF c_use_eth_0_UDP = TRUE GENERATE
+ -- Derive MAC/IP/UDP from gn_index
gn_eth_src_mac_I <= c_base_mac & func_eth_tester_gn_index_to_mac_15_0(gn_index, 0);
gn_ip_src_addr_I <= c_base_ip & func_eth_tester_gn_index_to_ip_15_0(gn_index, 0);
gn_udp_src_port_I <= c_base_udp & func_eth_tester_gn_index_to_udp_7_0(gn_index, 0);
+ -- Generate UDP Tx and monitor UDP Rx
u_eth_tester_I : ENTITY eth_lib.eth_tester
GENERIC MAP (
- g_nof_streams => c_nof_udp_streams_1GbE_I,
+ g_nof_streams => c_nof_udp_streams_eth_0,
g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
g_remove_crc => TRUE -- use TRUE when using TSE link interface
)
@@ -830,83 +827,46 @@ BEGIN
tx_fifo_rd_emp_arr => OPEN,
- tx_udp_sosi_arr => eth1g_I_udp_tx_sosi_arr,
- tx_udp_siso_arr => eth1g_I_udp_tx_siso_arr,
+ tx_udp_sosi_arr => eth_0_udp_tx_sosi_arr,
+ tx_udp_siso_arr => eth_0_udp_tx_siso_arr,
-- UDP receive interface
- rx_udp_sosi_arr => eth1g_I_udp_rx_sosi_arr,
+ rx_udp_sosi_arr => eth_0_udp_rx_sosi_arr,
-- Memory Mapped Slaves (one per stream)
-- . Tx
- reg_bg_ctrl_copi => reg_eth1g_I_bg_ctrl_copi,
- reg_bg_ctrl_cipo => reg_eth1g_I_bg_ctrl_cipo,
- reg_hdr_dat_copi => reg_eth1g_I_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_eth1g_I_hdr_dat_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_eth1g_I_bsn_monitor_v2_tx_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_eth1g_I_bsn_monitor_v2_tx_cipo,
- reg_strobe_total_count_tx_copi => reg_eth1g_I_strobe_total_count_tx_copi,
- reg_strobe_total_count_tx_cipo => reg_eth1g_I_strobe_total_count_tx_cipo,
+ reg_bg_ctrl_copi => reg_diag_bg_eth_0_copi,
+ reg_bg_ctrl_cipo => reg_diag_bg_eth_0_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_eth_0_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_eth_0_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_0_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_0_cipo,
-- . Rx
- reg_bsn_monitor_v2_rx_copi => reg_eth1g_I_bsn_monitor_v2_rx_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_eth1g_I_bsn_monitor_v2_rx_cipo,
- reg_strobe_total_count_rx_copi => reg_eth1g_I_strobe_total_count_rx_copi,
- reg_strobe_total_count_rx_cipo => reg_eth1g_I_strobe_total_count_rx_cipo
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_0_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_0_cipo
);
- END GENERATE;
-
-
- -- Instantiate a second 1GbE to check pinning
- gen_eth_II: IF c_use_1GbE_II = TRUE GENERATE
- u_eth : ENTITY eth_lib.eth
- GENERIC MAP (
- g_technology => g_technology,
- g_init_ip_address => c_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => TRUE,
- g_frm_discard_en => TRUE
- )
- PORT MAP (
- -- Clocks and reset
- mm_rst => mm_rst, -- use reset from QSYS
- mm_clk => mm_clk, -- use mm_clk direct
- --eth_clk => xo_ethclk, -- 125 MHz clock
- eth_clk => ETH_CLK(1),
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => (others => c_dp_sosi_rst),
- udp_tx_snk_out_arr => open,
- -- UDP receive interface
- udp_rx_src_in_arr => (others => c_dp_siso_rdy),
- udp_rx_src_out_arr => open,
-
- -- Memory Mapped Slaves
- tse_sla_in => c_mem_mosi_rst,
- tse_sla_out => open,
- reg_sla_in => c_mem_mosi_rst,
- reg_sla_out => open,
- reg_sla_interrupt => open,
- ram_sla_in => c_mem_mosi_rst,
- ram_sla_out => open,
-
- -- PHY interface
- eth_txp => ETH_SGOUT(1),
- eth_rxp => ETH_SGIN(1),
-
- -- LED interface
- tse_led => open
- );
+ -- Uses eth.vhd with ETH/TSE interface with UDP streams in ctrl_unb2c_board
+ -- to stream UDP data via eth_0 = 1GbE-I.
+ END GENERATE;
- -- TODO: Add control and connect for second 1GbE
+ -- Instantiate a second 1GbE-II to check pinning and to test UDP data via a
+ -- dedicated 1GbE port, instead of multiplexed with M&C
+ gen_eth_1: IF c_use_eth_1 = TRUE GENERATE
+ -- Derive eth_1 MAC/IP/UDP from eth_0
gn_eth_src_mac_II <= c_base_mac & func_eth_tester_gn_index_to_mac_15_0(gn_index, 1);
gn_ip_src_addr_II <= c_base_ip & func_eth_tester_gn_index_to_ip_15_0(gn_index, 1);
gn_udp_src_port_II <= c_base_udp & func_eth_tester_gn_index_to_udp_7_0(gn_index, 1);
+ -- Generate UDP Tx and monitor UDP Rx
u_eth_tester_II : ENTITY eth_lib.eth_tester
GENERIC MAP (
- g_nof_streams => c_nof_udp_streams_1GbE_II,
+ g_nof_streams => c_nof_udp_streams_eth_1,
g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
g_remove_crc => TRUE -- use TRUE when using TSE link interface
)
@@ -925,27 +885,69 @@ BEGIN
tx_fifo_rd_emp_arr => OPEN,
- tx_udp_sosi_arr => eth1g_II_udp_tx_sosi_arr,
- tx_udp_siso_arr => eth1g_II_udp_tx_siso_arr,
+ tx_udp_sosi_arr => eth_1_udp_tx_sosi_arr,
+ tx_udp_siso_arr => eth_1_udp_tx_siso_arr,
-- UDP receive interface
- rx_udp_sosi_arr => eth1g_II_udp_rx_sosi_arr,
+ rx_udp_sosi_arr => eth_1_udp_rx_sosi_arr,
-- Memory Mapped Slaves (one per stream)
-- . Tx
- reg_bg_ctrl_copi => reg_eth1g_II_bg_ctrl_copi,
- reg_bg_ctrl_cipo => reg_eth1g_II_bg_ctrl_cipo,
- reg_hdr_dat_copi => reg_eth1g_II_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_eth1g_II_hdr_dat_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_eth1g_II_bsn_monitor_v2_tx_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_eth1g_II_bsn_monitor_v2_tx_cipo,
- reg_strobe_total_count_tx_copi => reg_eth1g_II_strobe_total_count_tx_copi,
- reg_strobe_total_count_tx_cipo => reg_eth1g_II_strobe_total_count_tx_cipo,
+ reg_bg_ctrl_copi => reg_diag_bg_eth_1_copi,
+ reg_bg_ctrl_cipo => reg_diag_bg_eth_1_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_eth_1_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_eth_1_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_1_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_1_cipo,
-- . Rx
- reg_bsn_monitor_v2_rx_copi => reg_eth1g_II_bsn_monitor_v2_rx_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_eth1g_II_bsn_monitor_v2_rx_cipo,
- reg_strobe_total_count_rx_copi => reg_eth1g_II_strobe_total_count_rx_copi,
- reg_strobe_total_count_rx_cipo => reg_eth1g_II_strobe_total_count_rx_cipo
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_1_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_1_cipo
+ );
+
+ -- Use eth_stream with ETH/TSE interface for UDP port g_rx_udp_port to
+ -- stream UDP data via eth_1 = 1GbE-II
+ u_eth_stream : ENTITY eth_lib.eth_stream
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_rx_udp_port => TO_UINT(c_eth_rx_udp_port), -- = 0x1771 = 6001
+ g_jumbo_en => FALSE,
+ g_sim => g_sim,
+ g_sim_level => 1 -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => mm_rst, -- eth_1_mm_rst
+ mm_clk => mm_clk,
+ eth_clk => ETH_CLK(1),
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- TSE setup
+ src_mac => gn_eth_src_mac_II,
+ setup_done => OPEN,
+
+ -- UDP transmit interface
+ udp_tx_snk_in => eth_1_udp_tx_sosi_arr(0),
+ udp_tx_snk_out => eth_1_udp_tx_siso_arr(0),
+
+ -- UDP receive interface
+ udp_rx_src_in => c_dp_siso_rdy,
+ udp_rx_src_out => eth_1_udp_rx_sosi_arr(0),
+
+ -- Memory Mapped Slaves
+ tse_ctlr_copi => eth_1_tse_mosi,
+ tse_ctlr_cipo => eth_1_tse_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT(1),
+ eth_rxp => ETH_SGIN(1),
+
+ -- LED interface
+ tse_led => OPEN
);
END GENERATE;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
index e4509f19e3093b66f624ad69474530678c26ddda..6ee8be5303c12650dbf08a19232fe2ce7f86b1c1 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
@@ -76,19 +76,21 @@ PACKAGE unb2c_test_pkg IS
type_MB_I : t_c_tech_ddr;
type_MB_II : t_c_tech_ddr;
END RECORD;
+
-- loop 1GbE 1GbE qsfp ring bk0 jesd DDR4 DDR4 heatr
- CONSTANT c_test_minimal : t_unb2c_test_config := (FALSE, TRUE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- CONSTANT c_test_10GbE : t_unb2c_test_config := (FALSE, TRUE, TRUE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- CONSTANT c_test_10GbE_qb : t_unb2c_test_config := (FALSE, TRUE, TRUE, TRUE,FALSE, TRUE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- CONSTANT c_test_ddr : t_unb2c_test_config := (FALSE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE, TRUE, TRUE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- CONSTANT c_test_ddr_16G : t_unb2c_test_config := (FALSE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE, TRUE, TRUE,FALSE,c_tech_ddr4_16g_1600m_72_64, c_tech_ddr4_16g_1600m_72_64);
- CONSTANT c_test_heater : t_unb2c_test_config := (FALSE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- CONSTANT c_test_jesd204b : t_unb2c_test_config := (FALSE, TRUE, TRUE,FALSE,FALSE,FALSE, TRUE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ CONSTANT c_test_minimal : t_unb2c_test_config := (FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ CONSTANT c_test_1GbE_I_UDP : t_unb2c_test_config := (FALSE, TRUE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ CONSTANT c_test_1GbE_II_UDP : t_unb2c_test_config := (FALSE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ CONSTANT c_test_10GbE : t_unb2c_test_config := (FALSE,FALSE,FALSE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ CONSTANT c_test_10GbE_qb : t_unb2c_test_config := (FALSE,FALSE,FALSE, TRUE,FALSE, TRUE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ CONSTANT c_test_ddr : t_unb2c_test_config := (FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE, TRUE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ CONSTANT c_test_ddr_16G : t_unb2c_test_config := (FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE, TRUE,FALSE,c_tech_ddr4_16g_1600m_72_64, c_tech_ddr4_16g_1600m_72_64);
+ CONSTANT c_test_heater : t_unb2c_test_config := (FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ CONSTANT c_test_jesd204b : t_unb2c_test_config := (FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
-- Function to select the revision configuration.
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_unb2c_test_config;
-
END unb2c_test_pkg;
@@ -96,11 +98,13 @@ PACKAGE BODY unb2c_test_pkg IS
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_unb2c_test_config IS
BEGIN
- IF g_design_name = "unb2c_test_10GbE" THEN RETURN c_test_10GbE;
- ELSIF g_design_name = "unb2c_test_ddr" THEN RETURN c_test_ddr;
+ IF g_design_name = "unb2c_test_10GbE" THEN RETURN c_test_10GbE;
+ ELSIF g_design_name = "unb2c_test_ddr" THEN RETURN c_test_ddr;
+ ELSIF g_design_name = "unb2c_test_heater" THEN RETURN c_test_heater;
+ ELSIF g_design_name = "unb2c_test_jesd204b" THEN RETURN c_test_jesd204b;
+ ELSIF g_design_name = "unb2c_test_1GbE_I" THEN RETURN c_test_1GbE_I_UDP;
+ ELSIF g_design_name = "unb2c_test_1GbE_II" THEN RETURN c_test_1GbE_II_UDP;
ELSIF g_design_name = "unb2c_test_ddr_16G" THEN RETURN c_test_ddr_16G;
- ELSIF g_design_name = "unb2c_test_heater" THEN RETURN c_test_heater;
- ELSIF g_design_name = "unb2c_test_jesd204b" THEN RETURN c_test_jesd204b;
ELSE RETURN c_test_minimal;
END IF;
END;
diff --git a/boards/uniboard2c/designs/unb2c_test/unb2c_test.fpga.yaml b/boards/uniboard2c/designs/unb2c_test/unb2c_test.fpga.yaml
index 0b33ed4c02331e284be62af8c60356aebc66870d..0c7f07d961f8ea77e4da22f3a53b55003d482881 100644
--- a/boards/uniboard2c/designs/unb2c_test/unb2c_test.fpga.yaml
+++ b/boards/uniboard2c/designs/unb2c_test/unb2c_test.fpga.yaml
@@ -6,9 +6,8 @@ hdl_library_name: unb2c_test
fpga_name : unb2c_test
fpga_description: "FPGA design unb2c_test"
parameters:
- - { name: c_nof_streams_1GbE_UDP, value: 2 }
- - { name: c_def_1GbE_block_size, value: 20 }
- - { name: c_nof_streams_10GbE_UDP, value: 72 }
+ - { name: c_nof_streams_eth0_UDP, value: 4 }
+ - { name: c_nof_streams_10GbE_UDP, value: 72 }
- { name: c_def_10GbE_block_size, value: 900 }
- { name: c_nof_streams_qsfp, value: 24 }
- { name: c_nof_streams_ring, value: 24 }
@@ -39,6 +38,7 @@ peripherals:
- RAM_SCRAP
- peripheral_name: eth/eth
+ peripheral_group: eth0
mm_port_names:
- AVS_ETH_0_TSE
- AVS_ETH_0_REG
@@ -71,47 +71,106 @@ peripherals:
mm_port_names:
- REG_HEATER
- # 1GbE
+ # 1GbE-I
- peripheral_name: diag/diag_block_gen
- peripheral_group: eth_1gbe
+ peripheral_group: eth0_tx
parameter_overrides:
- - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
- - { name: g_buf_dat_w, value: 32 }
- - { name: g_buf_addr_w, value: ceil_log2(c_def_1GbE_block_size) }
+ - { name: g_nof_streams, value: c_nof_streams_eth0_UDP }
+ - { name: g_nof_reg, value: c_nof_streams_eth0_UDP }
+ - { name: g_buf_addr_w, value: 8 }
mm_port_names:
- - REG_DIAG_BG_1GBE
- - RAM_DIAG_BG_1GBE
+ - REG_DIAG_BG_ETH_0
+ - RAM_DIAG_BG_ETH_0_NOT_USED # not used in eth_tester_tx
- - peripheral_name: diag/diag_tx_seq
- peripheral_group: eth_1gbe
+ - peripheral_name: eth_tester_offload_hdr_dat
+ peripheral_group: eth0_tx
+ number_of_peripherals: c_nof_streams_eth0_UDP
+ peripheral_span: ceil_pow2(c_nof_streams_eth0_UDP) * 32 * MM_BUS_SIZE # number_of_ports = 4, mm_port_span = 32 words
+ mm_port_names:
+ - REG_HDR_DAT_ETH_0
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: eth0_tx
parameter_overrides:
- - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
+ - { name: g_nof_streams, value: c_nof_streams_eth0_UDP }
mm_port_names:
- - REG_DIAG_TX_SEQ_1GBE
+ - REG_BSN_MONITOR_V2_TX_ETH_0
- - peripheral_name: dp/dp_bsn_monitor
- peripheral_group: eth_1gbe
+ - peripheral_name: dp/dp_strobe_total_count
+ peripheral_group: eth0_tx
+ number_of_peripherals: c_nof_streams_eth0_UDP
+ peripheral_span: ceil_pow2(c_nof_streams_eth0_UDP) * 32 * MM_BUS_SIZE # number_of_ports = 4, mm_port_span = 32 words
parameter_overrides:
- - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
+ - { name: g_nof_counts, value: 1 } # actual nof counts, <= g_nof_counts_max = 15
+ # 0 = nof_sop
mm_port_names:
- - REG_BSN_MONITOR_1GBE
+ - REG_STROBE_TOTAL_COUNT_TX_ETH_0
- - peripheral_name: diag/diag_data_buffer
- peripheral_group: eth_1gbe
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: eth0_rx
parameter_overrides:
- - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
- - { name: g_data_w, value: 32 }
- - { name: g_nof_data, value: c_def_1GbE_block_size }
+ - { name: g_nof_streams, value: c_nof_streams_eth0_UDP }
mm_port_names:
- - REG_DIAG_DATA_BUFFER_1GBE
- - RAM_DIAG_DATA_BUFFER_1GBE
+ - REG_BSN_MONITOR_V2_RX_ETH_0
- - peripheral_name: diag/diag_rx_seq
- peripheral_group: eth_1gbe
+ - peripheral_name: dp/dp_strobe_total_count
+ peripheral_group: eth0_rx
+ number_of_peripherals: c_nof_streams_eth0_UDP
+ peripheral_span: ceil_pow2(c_nof_streams_eth0_UDP) * 32 * MM_BUS_SIZE # number_of_ports = 4, mm_port_span = 32 words
+ parameter_overrides:
+ - { name: g_nof_counts, value: 3 } # actual nof counts, <= g_nof_counts_max = 15
+ # 0 = nof_sop, 1 = nof_valid, 2 = nof_crc_corrupt
+ mm_port_names:
+ - REG_STROBE_TOTAL_COUNT_RX_ETH_0
+
+ # 1GbE-II
+ - peripheral_name: eth/eth # eth_stream
+ peripheral_group: eth1
+ mm_port_names:
+ - AVS_ETH_1_TSE
+ - AVS_ETH_1_REG # not used for eth_stream
+ - AVS_ETH_1_RAM # not used for eth_stream
+
+ - peripheral_name: diag/diag_block_gen
+ peripheral_group: eth1_tx
+ parameter_overrides:
+ - { name: g_nof_streams, value: 1 }
+ - { name: g_nof_reg, value: 1 }
+ - { name: g_buf_addr_w, value: 8 }
+ mm_port_names:
+ - REG_DIAG_BG_ETH_1
+ - RAM_DIAG_BG_ETH_1_NOT_USED # not used in eth_tester_tx
+
+ - peripheral_name: eth_tester_offload_hdr_dat
+ peripheral_group: eth1_tx
+ mm_port_names:
+ - REG_HDR_DAT_ETH_1
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: eth1_tx
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_TX_ETH_1
+
+ - peripheral_name: dp/dp_strobe_total_count
+ peripheral_group: eth1_tx
+ parameter_overrides:
+ - { name: g_nof_counts, value: 1 } # actual nof counts, <= g_nof_counts_max = 15
+ # 0 = nof_sop
+ mm_port_names:
+ - REG_STROBE_TOTAL_COUNT_TX_ETH_1
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: eth1_rx
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_RX_ETH_1
+
+ - peripheral_name: dp/dp_strobe_total_count
+ peripheral_group: eth1_rx
parameter_overrides:
- - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
+ - { name: g_nof_counts, value: 3 } # actual nof counts, <= g_nof_counts_max = 15
+ # 0 = nof_sop, 1 = nof_valid, 2 = nof_crc_corrupt
mm_port_names:
- - REG_DIAG_TX_SEQ_1GBE
+ - REG_STROBE_TOTAL_COUNT_RX_ETH_1
# 10GbE
- peripheral_name: diag/diag_block_gen
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index 429197e7d13e277f1e30b4d0081f425d09625b9e..eee61c714df8ba91089b8ed81f6c3b59454a6401 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -25,7 +25,7 @@
* Zenodo DOI
* Install OpenSCAD
* Drawio
-
+* DTS-lab unb2c
@@ -115,6 +115,8 @@ during tb simulation load --> fixed by "sudo chmod a+w -R modelsim_altera_libs/1
. remove components
. add components from Uniboard library (double click avs_common_mm or use green +)
use qsys_unb2c_test_ prefix in component name ip file, but rename component without prefix
+ . use periperal names that match the upe_gear default name + instance scheme
+ double click export name to change it, none for default
. System/assign base addresses
System/assign interrupt numbers
if needed do: Sync system infos button
@@ -124,18 +126,32 @@ during tb simulation load --> fixed by "sudo chmod a+w -R modelsim_altera_libs/1
> Copy qsys and ip files to the quartus dir of the mother design.
. cp build/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/*.ip boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/
. cp build/unb2c/quartus/unb2c_test_1GbE_I/qsys_unb2c_test.qsys boards/uniboard2c/designs/unb2c_test/quartus
+> Edit the hdllib.cfg of each revision to include the new peripheral ip files
> The hdllib.cfg of each revision design will copy the qsys and ip files to each
revision build quartus dir, so all revisions use the same qsys.
+# Run command line synthesis for unb2c_test revision
+quartus_config unb2c
+run_qsys_pro unb2c unb2c_test_1GbE_I
+gen_rom_mmap.py --avalon -d unb2c_test -r unb2c_test_1GbE_I
+run_reg unb2c unb2c_test_1GbE_I
+run_qcomp unb2c unb2c_test_1GbE_I --clk=CLK
+run_rbf unb2c unb2c_test_1GbE_I
+==> All in one: build_image unb2c unb2c_test --rev=unb2c_test_1GbE_I --seed=1,2
-
+quartus_config unb2c
+run_qsys_pro unb2c unb2c_test_1GbE_II
+gen_rom_mmap.py --avalon -d unb2c_test -r unb2c_test_1GbE_II
+run_reg unb2c unb2c_test_1GbE_II
+run_qcomp unb2c unb2c_test_1GbE_II --clk=CLK
+run_rbf unb2c unb2c_test_1GbE_II
# Run command line synthesis for dts
quartus_config unb2c
-run_qsys_pro unb2c lofar2_unb2c_sdp_station_full;
-gen_rom_mmap.py --avalon -d lofar2_unb2c_sdp_station -r lofar2_unb2c_sdp_station_full;
-run_reg unb2c lofar2_unb2c_sdp_station_full;
-run_qcomp unb2c lofar2_unb2c_sdp_station_full --clk=CLK;
+run_qsys_pro unb2c lofar2_unb2c_sdp_station_full
+gen_rom_mmap.py --avalon -d lofar2_unb2c_sdp_station -r lofar2_unb2c_sdp_station_full
+run_reg unb2c lofar2_unb2c_sdp_station_full
+run_qcomp unb2c lofar2_unb2c_sdp_station_full --clk=CLK
run_rbf unb2c lofar2_unb2c_sdp_station_full
# Run command line synthesis for sdp-arts
@@ -1154,3 +1170,23 @@ Gelukt !
Oude drawio uninstall mbv Administration/Software Manager
Nieuw heet nu diagrams.net 18.1.3 installed mbv Administration/Software Manager
Alt-F7 to move window on screen
+
+
+
+*******************************************************************************
+* DTS-lab unb2c
+*******************************************************************************
+
+> mystep
+> Program FPGA using USB programmer:
+ > run_quartus unb2c &
+ - Open programmer via button icon --> Hardware setup --> Add hardware
+ Server name 10.87.6.204 (lab laptop) password: uniboard
+ JTAG settings (OK)
+ Hardware settings dubbel click
+ Auto detect
+ Select FPGA --> change file (sof) --> select Program/Reconfigure --> Start
+ > Via dop421 upe_gear:
+ . ./init_upe.sh
+ mkdir reginfo
+ util_unb2.py --unb2 0 --pn2 0:3 --seq REGMAPt
diff --git a/libraries/base/common/src/vhdl/common_mem_pkg.vhd b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
index 27fcd79466c332fc6ece560e5c5cc34b616407ca..dd26500d83613818ffad93645f699eaf5a229ff3 100644
--- a/libraries/base/common/src/vhdl/common_mem_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
@@ -109,7 +109,27 @@ PACKAGE common_mem_pkg IS
FUNCTION RESIZE_MEM_UDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_MEM_SDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- sign extended
FUNCTION RESIZE_MEM_XDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- set unused MSBits to 'X'
-
+
+ ------------------------------------------------------------------------------
+ -- Procedures to access MM bus
+ -- . no mm_clk, combinatoral inputs only, to allow use in a state machine
+ -- . similar proc_mem_mm_bus_*() procs in tb_common_mem_pkg.vhd do have
+ -- mm_clk inputs
+ -- . if mm_copi.waitrequest is used, then issue the MM access and externaly
+ -- check and wait for mm_copi.waitrequest = '0' before removing the MM
+ -- access.
+ ------------------------------------------------------------------------------
+ PROCEDURE proc_mem_bus_wr(CONSTANT wr_addr : IN NATURAL;
+ CONSTANT wr_data : IN INTEGER;
+ SIGNAL mm_copi : OUT t_mem_copi);
+
+ PROCEDURE proc_mem_bus_wr(CONSTANT wr_addr : IN NATURAL;
+ CONSTANT wr_data : IN STD_LOGIC_VECTOR;
+ SIGNAL mm_copi : OUT t_mem_copi);
+
+ PROCEDURE proc_mem_bus_rd(CONSTANT wr_addr : IN NATURAL;
+ SIGNAL mm_copi : OUT t_mem_copi);
+
------------------------------------------------------------------------------
-- Burst memory access (for DDR access interface)
------------------------------------------------------------------------------
@@ -279,7 +299,32 @@ PACKAGE BODY common_mem_pkg IS
v_vec(vec'LENGTH-1 DOWNTO 0) := vec;
RETURN v_vec;
END RESIZE_MEM_XDATA;
-
+
+ -- Procedures to access MM bus
+ PROCEDURE proc_mem_bus_wr(CONSTANT wr_addr : IN NATURAL;
+ CONSTANT wr_data : IN INTEGER;
+ SIGNAL mm_copi : OUT t_mem_copi) IS
+ BEGIN
+ mm_copi.address <= TO_MEM_ADDRESS(wr_addr);
+ mm_copi.wrdata <= TO_MEM_DATA(wr_data);
+ mm_copi.wr <= '1';
+ END proc_mem_bus_wr;
+
+ PROCEDURE proc_mem_bus_wr(CONSTANT wr_addr : IN NATURAL;
+ CONSTANT wr_data : IN STD_LOGIC_VECTOR;
+ SIGNAL mm_copi : OUT t_mem_copi) IS
+ BEGIN
+ mm_copi.address <= TO_MEM_ADDRESS(wr_addr);
+ mm_copi.wrdata <= RESIZE_MEM_DATA(wr_data);
+ mm_copi.wr <= '1';
+ END proc_mem_bus_wr;
+
+ PROCEDURE proc_mem_bus_rd(CONSTANT wr_addr : IN NATURAL;
+ SIGNAL mm_copi : OUT t_mem_copi) IS
+ BEGIN
+ mm_copi.address <= TO_MEM_ADDRESS(wr_addr);
+ mm_copi.rd <= '1';
+ END proc_mem_bus_rd;
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width
FUNCTION TO_MEM_CTLR_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR IS
diff --git a/libraries/base/diag/diag.peripheral.yaml b/libraries/base/diag/diag.peripheral.yaml
index ec4f28671473375570d764b2d7df883483f142e3..5b7932ea9733695a5b0d3ad31e965bfdcfc836d0 100644
--- a/libraries/base/diag/diag.peripheral.yaml
+++ b/libraries/base/diag/diag.peripheral.yaml
@@ -100,10 +100,11 @@ peripherals:
user_width: g_data_w
- peripheral_name: diag_block_gen # pi_diag_block_gen.py
- peripheral_description: "Block generator (BG)"
+ peripheral_description: "Block generator (BG) with g_nof_reg = 1 reg shared by all streams or g_nof_reg = g_nof_streams to have one reg per stream"
parameters:
# Parameters of mms_diag_block_gen.vhd
- { name: g_nof_streams, value: 1 }
+ - { name: g_nof_reg, value: 1 }
- { name: g_buf_dat_w, value: 16 }
- { name: g_buf_addr_w, value: 7 }
mm_ports:
@@ -112,7 +113,7 @@ peripherals:
mm_port_type: REG
mm_port_span: 8 * MM_BUS_SIZE
mm_port_description: "Block generator control."
- number_of_mm_ports: 1
+ number_of_mm_ports: g_nof_reg
fields:
- - field_name: enable
field_description: "Starts the block generator."
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index 6d38ee172529145bc9e302121ef92abc0b6b0f41..23ed67a9ea89b4d4af72a7c355e6e2ecb07e24b6 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -451,7 +451,7 @@ peripherals:
# MM port for dp_strobe_total_count.vhd
- mm_port_name: REG_DP_STROBE_TOTAL_COUNT
mm_port_type: REG
- mm_port_span: ceil_pow2(g_nof_counts_max*2 + 1) * MM_BUS_SIZE
+ mm_port_span: ceil_pow2(g_nof_counts_max*2 + 1) * MM_BUS_SIZE # = 32 * MM_BUS_SIZE
mm_port_description: ""
fields:
- - field_name: counts
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
index 083fd11c107e8efa6570a5e4b7ad7c09839be0eb..c8f9cb39db358df72a7a0fbd4ab161343a341e54 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF dp_fifo_core IS
SIGNAL fifo_wr_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0);
SIGNAL fifo_wr_req : STD_LOGIC;
SIGNAL fifo_wr_ful : STD_LOGIC;
- SIGNAL wr_init : STD_LOGIC := '0';
+ SIGNAL wr_init : STD_LOGIC := '0';
SIGNAL fifo_wr_usedw : STD_LOGIC_VECTOR(wr_usedw'RANGE);
SIGNAL fifo_rd_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
@@ -191,6 +191,7 @@ BEGIN
usedw => fifo_rd_usedw
);
+ wr_init <= '0'; -- to avoid no driver warning in synthesis
fifo_wr_usedw <= fifo_rd_usedw;
END GENERATE;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index 62ddba22104d5a5ff2ba355a63bbe5150b39a20e..9d904f89e2cf577428a406bc5ee0fb2b1530b9f6 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -224,8 +224,7 @@ BEGIN
-- No need to transfer eop counter across clock domains for single clock
gen_rd_eop_cnt_sc : IF g_use_dual_clock=FALSE GENERATE
- wr_fifo_usedw <= rd_fifo_usedw;
- rd_eop_new <= '1';
+ rd_eop_new <= '1';
END GENERATE;
-- Set rd_eop_cnt outside generate statements to avoid Modelsim warning "Nonresolved signal 'rd_eop_cnt' may have multiple sources".
diff --git a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
index 537d5871db8aab4bd9035a22f9567097feff51de..ecd2e6b6fea23856b16269dfba6fa2203f4f6eb3 100644
--- a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
@@ -272,6 +272,12 @@ PACKAGE dp_stream_pkg Is
FUNCTION TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : STD_LOGIC; bsn, data, re, im, empty, channel, err : UNSIGNED) RETURN t_dp_sosi_unsigned;
+ -- Map between array and single element
+ FUNCTION TO_DP_ARR(sosi : t_dp_sosi) RETURN t_dp_sosi_arr;
+ FUNCTION TO_DP_ARR(siso : t_dp_siso) RETURN t_dp_siso_arr;
+ FUNCTION TO_DP_ONE(sosi_arr : t_dp_sosi_arr) RETURN t_dp_sosi;
+ FUNCTION TO_DP_ONE(siso_arr : t_dp_siso_arr) RETURN t_dp_siso;
+
-- Keep part of head data and combine part of tail data, use the other sosi from head_sosi
FUNCTION func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : NATURAL) RETURN t_dp_sosi;
-- Shift and combine part of previous data and this data, use the other sosi from prev_sosi
@@ -638,6 +644,30 @@ PACKAGE BODY dp_stream_pkg IS
RETURN v_sosi_unsigned;
END TO_DP_SOSI_UNSIGNED;
+ -- Map between array and single element
+ FUNCTION TO_DP_ARR(sosi : t_dp_sosi) RETURN t_dp_sosi_arr IS
+ VARIABLE v_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0) := (OTHERS => sosi);
+ BEGIN
+ RETURN v_sosi_arr;
+ END TO_DP_ARR;
+
+ FUNCTION TO_DP_ARR(siso : t_dp_siso) RETURN t_dp_siso_arr IS
+ VARIABLE v_siso_arr : t_dp_siso_arr(0 DOWNTO 0) := (OTHERS => siso);
+ BEGIN
+ RETURN v_siso_arr;
+ END TO_DP_ARR;
+
+ FUNCTION TO_DP_ONE(sosi_arr : t_dp_sosi_arr) RETURN t_dp_sosi IS
+ BEGIN
+ RETURN sosi_arr(0);
+ END TO_DP_ONE;
+
+ FUNCTION TO_DP_ONE(siso_arr : t_dp_siso_arr) RETURN t_dp_siso IS
+ BEGIN
+ RETURN siso_arr(0);
+ END TO_DP_ONE;
+
+
-- Keep part of head data and combine part of tail data
FUNCTION func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : NATURAL) RETURN t_dp_sosi IS
VARIABLE vN : NATURAL := nof_symbols_per_data;
diff --git a/libraries/dsp/si/src/python/si.py b/libraries/dsp/si/src/python/si.py
new file mode 100755
index 0000000000000000000000000000000000000000..3ba02f4000a5220082e1a5d551ff44c1b777a00b
--- /dev/null
+++ b/libraries/dsp/si/src/python/si.py
@@ -0,0 +1,118 @@
+#! /usr/bin/env python3
+###############################################################################
+#
+# Copyright 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+###############################################################################
+
+# Author: Eric Kooistra
+# Date: Nov 2022
+# Purpose:
+# Derive RF frequency of subband center dependend on subband index, Nyquist
+# zone and spectral inversion.
+# Description:
+# The > 1 st Nyquist zones are digitized using sub sampling. The analog
+# filter in the receiver blocks the other Nyquist zones, so that only the
+# wanted Nyquist zone is digitized.
+# The sub sampling act as a mixer that shifts all Nyquist zones down to the
+# first Nyquist zone. The sub sampling causes that the frequency band for
+# all even Nyquist zones gets flipped from hi to lo. This frequency flip can
+# be undone by enabling the spectral inversion for those even Nyquist zones.
+# For ADC sample frequenc f_sample = 200 MHz:
+# 1st Nyquist zone: f = 0 - 100 MHz
+# 2nd Nyquist zone: f = 100 - 200 MHz
+# 3rd Nyquist zone: f = 200 - 300 MHz
+# Spectral inversion flips the frequency bands (Nyquist zones), it does not
+# shift frequencies.
+
+import argparse
+import textwrap
+
+import numpy as np
+import matplotlib
+matplotlib.use('tkagg')
+import matplotlib.pyplot as plt
+
+# Parse arguments to derive user parameters
+_parser = argparse.ArgumentParser(
+ description="".join(textwrap.dedent("""\
+ Calculate RF center frequency for subbands dependend on the Nyquist
+ zone and the spectral inversion control.
+
+ Apply spectral inversion for 2nd Nyquist zone to have increasing
+ subband index correspond to increasing RF frequency:
+
+ > python si.py --si 0 --zi 0 -N 16
+ > python si.py --si 1 --zi 1 -N 16
+ > python si.py --si 0 --zi 2 -N 16
+
+ \n""")),
+ formatter_class=argparse.RawTextHelpFormatter)
+_parser.add_argument('--si', default=0, type=int, help='Spectral inversion control 0 = keep band, 1 = flip band')
+_parser.add_argument('--zi', default=0, type=int, help='Nyquist zone index 0 = 1st, 1 = 2nd, 2 = 3rd, etc')
+_parser.add_argument('-N', default=512, type=int, help='Number of subbands')
+args = _parser.parse_args()
+
+spectral_inv = args.si
+nyquist_zone_index = args.zi
+N_sub = args.N
+
+subbands = np.arange(N_sub) # subband indices
+
+# SDP parameters
+N_complex = 2 # Two complex parts, real and imag
+N_fft = N_sub * N_complex # Number of points of subband filterbank FFT
+f_sample = 200e6 # Hz (ADC sample frequency)
+BW_RF = f_sample / N_complex # = 100 MHz, sampled RF band width of each
+ # Nyquist zone,
+f_sub = f_sample / N_fft # = 195312.5 Hz, subband frequency
+
+# Determine netto result of sub sampling and spectral inversion control
+zone_inv = nyquist_zone_index % N_complex
+
+def boolean_xor(a, b):
+ return (a and not b) or (b and not a)
+
+def natural_xor(a, b):
+ if boolean_xor(a, b):
+ return 1
+ else:
+ return 0
+
+bw_inv = natural_xor(spectral_inv, zone_inv)
+
+# Subband center RF frequency
+f_lo = nyquist_zone_index * BW_RF
+
+n = subbands
+if bw_inv:
+ n = N_sub - 1 - subbands
+
+f_sub_rf = f_lo + n * f_sub
+
+# Plot results
+figNr = 0
+
+figNr += 1
+plt.figure(figNr)
+plt.plot(subbands, f_sub_rf / 1e6, 'o')
+plt.title("spectral_inv = %d, nyquist_zone_index = %d" % (spectral_inv, nyquist_zone_index))
+plt.xlabel("Subband index (range 0:%d)" % (N_sub - 1))
+plt.ylabel("Subband RF frequency [MHz]")
+plt.grid()
+
+plt.show()
diff --git a/libraries/io/eth/hdllib.cfg b/libraries/io/eth/hdllib.cfg
index 11d97855c2d2c66fc69d0db9120c34e4d56095d3..39fcfc924d6665a6a0352057d1689ac17fb4937a 100644
--- a/libraries/io/eth/hdllib.cfg
+++ b/libraries/io/eth/hdllib.cfg
@@ -22,6 +22,8 @@ synth_files =
src/vhdl/eth_control.vhd
src/vhdl/eth_ihl_to_20.vhd
src/vhdl/eth.vhd
+ src/vhdl/eth_stream_udp.vhd
+ src/vhdl/eth_stream.vhd
src/vhdl/eth_tester_pkg.vhd
src/vhdl/eth_tester_tx.vhd
src/vhdl/eth_tester_rx.vhd
@@ -35,8 +37,10 @@ test_bench_files =
tb/vhdl/tb_eth.vhd
tb/vhdl/tb_eth_tester_pkg.vhd
tb/vhdl/tb_eth_tester.vhd
+ tb/vhdl/tb_eth_stream_udp.vhd
tb/vhdl/tb_tb_eth.vhd
tb/vhdl/tb_tb_eth_tester.vhd
+ tb/vhdl/tb_tb_eth_stream_udp.vhd
tb/vhdl/tb_eth_udp_offload.vhd
tb/vhdl/tb_eth_ihl_to_20.vhd
tb/vhdl/tb_tb_tb_eth_regression.vhd
@@ -49,6 +53,7 @@ regression_test_vhdl =
tb/vhdl/tb_eth_ihl_to_20.vhd
tb/vhdl/tb_tb_eth.vhd
tb/vhdl/tb_tb_eth_tester.vhd
+ tb/vhdl/tb_tb_eth_stream_udp.vhd
[modelsim_project_file]
diff --git a/libraries/io/eth/src/vhdl/eth_pkg.vhd b/libraries/io/eth/src/vhdl/eth_pkg.vhd
index eb4f556c1b29f3bd5bc7cb8f949bda396653bc28..632bbb7af95e91fa12763f67831023472e48846d 100644
--- a/libraries/io/eth/src/vhdl/eth_pkg.vhd
+++ b/libraries/io/eth/src/vhdl/eth_pkg.vhd
@@ -86,6 +86,9 @@ PACKAGE eth_pkg IS
CONSTANT c_eth_channel_w : NATURAL := ceil_log2(c_eth_nof_udp_ports + 1); -- + 1 for all other packets that go to the default port
CONSTANT c_eth_nof_channels : NATURAL := 2**c_eth_channel_w;
+ -- Default Rx UDP port for UDP onload
+ CONSTANT c_eth_rx_udp_port : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(6001, 16); -- 0x1771 = 6001
+
------------------------------------------------------------------------------
-- MM register map
------------------------------------------------------------------------------
diff --git a/libraries/io/eth/src/vhdl/eth_stream.vhd b/libraries/io/eth/src/vhdl/eth_stream.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ea47c91393a4503900bef921d609bd7a13e26283
--- /dev/null
+++ b/libraries/io/eth/src/vhdl/eth_stream.vhd
@@ -0,0 +1,179 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author: Eric Kooistra
+-- Purpose:
+-- Provide Ethernet access to a node for one UDP stream via TSE.
+-- Description:
+-- * This eth_stream.vhd is a stripped down version of eth.vhd to offload and
+-- onload one UDP stream.
+-- . see eth_stream_udp.vhd for UDP offload/onload stream details
+-- . contains the TSE
+-- . sets up TSE in state machnine and then switch to external mm_ctlr,
+-- when setup_done = '1', to allow external monitoring of the TSE
+-- . use g_jumbo_en = FALSE to support 1500 octet frames 1518 like in
+-- unb_osy/unbos_eth.h, or use g_jumbo_en = TRUE to support 9000 octet
+-- frames. With g_jumbo_en = FALSE a 9000 octet packet is received
+-- properly, but has rx_src_out.err = 3 indicating invalid length.
+-- Use c_jumbo_en = TRUE to avoid invalid length.
+--
+-- References:
+-- [1] https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+ETH+tester+unit+for+1GbE
+
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_tse_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE work.eth_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY eth_stream IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
+ g_ETH_PHY : STRING := "LVDS"; -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+ g_rx_udp_port : NATURAL := TO_UINT(c_eth_rx_udp_port);
+ g_jumbo_en : BOOLEAN := FALSE;
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0 -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
+ );
+ PORT (
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
+ mm_clk : IN STD_LOGIC; -- memory-mapped bus clock
+ eth_clk : IN STD_LOGIC; -- ethernet phy reference clock
+ st_rst : IN STD_LOGIC; -- reset synchronous with st_clk
+ st_clk : IN STD_LOGIC; -- packet stream clock
+
+ cal_rec_clk : IN STD_LOGIC := '0'; -- Calibration & reconfig clock when using XCVR
+
+ -- TSE setup
+ src_mac : IN STD_LOGIC_VECTOR(c_48-1 DOWNTO 0);
+ setup_done : OUT STD_LOGIC;
+
+ -- UDP transmit interface
+ udp_tx_snk_in : IN t_dp_sosi := c_dp_sosi_rst;
+ udp_tx_snk_out : OUT t_dp_siso;
+
+ -- UDP receive interface
+ udp_rx_src_in : IN t_dp_siso := c_dp_siso_rdy;
+ udp_rx_src_out : OUT t_dp_sosi;
+
+ -- Memory Mapped Slaves
+ tse_ctlr_copi : IN t_mem_mosi; -- ETH TSE MAC registers
+ tse_ctlr_cipo : OUT t_mem_miso;
+
+ -- PHY interface
+ eth_txp : OUT STD_LOGIC;
+ eth_rxp : IN STD_LOGIC;
+
+ -- LED interface
+ tse_led : OUT t_tech_tse_led
+ );
+END eth_stream;
+
+
+ARCHITECTURE str OF eth_stream IS
+
+ -- Tx UDP offload stream to TSE
+ SIGNAL tse_tx_sosi : t_dp_sosi;
+ SIGNAL tse_tx_siso : t_dp_siso;
+
+ -- Rx stream from TSE (contains the UDP onload packets and possibly other
+ -- network packets)
+ SIGNAL tse_rx_sosi : t_dp_sosi;
+ SIGNAL tse_rx_siso : t_dp_siso;
+
+BEGIN
+
+ u_eth_stream_udp : ENTITY work.eth_stream_udp
+ GENERIC MAP (
+ g_rx_udp_port => g_rx_udp_port
+ )
+ PORT MAP (
+ -- Clocks and reset
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- User UDP interface
+ -- . Tx
+ udp_tx_sosi => udp_tx_snk_in,
+ udp_tx_siso => udp_tx_snk_out,
+ -- . Rx
+ udp_rx_sosi => udp_rx_src_out,
+ udp_rx_siso => udp_rx_src_in,
+
+ -- PHY interface
+ -- . Tx
+ tse_tx_sosi => tse_tx_sosi,
+ tse_tx_siso => tse_tx_siso,
+ -- . Rx
+ tse_rx_sosi => tse_rx_sosi,
+ tse_rx_siso => tse_rx_siso
+ );
+
+ u_tech_tse_with_setup : ENTITY tech_tse_lib.tech_tse_with_setup
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_ETH_PHY => g_ETH_PHY,
+ g_jumbo_en => g_jumbo_en,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk, -- MM
+ eth_clk => eth_clk, -- 125 MHz
+ tx_snk_clk => st_rst, -- DP
+ rx_src_clk => st_clk, -- DP
+
+ -- TSE setup
+ src_mac => src_mac,
+ setup_done => setup_done,
+
+ -- Calibration & reconfig clock
+ cal_rec_clk => cal_rec_clk,
+
+ -- Memory Mapped Peripheral
+ mm_ctlr_copi => tse_ctlr_copi,
+ mm_ctlr_cipo => tse_ctlr_cipo,
+
+ -- MAC transmit interface
+ -- . ST sink
+ tx_snk_in => tse_tx_sosi,
+ tx_snk_out => tse_tx_siso,
+
+ -- MAC receive interface
+ -- . ST Source
+ rx_src_in => tse_rx_siso,
+ rx_src_out => tse_rx_sosi,
+
+ -- PHY interface
+ eth_txp => eth_txp,
+ eth_rxp => eth_rxp,
+
+ tse_led => tse_led
+ );
+
+END str;
diff --git a/libraries/io/eth/src/vhdl/eth_stream_udp.vhd b/libraries/io/eth/src/vhdl/eth_stream_udp.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a11b6a23e2ad5f6ec34d32d2b5b43bde787e7c69
--- /dev/null
+++ b/libraries/io/eth/src/vhdl/eth_stream_udp.vhd
@@ -0,0 +1,188 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author: Eric Kooistra
+-- Purpose:
+-- Provide Ethernet access to a node for one UDP stream.
+-- Description:
+-- * This eth_stream_udp.vhd contains the IP/UDP related components of eth.vhd
+-- that are needed to send or receive an UDP stream via 1GbE.
+-- . support only only UDP offload/onload stream.
+-- . the IP checksum is filled in for Tx and checked or Rx.
+-- . the Tx only contains UDP stream data, so no need for a dp_mux.
+-- . the Rx may contain other packet types, because the 1GbE connects to
+-- a network. All Rx packets that are not UDP for g_rx_udp_port are
+-- discarded.
+-- * Use eth_stream.vhd to have eth_stream_udp in combination with the TSE.
+--
+-- References:
+-- [1] https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+ETH+tester+unit+for+1GbE
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.eth_pkg.ALL;
+
+ENTITY eth_stream_udp IS
+ GENERIC (
+ g_rx_udp_port : NATURAL
+ );
+ PORT (
+ -- Clocks and reset
+ st_rst : IN STD_LOGIC;
+ st_clk : IN STD_LOGIC;
+
+ -- User UDP interface
+ -- . Tx
+ udp_tx_sosi : IN t_dp_sosi;
+ udp_tx_siso : OUT t_dp_siso;
+ -- . Rx
+ udp_rx_sosi : OUT t_dp_sosi;
+ udp_rx_siso : IN t_dp_siso := c_dp_siso_rdy;
+
+ -- PHY interface
+ -- . Tx
+ tse_tx_sosi : OUT t_dp_sosi;
+ tse_tx_siso : IN t_dp_siso;
+ -- . Rx
+ tse_rx_sosi : IN t_dp_sosi;
+ tse_rx_siso : OUT t_dp_siso
+ );
+END eth_stream_udp;
+
+
+ARCHITECTURE str OF eth_stream_udp IS
+
+ -- ETH Tx
+ SIGNAL eth_tx_siso : t_dp_siso;
+ SIGNAL eth_tx_sosi : t_dp_sosi;
+
+ -- ETH Rx
+ SIGNAL rx_adapt_siso : t_dp_siso;
+ SIGNAL rx_adapt_sosi : t_dp_sosi;
+
+ SIGNAL rx_hdr_status : t_eth_hdr_status;
+ SIGNAL rx_hdr_status_complete : STD_LOGIC;
+
+ SIGNAL rx_eth_discard : STD_LOGIC;
+ SIGNAL rx_eth_discard_val : STD_LOGIC;
+
+BEGIN
+
+ ------------------------------------------------------------------------------
+ -- TX
+ ------------------------------------------------------------------------------
+
+ -- Insert IP header checksum
+ u_tx_ip : ENTITY work.eth_hdr
+ GENERIC MAP (
+ g_header_store_and_forward => TRUE,
+ g_ip_header_checksum_calculate => TRUE
+ )
+ PORT MAP (
+ -- Clocks and reset
+ rst => st_rst,
+ clk => st_clk,
+
+ -- Streaming Sink
+ snk_in => udp_tx_sosi,
+ snk_out => udp_tx_siso,
+
+ -- Streaming Source
+ src_in => tse_tx_siso,
+ src_out => tse_tx_sosi -- with err field value 0 for OK
+ );
+
+ ------------------------------------------------------------------------------
+ -- RX
+ ------------------------------------------------------------------------------
+
+ -- Adapt the TSE RX source ready latency from 2 to 1
+ u_adapt : ENTITY dp_lib.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => c_eth_rx_ready_latency, -- = 2
+ g_out_latency => c_eth_ready_latency -- = 1
+ )
+ PORT MAP (
+ rst => st_rst,
+ clk => st_clk,
+ -- ST sink
+ snk_out => tse_rx_siso,
+ snk_in => tse_rx_sosi,
+ -- ST source
+ src_in => rx_adapt_siso,
+ src_out => rx_adapt_sosi
+ );
+
+ -- Pass on UDP stream for g_rx_udp_port
+ -- . Verify IP header checksum for IP
+ u_rx_udp : ENTITY work.eth_hdr
+ GENERIC MAP (
+ g_header_store_and_forward => TRUE,
+ g_ip_header_checksum_calculate => TRUE
+ )
+ PORT MAP (
+ -- Clocks and reset
+ rst => st_rst,
+ clk => st_clk,
+
+ -- Streaming Sink
+ snk_in => rx_adapt_sosi,
+ snk_out => rx_adapt_siso,
+
+ -- Streaming Source
+ src_in => udp_rx_siso,
+ src_out => udp_rx_sosi,
+
+ -- Frame control
+ frm_discard => rx_eth_discard,
+ frm_discard_val => rx_eth_discard_val,
+
+ -- Header info
+ hdr_status => rx_hdr_status,
+ hdr_status_complete => rx_hdr_status_complete
+ );
+
+ -- Discard all Rx data that is not UDP for g_rx_udp_port
+ p_rx_discard : PROCESS(st_rst, st_clk)
+ BEGIN
+ IF st_rst = '1' THEN
+ rx_eth_discard <= '1'; -- default discard
+ rx_eth_discard_val <= '0';
+ ELSIF rising_edge(st_clk) THEN
+ -- Default keep rx_eth_discard status (instead of '1'), to more clearly
+ -- see when a change occurs
+ IF rx_hdr_status_complete = '1' THEN
+ rx_eth_discard <= '1'; -- default discard
+ IF rx_hdr_status.is_ip = '1' AND
+ rx_hdr_status.is_udp = '1' AND
+ TO_UINT(rx_hdr_status.udp_port) = g_rx_udp_port THEN
+ rx_eth_discard <= '0'; -- pass on IP/UDP stream for g_rx_udp_port
+ END IF;
+ END IF;
+
+ rx_eth_discard_val <= rx_hdr_status_complete;
+ END IF;
+ END PROCESS;
+
+END str;
diff --git a/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd b/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
index 207728be0545d8f11f45451d303960e31546ab05..defeba8d5c5541a777b972d1a5e296eccf172b61 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
@@ -107,6 +107,9 @@ PACKAGE eth_tester_pkg is
CONSTANT c_eth_tester_ip_src_addr_31_16 : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0A63";
CONSTANT c_eth_tester_udp_src_port_15_8 : STD_LOGIC_VECTOR( 7 DOWNTO 0) := x"E0";
+ -- Default eth_tester Rx UDP port for single stream via 1GbE-II
+ CONSTANT c_eth_tester_eth1g_II_rx_udp_port : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(6001, 16); -- 0x1771 = 6001
+
TYPE t_eth_tester_app_header IS RECORD
dp_length : STD_LOGIC_VECTOR(15 DOWNTO 0);
dp_reserved : STD_LOGIC_VECTOR(14 DOWNTO 0);
diff --git a/libraries/io/eth/src/vhdl/eth_tester_tx.vhd b/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
index d1051404ea32694f5633b233db53fafb86f8e364..0ee2539d169bee295d7e9053d505170e88493e00 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
@@ -82,6 +82,7 @@ ARCHITECTURE str OF eth_tester_tx IS
CONSTANT c_packet_sz_max : NATURAL := ceil_div(c_eth_tester_bg_block_len_max, c_word_sz);
CONSTANT c_fifo_fill : NATURAL := c_packet_sz_max * 11 / 10;
CONSTANT c_fifo_size : NATURAL := true_log_pow2(c_fifo_fill + c_packet_sz_max); -- = 8192
+ CONSTANT c_fifo_size_w : NATURAL := ceil_log2(c_fifo_size);
CONSTANT c_nof_total_counts : NATURAL := 1; -- one to count Tx packets
@@ -101,8 +102,10 @@ ARCHITECTURE str OF eth_tester_tx IS
SIGNAL tx_fifo_data : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL tx_fifo_siso : t_dp_siso;
SIGNAL tx_fifo_wr_ful : STD_LOGIC;
- SIGNAL tx_fifo_wr_usedw : STD_LOGIC_VECTOR(ceil_log2(c_fifo_size)-1 DOWNTO 0);
+ SIGNAL tx_fifo_wr_usedw : STD_LOGIC_VECTOR(c_fifo_size_w-1 DOWNTO 0);
SIGNAL i_tx_fifo_rd_emp : STD_LOGIC;
+ SIGNAL tx_offload_siso : t_dp_siso;
+ SIGNAL tx_offload_sosi : t_dp_sosi;
SIGNAL i_ref_sync : STD_LOGIC := '0';
SIGNAL in_strobe_arr : STD_LOGIC_VECTOR(c_nof_total_counts-1 DOWNTO 0);
@@ -159,9 +162,11 @@ BEGIN
-- BG block level flow control, needed in case BG settings result in eth bit
-- rate > 1 Gbps, to avoid u_tx_fifo overflow.
- p_bg_siso_xon : PROCESS(st_clk)
+ p_bg_siso_xon : PROCESS(st_rst, st_clk)
BEGIN
- IF rising_edge(st_clk) THEN
+ IF st_rst = '1' THEN
+ bg_siso.xon <= '1';
+ ELSIF rising_edge(st_clk) THEN
bg_siso.xon <= '1';
IF TO_UINT(tx_fifo_wr_usedw) > c_fifo_fill THEN
bg_siso.xon <= '0';
@@ -198,19 +203,19 @@ BEGIN
g_fifo_size => c_fifo_size
)
PORT MAP (
- wr_rst => st_rst,
- wr_clk => st_clk,
- rd_rst => st_rst,
- rd_clk => st_clk,
+ wr_rst => st_rst,
+ wr_clk => st_clk,
+ rd_rst => st_rst,
+ rd_clk => st_clk,
-- Monitor FIFO filling
- wr_ful => tx_fifo_wr_ful,
- wr_usedw => tx_fifo_wr_usedw,
- rd_emp => i_tx_fifo_rd_emp,
+ wr_ful => tx_fifo_wr_ful,
+ wr_usedw => tx_fifo_wr_usedw,
+ rd_emp => i_tx_fifo_rd_emp,
-- ST sink
- snk_in => tx_packed_sosi,
+ snk_in => tx_packed_sosi,
-- ST source
- src_in => tx_fifo_siso,
- src_out => tx_fifo_sosi
+ src_in => tx_fifo_siso,
+ src_out => tx_fifo_sosi
);
-------------------------------------------------------------------------------
@@ -295,8 +300,8 @@ BEGIN
snk_in_arr(0) => tx_fifo_sosi,
snk_out_arr(0) => tx_fifo_siso,
- src_out_arr(0) => i_tx_udp_sosi,
- src_in_arr(0) => tx_udp_siso,
+ src_out_arr(0) => tx_offload_sosi,
+ src_in_arr(0) => tx_offload_siso,
hdr_fields_in_arr(0) => hdr_fields_slv_in, -- hdr_fields_slv_in_arr(i) is considered valid @ snk_in_arr(i).sop
hdr_fields_out_arr(0) => hdr_fields_slv_tx
@@ -306,6 +311,22 @@ BEGIN
hdr_fields_rec_in <= func_eth_tester_map_header(hdr_fields_slv_in);
hdr_fields_rec_tx <= func_eth_tester_map_header(hdr_fields_slv_tx);
+
+ -------------------------------------------------------------------------------
+ -- dp_pipeline_ready to ease timing closure
+ -------------------------------------------------------------------------------
+ u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready
+ PORT MAP(
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => tx_offload_siso,
+ snk_in => tx_offload_sosi,
+ src_in => tx_udp_siso,
+ src_out => i_tx_udp_sosi
+ );
+
+
-------------------------------------------------------------------------------
-- Tx packet monitors
-------------------------------------------------------------------------------
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd b/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..95bf74ff0c3a07509b35aaf3ab293d9afefea1e5
--- /dev/null
+++ b/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd
@@ -0,0 +1,436 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- AUthor: E. Kooistra
+-- Purpose: Test bench for eth_stream_udp using eth_tester
+-- Description:
+-- Similar as tb_eth_tester.vhd, but for only one stream and using streaming
+-- interface loop back.
+--
+-- Usage:
+-- > as 8
+-- > run -a
+--
+-- References:
+-- [1] https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+ETH+tester+unit+for+1GbE
+
+LIBRARY IEEE, common_lib, dp_lib, diag_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE work.eth_pkg.ALL;
+USE work.eth_tester_pkg.ALL;
+USE work.tb_eth_tester_pkg.ALL;
+
+ENTITY tb_eth_stream_udp IS
+ GENERIC (
+ g_tb_index : NATURAL := 0; -- use to incremental delay logging from tb instances in tb_tb
+ g_nof_sync : NATURAL := 2; -- number of BG sync intervals to set c_run_time
+ g_udp_port_match : BOOLEAN := TRUE;
+
+ -- t_diag_block_gen_integer =
+ -- sl: enable
+ -- sl: enable_sync
+ -- nat: samples_per_packet
+ -- nat: blocks_per_sync
+ -- nat: gapsize
+ -- nat: mem_low_adrs
+ -- nat: mem_high_adrs
+ -- nat: bsn_init
+ g_bg_ctrl : t_diag_block_gen_integer := ('1', '1', 50, 3, 200, 0, c_diag_bg_mem_max_adr, 0) -- for first stream
+ );
+END tb_eth_stream_udp;
+
+
+ARCHITECTURE tb OF tb_eth_stream_udp IS
+
+ CONSTANT c_tb_str : STRING := "tb-" & NATURAL'IMAGE(g_tb_index) & " : "; -- use to distinguish logging from tb instances in tb_tb
+ CONSTANT mm_clk_period : TIME := 10 ns; -- 100 MHz
+ CONSTANT c_nof_st_clk_per_s : NATURAL := 200 * 10**6;
+ CONSTANT st_clk_period : TIME := (10**9 / c_nof_st_clk_per_s) * 1 ns; -- 5 ns, 200 MHz
+
+ CONSTANT c_bg_block_len : NATURAL := g_bg_ctrl.samples_per_packet;
+ CONSTANT c_bg_slot_len : NATURAL := c_bg_block_len + g_bg_ctrl.gapsize;
+ CONSTANT c_eth_packet_len : NATURAL := func_eth_tester_eth_packet_length(c_bg_block_len);
+
+ -- Use REAL to avoid NATURAL overflow in bps calculation
+ CONSTANT c_bg_nof_bps : REAL := REAL(c_bg_block_len * c_octet_w) * REAL(c_nof_st_clk_per_s) / REAL(c_bg_slot_len);
+ CONSTANT c_bg_sync_period : NATURAL := c_bg_slot_len * g_bg_ctrl.blocks_per_sync;
+
+ CONSTANT c_run_time : NATURAL := g_nof_sync * c_bg_sync_period;
+ CONSTANT c_nof_sync : NATURAL := c_run_time / c_bg_sync_period;
+
+ -- Destination UDP port
+ CONSTANT c_rx_udp_port : NATURAL := TO_UINT(c_eth_tester_udp_dst_port);
+ CONSTANT c_dst_udp_port : NATURAL := sel_a_b(g_udp_port_match, c_rx_udp_port, 17);
+
+ -- Expected Tx --> Rx latency values obtained from a tb run
+ CONSTANT c_tx_exp_latency : NATURAL := 0;
+ CONSTANT c_rx_exp_latency_en : BOOLEAN := c_bg_block_len >= 50;
+ CONSTANT c_rx_exp_latency_st : NATURAL := sel_a_b(g_udp_port_match, 58, 0);
+
+ CONSTANT c_nof_valid_per_packet : NATURAL := c_bg_block_len;
+
+ CONSTANT c_total_count_nof_valid_per_sync : NATURAL := g_bg_ctrl.blocks_per_sync * c_nof_valid_per_packet;
+
+ CONSTANT c_mon_nof_sop_tx : NATURAL := g_bg_ctrl.blocks_per_sync;
+ CONSTANT c_mon_nof_sop_rx : NATURAL := sel_a_b(g_udp_port_match, c_mon_nof_sop_tx, 0);
+ CONSTANT c_mon_nof_valid_tx : NATURAL := c_mon_nof_sop_tx * ceil_div(c_bg_block_len * c_octet_w, c_word_w);
+ CONSTANT c_mon_nof_valid_rx : NATURAL := c_mon_nof_sop_rx * c_nof_valid_per_packet;
+
+ -- Use sim default src MAC, IP, UDP port from eth_tester_pkg.vhd and based on c_gn_index
+ CONSTANT c_gn_index : NATURAL := 17; -- global node index
+ CONSTANT c_gn_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0) := c_eth_tester_eth_src_mac_47_16 & func_eth_tester_gn_index_to_mac_15_0(c_gn_index);
+ CONSTANT c_gn_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0) := c_eth_tester_ip_src_addr_31_16 & func_eth_tester_gn_index_to_ip_15_0(c_gn_index);
+ CONSTANT c_gn_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0) := c_eth_tester_udp_src_port_15_8 & TO_UVEC(c_gn_index, 8);
+
+ -- Clocks and reset
+ SIGNAL mm_rst : STD_LOGIC := '1';
+ SIGNAL mm_clk : STD_LOGIC := '1';
+ SIGNAL st_rst : STD_LOGIC := '1';
+ SIGNAL st_clk : STD_LOGIC := '1';
+ SIGNAL st_pps : STD_LOGIC := '0';
+ SIGNAL stimuli_end : STD_LOGIC := '0';
+ SIGNAL tb_end : STD_LOGIC := '0';
+
+ SIGNAL tx_fifo_rd_emp : STD_LOGIC;
+
+ -- ETH UDP data path interface
+ SIGNAL tx_udp_sosi : t_dp_sosi;
+ SIGNAL tx_udp_siso : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL rx_udp_sosi : t_dp_sosi;
+
+ -- MM interface
+ -- . Tx
+ SIGNAL reg_bg_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bg_ctrl_cipo : t_mem_cipo;
+ SIGNAL reg_hdr_dat_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_hdr_dat_cipo : t_mem_cipo;
+ SIGNAL reg_bsn_monitor_v2_tx_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_tx_cipo : t_mem_cipo;
+ SIGNAL reg_strobe_total_count_tx_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_strobe_total_count_tx_cipo : t_mem_cipo;
+ -- . Rx
+ SIGNAL reg_bsn_monitor_v2_rx_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_rx_cipo : t_mem_cipo;
+ SIGNAL reg_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_strobe_total_count_rx_cipo : t_mem_cipo;
+
+ -- . reg_strobe_total_count
+ SIGNAL tx_total_count_nof_packet : NATURAL;
+ SIGNAL rx_total_count_nof_packet : NATURAL;
+ SIGNAL tx_exp_total_count_nof_packet : NATURAL;
+ SIGNAL rx_exp_total_count_nof_packet : NATURAL;
+
+ SIGNAL rx_total_count_nof_valid : NATURAL;
+ SIGNAL rx_exp_total_count_nof_valid : NATURAL;
+
+ -- . reg_bsn_monitor_v2
+ SIGNAL tx_mon_nof_sop : NATURAL;
+ SIGNAL tx_mon_nof_valid : NATURAL;
+ SIGNAL tx_mon_latency : NATURAL;
+ SIGNAL rx_mon_nof_sop : NATURAL;
+ SIGNAL rx_mon_nof_valid : NATURAL;
+ SIGNAL rx_mon_latency : NATURAL;
+
+ -- ETH stream
+ SIGNAL tse_tx_sosi : t_dp_sosi;
+ SIGNAL tse_tx_siso : t_dp_siso;
+ SIGNAL tse_rx_sosi : t_dp_sosi;
+ SIGNAL tse_rx_siso : t_dp_siso;
+
+ -- View in Wave window
+ SIGNAL dbg_g_bg_ctrl : t_diag_block_gen_integer := g_bg_ctrl;
+ SIGNAL dbg_c_run_time : NATURAL := c_run_time;
+ SIGNAL dbg_c_mon_nof_sop_tx : NATURAL := c_mon_nof_sop_tx;
+ SIGNAL dbg_c_mon_nof_sop_rx : NATURAL := c_mon_nof_sop_rx;
+ SIGNAL dbg_c_mon_nof_valid_tx : NATURAL := c_mon_nof_valid_tx;
+ SIGNAL dbg_c_mon_nof_valid_rx : NATURAL := c_mon_nof_valid_rx;
+
+BEGIN
+
+ mm_clk <= (NOT mm_clk) OR tb_end AFTER mm_clk_period/2;
+ st_clk <= (NOT st_clk) OR tb_end AFTER st_clk_period/2;
+ mm_rst <= '1', '0' AFTER mm_clk_period*5;
+ st_rst <= '1', '0' AFTER st_clk_period*5;
+
+ tx_exp_total_count_nof_packet <= c_nof_sync * g_bg_ctrl.blocks_per_sync;
+ rx_exp_total_count_nof_packet <= sel_a_b(g_udp_port_match, tx_exp_total_count_nof_packet, 0);
+
+ rx_exp_total_count_nof_valid <= sel_a_b(g_udp_port_match, c_nof_sync * c_total_count_nof_valid_per_sync, 0);
+
+ -----------------------------------------------------------------------------
+ -- MM control and monitoring
+ -----------------------------------------------------------------------------
+ p_mm : PROCESS
+ BEGIN
+ tb_end <= '0';
+
+ proc_common_wait_until_low(mm_clk, mm_rst);
+ proc_common_wait_some_cycles(mm_clk, 10);
+
+ ---------------------------------------------------------------------------
+ -- Rx UDP offload port
+ ---------------------------------------------------------------------------
+ -- Set destination MAC/IP/UDP port in tx header
+ -- The MM addresses follow from byte address_offset // 4 in eth.peripheral.yaml
+ proc_mem_mm_bus_wr(16#7#, c_dst_udp_port, mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
+ proc_mem_mm_bus_wr(16#10#, TO_SINT(c_eth_tester_ip_dst_addr), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi); -- use signed to fit 32 b in INTEGER
+ proc_mem_mm_bus_wr(16#18#, TO_SINT(c_eth_tester_eth_dst_mac(31 DOWNTO 0)), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi); -- use signed to fit 32 b in INTEGER
+ proc_mem_mm_bus_wr(16#19#, TO_UINT(c_eth_tester_eth_dst_mac(47 DOWNTO 32)), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
+
+ ---------------------------------------------------------------------------
+ -- Stimuli
+ ---------------------------------------------------------------------------
+ -- Prepare the BG
+ proc_mem_mm_bus_wr(1, g_bg_ctrl.samples_per_packet, mm_clk, reg_bg_ctrl_copi);
+ proc_mem_mm_bus_wr(2, g_bg_ctrl.blocks_per_sync, mm_clk, reg_bg_ctrl_copi);
+ proc_mem_mm_bus_wr(3, g_bg_ctrl.gapsize, mm_clk, reg_bg_ctrl_copi);
+ proc_mem_mm_bus_wr(4, g_bg_ctrl.mem_low_adrs, mm_clk, reg_bg_ctrl_copi);
+ proc_mem_mm_bus_wr(5, g_bg_ctrl.mem_high_adrs, mm_clk, reg_bg_ctrl_copi);
+ proc_mem_mm_bus_wr(6, g_bg_ctrl.bsn_init, mm_clk, reg_bg_ctrl_copi); -- low part
+ proc_mem_mm_bus_wr(7, 0, mm_clk, reg_bg_ctrl_copi); -- high part
+ -- Enable the BG at st_pps pulse.
+ proc_mem_mm_bus_wr(0, 3, mm_clk, reg_bg_ctrl_copi);
+ proc_common_wait_some_cycles(mm_clk, 10);
+ -- Issue an st_pps pulse to start the enabled BG
+ proc_common_gen_pulse(st_clk, st_pps);
+
+ -- Run test
+ proc_common_wait_some_cycles(st_clk, c_run_time);
+
+ -- Disable the BG
+ proc_mem_mm_bus_wr(0, 0, mm_clk, reg_bg_ctrl_copi);
+
+ -- Wait until Tx FIFO has emptied for the stream
+ WHILE tx_fifo_rd_emp /= '1' LOOP
+ proc_common_wait_some_cycles(st_clk, 1);
+ END LOOP;
+ proc_common_wait_some_cycles(st_clk, c_bg_sync_period);
+ stimuli_end <= '1';
+
+ -- Delay logging between different tb instances
+ proc_common_wait_some_cycles(st_clk, g_tb_index * 100);
+
+ -- Print logging
+ print_str(""); -- log empty line between tb results
+ print_str(c_tb_str &
+ "ETH bit rate :" &
+ " c_bg_nof_bps = " & REAL'IMAGE(c_bg_nof_bps) & " bps");
+ ASSERT c_bg_nof_bps < 10.0**9 REPORT "Tx flow control will keep ETH bitrate < 1Gbps." SEVERITY NOTE;
+
+ -------------------------------------------------------------------------
+ -- Verification: Total counts
+ -------------------------------------------------------------------------
+ -- . read low part, ignore high part (= 0) of two word total counts
+ -- Tx total nof packets
+ proc_mem_mm_bus_rd(0, mm_clk, reg_strobe_total_count_tx_cipo, reg_strobe_total_count_tx_copi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ tx_total_count_nof_packet <= TO_UINT(reg_strobe_total_count_tx_cipo.rddata(c_word_w-1 DOWNTO 0));
+ -- Rx total nof packets
+ proc_mem_mm_bus_rd(0, mm_clk, reg_strobe_total_count_rx_cipo, reg_strobe_total_count_rx_copi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rx_total_count_nof_packet <= TO_UINT(reg_strobe_total_count_rx_cipo.rddata(c_word_w-1 DOWNTO 0));
+ -- Rx total nof valids
+ proc_mem_mm_bus_rd(2, mm_clk, reg_strobe_total_count_rx_cipo, reg_strobe_total_count_rx_copi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rx_total_count_nof_valid <= TO_UINT(reg_strobe_total_count_rx_cipo.rddata(c_word_w-1 DOWNTO 0));
+ proc_common_wait_some_cycles(mm_clk, 1);
+
+ -- Print logging
+ print_str(c_tb_str &
+ "Tx total counts monitor :" &
+ " nof_packet = " & NATURAL'IMAGE(tx_total_count_nof_packet));
+
+ print_str(c_tb_str &
+ "Rx total counts monitor :" &
+ " nof_packet = " & NATURAL'IMAGE(rx_total_count_nof_packet) &
+ ", nof_valid = " & NATURAL'IMAGE(rx_total_count_nof_valid));
+
+ -- Verify, only log when wrong
+ IF c_bg_nof_bps < 10.0**9 THEN
+ ASSERT tx_total_count_nof_packet = tx_exp_total_count_nof_packet REPORT c_tb_str &
+ "Wrong Tx total nof packets count, Tx count = " & NATURAL'IMAGE(tx_total_count_nof_packet) &
+ " /= " & NATURAL'IMAGE(tx_exp_total_count_nof_packet) &
+ " = Expected count" SEVERITY ERROR;
+
+ ASSERT rx_total_count_nof_packet = rx_exp_total_count_nof_packet REPORT c_tb_str &
+ "Wrong Rx total nof packets count, Rx count = " & NATURAL'IMAGE(rx_total_count_nof_packet) &
+ " /= " & NATURAL'IMAGE(rx_exp_total_count_nof_packet) &
+ " = Expected count" SEVERITY ERROR;
+
+ ASSERT rx_total_count_nof_valid = rx_exp_total_count_nof_valid REPORT c_tb_str &
+ "Wrong Rx total nof valids count, Rx count = " & NATURAL'IMAGE(rx_total_count_nof_valid) &
+ " /= " & NATURAL'IMAGE(rx_exp_total_count_nof_valid) &
+ " = Expected count" SEVERITY ERROR;
+ END IF;
+
+ -------------------------------------------------------------------------
+ -- Verification: BSN monitors (yield same values in every sync interval)
+ -------------------------------------------------------------------------
+ -- 3 = nof_sop
+ -- 4 = nof_valid
+ -- 6 = latency
+ -- . Tx
+ proc_mem_mm_bus_rd(3, mm_clk, reg_bsn_monitor_v2_tx_cipo, reg_bsn_monitor_v2_tx_copi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ tx_mon_nof_sop <= TO_UINT(reg_bsn_monitor_v2_tx_cipo.rddata(c_word_w-1 DOWNTO 0));
+ proc_mem_mm_bus_rd(4, mm_clk, reg_bsn_monitor_v2_tx_cipo, reg_bsn_monitor_v2_tx_copi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ tx_mon_nof_valid <= TO_UINT(reg_bsn_monitor_v2_tx_cipo.rddata(c_word_w-1 DOWNTO 0));
+ proc_mem_mm_bus_rd(6, mm_clk, reg_bsn_monitor_v2_tx_cipo, reg_bsn_monitor_v2_tx_copi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ tx_mon_latency <= TO_UINT(reg_bsn_monitor_v2_tx_cipo.rddata(c_word_w-1 DOWNTO 0));
+ -- . Rx
+ proc_mem_mm_bus_rd(3, mm_clk, reg_bsn_monitor_v2_rx_cipo, reg_bsn_monitor_v2_rx_copi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rx_mon_nof_sop <= TO_UINT(reg_bsn_monitor_v2_rx_cipo.rddata(c_word_w-1 DOWNTO 0));
+ proc_mem_mm_bus_rd(4, mm_clk, reg_bsn_monitor_v2_rx_cipo, reg_bsn_monitor_v2_rx_copi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rx_mon_nof_valid <= TO_UINT(reg_bsn_monitor_v2_rx_cipo.rddata(c_word_w-1 DOWNTO 0));
+ proc_mem_mm_bus_rd(6, mm_clk, reg_bsn_monitor_v2_rx_cipo, reg_bsn_monitor_v2_rx_copi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rx_mon_latency <= TO_UINT(reg_bsn_monitor_v2_rx_cipo.rddata(c_word_w-1 DOWNTO 0));
+ proc_common_wait_some_cycles(mm_clk, 1);
+
+ -- Print logging
+ print_str(c_tb_str &
+ "Tx BSN monitor :" &
+ " nof_sop = " & NATURAL'IMAGE(tx_mon_nof_sop) &
+ ", nof_valid = " & NATURAL'IMAGE(tx_mon_nof_valid) &
+ ", latency = " & NATURAL'IMAGE(tx_mon_latency));
+
+ print_str(c_tb_str &
+ "Rx BSN monitor :" &
+ " nof_sop = " & NATURAL'IMAGE(rx_mon_nof_sop) &
+ ", nof_valid = " & NATURAL'IMAGE(rx_mon_nof_valid) &
+ ", latency = " & NATURAL'IMAGE(rx_mon_latency));
+
+ IF c_bg_nof_bps < 10.0**9 THEN
+ -- Verify BSN monitors only when the BG sync interval is stable, so
+ -- the ETH data rate < 1 Gbps and no BG block flow control.
+ -- Verify, only log when wrong
+ ASSERT tx_mon_nof_sop = c_mon_nof_sop_tx REPORT c_tb_str & "Wrong tx nof_sop" SEVERITY ERROR;
+ ASSERT rx_mon_nof_sop = c_mon_nof_sop_rx REPORT c_tb_str & "Wrong rx nof_sop" SEVERITY ERROR;
+ ASSERT tx_mon_nof_valid = c_mon_nof_valid_tx REPORT c_tb_str & "Wrong tx nof_valid" SEVERITY ERROR;
+ ASSERT rx_mon_nof_valid = c_mon_nof_valid_rx REPORT c_tb_str & "Wrong rx nof_valid" SEVERITY ERROR;
+ ASSERT tx_mon_latency = c_tx_exp_latency REPORT c_tb_str & "Wrong tx latency" SEVERITY ERROR;
+
+ -- For short block lengths the Rx latency appears to become less, the
+ -- exact Rx latency is therefore hard to predetermine. The actual
+ -- latency is not critical, therefore it is sufficient to only very
+ -- the latency when it is more or less fixed.
+ IF c_rx_exp_latency_en THEN
+ ASSERT almost_equal(rx_mon_latency, c_rx_exp_latency_st, 0) REPORT
+ c_tb_str & "Wrong rx latency using st interface" SEVERITY ERROR;
+ END IF;
+ END IF;
+
+ -------------------------------------------------------------------------
+ -- End of test
+ -------------------------------------------------------------------------
+ proc_common_wait_some_cycles(mm_clk, 100);
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ u_eth_tester : ENTITY work.eth_tester
+ GENERIC MAP (
+ g_nof_streams => 1,
+ g_bg_sync_timeout => c_eth_tester_sync_timeout,
+ g_remove_crc => FALSE -- no CRC with streaming loopback
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_pps => st_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => c_gn_eth_src_mac,
+ ip_src_addr => c_gn_ip_src_addr,
+ udp_src_port => c_gn_udp_src_port,
+
+ sl(tx_fifo_rd_emp_arr) => tx_fifo_rd_emp,
+
+ TO_DP_ONE(tx_udp_sosi_arr) => tx_udp_sosi,
+ tx_udp_siso_arr => TO_DP_ARR(tx_udp_siso),
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => TO_DP_ARR(rx_udp_sosi),
+
+ -- Memory Mapped Slaves (one per stream)
+ -- . Tx
+ reg_bg_ctrl_copi => reg_bg_ctrl_copi,
+ reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
+ -- . Rx
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
+ );
+
+
+ -- ETH stream
+ u_dut : ENTITY work.eth_stream_udp
+ GENERIC MAP (
+ g_rx_udp_port => c_rx_udp_port
+ )
+ PORT MAP (
+ -- Clocks and reset
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- User UDP interface
+ -- . Tx
+ udp_tx_sosi => tx_udp_sosi,
+ udp_tx_siso => tx_udp_siso,
+ -- . Rx
+ udp_rx_sosi => rx_udp_sosi,
+ udp_rx_siso => c_dp_siso_rdy,
+
+ -- PHY interface
+ -- . Tx
+ tse_tx_sosi => tse_tx_sosi,
+ tse_tx_siso => tse_tx_siso,
+ -- . Rx
+ tse_rx_sosi => tse_rx_sosi,
+ tse_rx_siso => tse_rx_siso
+ );
+
+ -- Loopback wire Tx to Rx, register to increasy ready latency from 1 to 2
+ tse_rx_sosi <= tse_tx_sosi WHEN rising_edge(st_clk);
+ tse_tx_siso <= tse_rx_siso;
+
+END tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
index 8ca739e98fcfacc242c044c470a00d290ef17097..8cd8710c7db6fc600784ddd6839be0b851ba9223 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
@@ -118,9 +118,9 @@ ARCHITECTURE tb OF tb_eth_tester IS
-- Expected Tx --> Rx latency values obtained from a tb run
CONSTANT c_tx_exp_latency : NATURAL := 0;
CONSTANT c_rx_exp_latency_en : BOOLEAN := c_bg_block_len_max >= 50;
- CONSTANT c_rx_exp_latency_st : NATURAL := 27;
- CONSTANT c_rx_exp_latency_sim_tse : NATURAL := 165;
- CONSTANT c_rx_exp_latency_tech_tse : NATURAL := 375;
+ CONSTANT c_rx_exp_latency_st : NATURAL := 28;
+ CONSTANT c_rx_exp_latency_sim_tse : NATURAL := 167;
+ CONSTANT c_rx_exp_latency_tech_tse : NATURAL := 372;
-- CRC is added by Tx TSE IP and removed by dp_offload_rx when g_remove_crc =
-- g_loopback_eth = TRUE. Therefore internally only application payload
@@ -522,7 +522,7 @@ BEGIN
END IF;
END IF;
ELSE
- ASSERT almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_st, 0) REPORT
+ ASSERT almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_st, 10) REPORT
c_tb_str & "Wrong rx latency using st interface (" & NATURAL'IMAGE(I) & ")" SEVERITY ERROR;
END IF;
END IF;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
index 4705b6f018f3b1f657ee08fd7ee846a909855ef8..93ca1f7791404443c6bcde867d3aada200646a1c 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
@@ -37,7 +37,7 @@ PACKAGE tb_eth_tester_pkg is
CONSTANT c_eth_tester_eth_dst_mac : STD_LOGIC_VECTOR(47 DOWNTO 0) := x"001B217176B9"; -- 001B217176B9 = DOP36-enp2s0
CONSTANT c_eth_tester_ip_dst_addr : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"0A6300FE"; -- 0A6300FE = '10.99.0.254' = DOP36-enp2s0
- CONSTANT c_eth_tester_udp_dst_port : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(6001, 16); -- 0x1771 = 6001
+ CONSTANT c_eth_tester_udp_dst_port : STD_LOGIC_VECTOR(15 DOWNTO 0) := c_eth_tester_eth1g_II_rx_udp_port;
-- Ethernet packet length in octets inclduing eth header and CRC
FUNCTION func_eth_tester_eth_packet_length(block_len : NATURAL) RETURN NATURAL;
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth_stream_udp.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth_stream_udp.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..82b1b5710af83a767611c835c6d6c34005ab299d
--- /dev/null
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth_stream_udp.vhd
@@ -0,0 +1,80 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: E. Kooistra
+-- Purpose: Multi test bench for eth_stream_udp
+-- Description:
+--
+-- Usage:
+-- > as 8
+-- > run -all
+
+LIBRARY IEEE, diag_lib;
+USE IEEE.std_logic_1164.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE work.tb_eth_tester_pkg.ALL;
+
+ENTITY tb_tb_eth_stream_udp IS
+END tb_tb_eth_stream_udp;
+
+ARCHITECTURE tb OF tb_tb_eth_stream_udp IS
+
+ -- Tb
+ CONSTANT c_eth_clk_MHz : NATURAL := 125;
+ CONSTANT c_st_clk_MHz : NATURAL := 200;
+ CONSTANT c_nof_sync : NATURAL := 2;
+ CONSTANT c_nof_blk : NATURAL := 3; -- nof_blk per sync
+
+ -- Tx packet size and gap size in octets
+ CONSTANT c_block_len : NATURAL := 50;
+ CONSTANT c_link_len : NATURAL := func_eth_tester_eth_packet_on_link_length(c_block_len);
+
+ -- For near maximum 1Gbps link rate the c_block_len + c_gap_len_min time
+ -- in the st_clk domain equals c_link_len time in eth_clk domain.
+ CONSTANT c_gap_len_min : NATURAL := c_link_len * c_st_clk_MHz / c_eth_clk_MHz - c_block_len;
+
+ -- Choose c_gap_len somewhat larger to have packet link rate < 1 Gbps
+ CONSTANT c_gap_len : NATURAL := c_gap_len_min * 2; -- for g_nof_streams = 1
+
+ -- BG ctrl
+ CONSTANT c_high : NATURAL := c_diag_bg_mem_max_adr; -- = 2**24
+
+ CONSTANT c_bg_ctrl : t_diag_block_gen_integer := ('1', '1', c_block_len, c_nof_blk, c_gap_len, 0, c_high, 0); -- for first stream
+
+BEGIN
+
+-- g_tb_index : NATURAL := 0; -- use to incremental delay logging from tb instances in tb_tb
+-- g_nof_sync : NATURAL := 2; -- number of BG sync intervals to set c_run_time
+-- g_udp_port_match : BOOLEAN := TRUE;
+--
+-- -- t_diag_block_gen_integer =
+-- -- sl: enable
+-- -- sl: enable_sync
+-- -- nat: samples_per_packet
+-- -- nat: blocks_per_sync
+-- -- nat: gapsize
+-- -- nat: mem_low_adrs
+-- -- nat: mem_high_adrs
+-- -- nat: bsn_init
+-- g_bg_ctrl : t_diag_block_gen_integer := ('1', '1', 50, 3, 200, 0, c_diag_bg_mem_max_adr, 0) -- for first stream
+
+ u_udp : ENTITY work.tb_eth_stream_udp GENERIC MAP (0, c_nof_sync, TRUE, c_bg_ctrl);
+ u_udp_mismatch : ENTITY work.tb_eth_stream_udp GENERIC MAP (1, c_nof_sync, FALSE, c_bg_ctrl);
+
+END tb;
diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg
index 5b71fe5191e51bac29016fed57641fab7f0cfcc8..86bd3ec8218f5f562c477a4dde02f407d2a573b8 100644
--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -29,16 +29,20 @@ synth_files =
tech_tse_arria10_e1sg.vhd
tech_tse_arria10_e2sg.vhd
tech_tse.vhd
+ tech_tse_setup.vhd
+ tech_tse_with_setup.vhd
tb_tech_tse_pkg.vhd
test_bench_files =
sim_tse.vhd
tb_tech_tse_pkg.vhd
tb_tech_tse.vhd
+ tb_tech_tse_with_setup.vhd
tb_tb_tech_tse.vhd
regression_test_vhdl =
tb_tb_tech_tse.vhd
+ tb_tech_tse_with_setup.vhd
[modelsim_project_file]
diff --git a/libraries/technology/tse/tb_tech_tse.vhd b/libraries/technology/tse/tb_tech_tse.vhd
index ce074ce5673c8b798bdc26a7f934adb1e5cebddd..5c43594f5cb322abd32f0a8a382cdfd934214401 100644
--- a/libraries/technology/tse/tb_tech_tse.vhd
+++ b/libraries/technology/tse/tb_tech_tse.vhd
@@ -50,7 +50,7 @@ ENTITY tb_tech_tse IS
-- g_data_type = c_tb_tech_tse_data_type_counter = 1
g_data_type : NATURAL := c_tb_tech_tse_data_type_symbols;
g_sim : BOOLEAN := TRUE;
- g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model;
g_tb_end : BOOLEAN := TRUE -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
);
PORT (
@@ -100,7 +100,9 @@ ARCHITECTURE tb OF tb_tech_tse IS
SIGNAL mm_init : STD_LOGIC := '1';
SIGNAL mm_miso : t_mem_miso;
SIGNAL mm_mosi : t_mem_mosi;
-
+ SIGNAL mm_wrdata : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- for view in Wave window
+ SIGNAL mm_rddata : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- for view in Wave window
+
SIGNAL mm_psc_access : STD_LOGIC;
-- TSE MAC transmit interface
@@ -116,6 +118,7 @@ ARCHITECTURE tb OF tb_tech_tse IS
-- . The tb is the ST sink
SIGNAL rx_sosi : t_dp_sosi;
SIGNAL rx_siso : t_dp_siso;
+ SIGNAL rx_data : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- for view in Wave window
-- . MAC specific
SIGNAL rx_mac_out : t_tech_tse_rx_mac;
@@ -143,6 +146,10 @@ BEGIN
total_header_loopback.eth <= c_eth_header_loopback;
total_header_etherlen.eth <= c_eth_header_etherlen;
+ mm_wrdata <= mm_mosi.wrdata(c_word_w-1 DOWNTO 0);
+ mm_rddata <= mm_miso.rddata(c_word_w-1 DOWNTO 0);
+ rx_data <= rx_sosi.data(c_word_w-1 DOWNTO 0);
+
p_mm_setup : PROCESS
BEGIN
mm_init <= '1';
diff --git a/libraries/technology/tse/tb_tech_tse_with_setup.vhd b/libraries/technology/tse/tb_tech_tse_with_setup.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1d57745fcc2dca0c6323b6df2e2e3b0a97f3941f
--- /dev/null
+++ b/libraries/technology/tse/tb_tech_tse_with_setup.vhd
@@ -0,0 +1,315 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Testbench for tech_tse for the Tripple Speed Ethernet IP technology
+-- wrapper, with setup.
+-- Description:
+-- Same tb as tb_tech_tse.vhd, but instead:
+-- . fixed use TSE IP (c_sim_level = 0)
+-- . using TSE setup in DUT
+-- . verify external MM access to TSE after setup in p_mm_setup.
+-- . use c_jumbo_en = FALSE for maximum 1500 packet size as with unb_osy, a
+-- 9000 octet packet is received properly, but has rx_src_out.err = 3
+-- indicating invalid length. Use c_jumbo_en = TRUE to avoid invalid
+-- length.
+-- Usage:
+-- > as 10
+-- > run -all
+
+LIBRARY IEEE, technology_lib, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE WORK.tech_tse_pkg.ALL;
+USE WORK.tb_tech_tse_pkg.ALL;
+
+
+ENTITY tb_tech_tse_with_setup IS
+ -- Test bench control parameters
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
+ -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
+ -- g_data_type = c_tb_tech_tse_data_type_counter = 1
+ g_data_type : NATURAL := c_tb_tech_tse_data_type_symbols;
+ g_tb_end : BOOLEAN := TRUE -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ );
+ PORT (
+ tb_end : OUT STD_LOGIC
+ );
+END tb_tech_tse_with_setup;
+
+
+ARCHITECTURE tb OF tb_tech_tse_with_setup IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model;
+ CONSTANT c_jumbo_en : BOOLEAN := TRUE;
+
+ CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz
+ CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz
+ CONSTANT cable_delay : TIME := sel_a_b(c_sim_level=0, 12 ns, 0 ns);
+
+ CONSTANT c_promis_en : BOOLEAN := FALSE;
+ CONSTANT c_tx_ready_latency : NATURAL := c_tech_tse_tx_ready_latency; -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
+ CONSTANT c_nof_tx_not_valid : NATURAL := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+
+ --CONSTANT c_pkt_length_arr : t_nat_natural_arr := (0, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 1472, 1473, 9000);
+ CONSTANT c_pkt_length_arr : t_nat_natural_arr := array_init(0, 80, 1) & array_init(1499, 2, 1) & 9000;
+ CONSTANT c_nof_pkt : NATURAL := c_pkt_length_arr'LENGTH;
+
+ CONSTANT c_dst_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"10FA01020300";
+ CONSTANT c_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ CONSTANT c_ethertype : STD_LOGIC_VECTOR(c_network_eth_type_slv'RANGE) := X"10FA";
+ CONSTANT c_etherlen : STD_LOGIC_VECTOR(c_network_eth_type_slv'RANGE) := "0000000000010000";
+
+ -- Packet headers
+ CONSTANT c_eth_header_loopback : t_network_eth_header := (c_src_mac, c_src_mac, c_ethertype);
+ CONSTANT c_eth_header_etherlen : t_network_eth_header := (c_src_mac, c_src_mac, c_etherlen);
+
+ SIGNAL total_header_loopback : t_network_total_header;
+ SIGNAL total_header_etherlen : t_network_total_header;
+
+ -- Clocks and reset
+ SIGNAL rx_end : STD_LOGIC := '0';
+ SIGNAL eth_clk : STD_LOGIC := '0'; -- tse reference clock
+ SIGNAL sys_clk : STD_LOGIC := '0'; -- system clock
+ SIGNAL st_clk : STD_LOGIC; -- stream clock
+ SIGNAL mm_clk : STD_LOGIC; -- memory-mapped bus clock
+ SIGNAL mm_rst : STD_LOGIC; -- reset synchronous with mm_clk
+
+ -- TSE MAC control interface
+ SIGNAL tse_setup_done : STD_LOGIC;
+
+ SIGNAL mm_init : STD_LOGIC := '1';
+ SIGNAL mm_copi : t_mem_copi;
+ SIGNAL mm_cipo : t_mem_cipo;
+ SIGNAL mm_rddata : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- for view in Wave window
+
+ -- TSE MAC transmit interface
+ -- . The tb is the ST source
+ SIGNAL tx_en : STD_LOGIC := '1';
+ SIGNAL tx_siso : t_dp_siso;
+ SIGNAL tx_sosi : t_dp_sosi;
+ -- . MAC specific
+ SIGNAL tx_mac_in : t_tech_tse_tx_mac;
+ SIGNAL tx_mac_out : t_tech_tse_tx_mac;
+
+ -- TSE MAC receive interface
+ -- . The tb is the ST sink
+ SIGNAL rx_sosi : t_dp_sosi;
+ SIGNAL rx_siso : t_dp_siso;
+ SIGNAL rx_data : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- for view in Wave window
+ -- . MAC specific
+ SIGNAL rx_mac_out : t_tech_tse_rx_mac;
+
+ -- TSE PHY interface
+ SIGNAL eth_txp : STD_LOGIC;
+ SIGNAL eth_rxp : STD_LOGIC;
+
+ SIGNAL tse_led : t_tech_tse_led;
+
+ -- Verification
+ SIGNAL tx_pkt_cnt : NATURAL := 0;
+ SIGNAL rx_pkt_cnt : NATURAL := 0;
+
+BEGIN
+
+ eth_clk <= NOT eth_clk AFTER eth_clk_period/2; -- TSE reference clock
+ sys_clk <= NOT sys_clk AFTER sys_clk_period/2; -- System clock
+
+ mm_clk <= sys_clk;
+ st_clk <= sys_clk;
+
+ -- Use signal to leave unused fields 'X'
+ total_header_loopback.eth <= c_eth_header_loopback;
+ total_header_etherlen.eth <= c_eth_header_etherlen;
+
+ mm_rddata <= mm_cipo.rddata(c_word_w-1 DOWNTO 0);
+ rx_data <= rx_sosi.data(c_word_w-1 DOWNTO 0);
+
+ p_mm_setup : PROCESS
+ VARIABLE v_version : NATURAL;
+ BEGIN
+ mm_init <= '1';
+ mm_copi.wr <= '0';
+ mm_copi.rd <= '0';
+
+ -- reset release
+ mm_rst <= '1';
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
+ mm_rst <= '0';
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
+
+ -- Wait for tech_tse_with_setup to finish MM access to TSE
+ proc_common_wait_until_high(mm_clk, tse_setup_done);
+ proc_common_wait_some_cycles(mm_clk, 10);
+
+ -- Verify external MM access to TSE
+ proc_mem_mm_bus_rd(16#000#, mm_clk, mm_cipo, mm_copi); -- REV --> CUST_VERSION & 0x0901, 0x1200, 0x1304
+ CASE c_tech_select_default IS
+ WHEN c_tech_stratixiv => v_version := 16#0901#; -- unb1
+ WHEN c_tech_arria10_e1sg => v_version := 16#1200#; -- unb2b
+ WHEN c_tech_arria10_e2sg => v_version := 16#1304#; -- unb2c
+ WHEN OTHERS => v_version := 0; -- default
+ END CASE;
+ ASSERT UNSIGNED(mm_rddata(c_16-1 DOWNTO 0)) = v_version REPORT "Wrong external MM read access result." SEVERITY ERROR;
+
+ -- Wait for link synchronisation
+ proc_common_wait_until_high(mm_clk, tse_led.link);
+ proc_common_wait_some_cycles(mm_clk, 10);
+
+ mm_init <= '0';
+ WAIT;
+ END PROCESS;
+
+
+ p_ff_transmitter : PROCESS
+ BEGIN
+ -- . Avalon ST
+ tx_sosi.data <= (OTHERS=>'0');
+ tx_sosi.valid <= '0';
+ tx_sosi.sop <= '0';
+ tx_sosi.eop <= '0';
+ tx_sosi.empty <= (OTHERS=>'0');
+ tx_sosi.err <= (OTHERS=>'0');
+ -- . MAC specific
+ tx_mac_in.crc_fwd <= '0'; -- when '0' then TSE MAC generates the TX CRC field
+
+ WHILE mm_init/='0' LOOP
+ WAIT UNTIL rising_edge(st_clk);
+ END LOOP;
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(st_clk); END LOOP;
+
+ -- Loopback txp->rxp so DST_MAC = c_src_mac to send to itself
+
+ -- TX frame:
+ -- . I=0 is empty payload, so only 4 words of the ETH header with 46 padding zeros, so empty = 2
+ -- . For I=1 to 46 the payload length remains 46 with padding zeros, so empty = 2
+ -- . For I>46 the payload length is I and empty = 4 - (I mod 4)
+
+ FOR I IN 0 TO c_nof_pkt-1 LOOP
+ proc_tech_tse_tx_packet(total_header_loopback, c_pkt_length_arr(I), g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+ END LOOP;
+
+ FOR I IN 0 TO 1500 * 2 LOOP WAIT UNTIL rising_edge(st_clk); END LOOP;
+ rx_end <= '1';
+ WAIT;
+ END PROCESS;
+
+
+ p_ff_receiver : PROCESS
+ BEGIN
+ -- . Avalon ST
+ rx_siso.ready <= '0';
+
+ WHILE mm_init/='0' LOOP
+ WAIT UNTIL rising_edge(st_clk);
+ END LOOP;
+
+ -- Receive forever
+ WHILE TRUE LOOP
+ proc_tech_tse_rx_packet(total_header_loopback, g_data_type, st_clk, rx_sosi, rx_siso);
+ END LOOP;
+
+ WAIT;
+ END PROCESS;
+
+
+ dut : ENTITY work.tech_tse_with_setup
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_ETH_PHY => "LVDS", -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+ g_jumbo_en => c_jumbo_en,
+ g_sim => c_sim,
+ g_sim_level => c_sim_level -- 0 = use IP; 1 = use fast serdes model;
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ eth_clk => eth_clk,
+ tx_snk_clk => st_clk,
+ rx_src_clk => st_clk,
+
+ -- TSE setup
+ src_mac => c_src_mac,
+ setup_done => tse_setup_done,
+
+ -- Memory Mapped Slave
+ mm_ctlr_copi => mm_copi,
+ mm_ctlr_cipo => mm_cipo,
+
+ -- MAC transmit interface
+ -- . ST sink
+ tx_snk_in => tx_sosi,
+ tx_snk_out => tx_siso,
+
+ -- MAC receive interface
+ -- . ST Source
+ rx_src_in => rx_siso,
+ rx_src_out => rx_sosi,
+
+ -- PHY interface
+ eth_txp => eth_txp,
+ eth_rxp => eth_rxp,
+
+ tse_led => tse_led
+ );
+
+ -- Loopback
+ eth_rxp <= TRANSPORT eth_txp AFTER cable_delay;
+
+ -- Verification
+ tx_pkt_cnt <= tx_pkt_cnt + 1 WHEN tx_sosi.sop='1' AND rising_edge(st_clk);
+ rx_pkt_cnt <= rx_pkt_cnt + 1 WHEN rx_sosi.eop='1' AND rising_edge(st_clk);
+
+ p_verify : PROCESS
+ BEGIN
+ tb_end <= '0';
+ WAIT UNTIL rx_end='1';
+ -- Verify that all transmitted packets have been received
+ IF tx_pkt_cnt=0 THEN
+ REPORT "No packets were transmitted." SEVERITY ERROR;
+ ELSIF rx_pkt_cnt=0 THEN
+ REPORT "No packets were received." SEVERITY ERROR;
+ ELSIF tx_pkt_cnt/=rx_pkt_cnt THEN
+ REPORT "Not all transmitted packets were received." SEVERITY ERROR;
+ END IF;
+ tb_end <= '1';
+
+ WAIT FOR 1 ns;
+ IF g_tb_end=FALSE THEN
+ REPORT "Tb simulation finished." SEVERITY NOTE;
+ ELSE
+ REPORT "Tb simulation finished." SEVERITY FAILURE;
+ END IF;
+ WAIT;
+ END PROCESS;
+
+END tb;
diff --git a/libraries/technology/tse/tech_tse_setup.vhd b/libraries/technology/tse/tech_tse_setup.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fc02da2dc47117ca8647e27f75e60cd68577433b
--- /dev/null
+++ b/libraries/technology/tse/tech_tse_setup.vhd
@@ -0,0 +1,259 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- AUthor: E. Kooistra
+-- Purpose: Set up TSE via MM
+-- Description:
+-- . TSE set up as in tb_tech_tse_pkg, unb_osy/unbos_eth.c and
+-- eth1g_master.vhd. Cannot use proc_mem_mm_bus_*() because a synthesis
+-- process can only have one rising_edge(mm_clk) statement
+-- . After tse_init is done, then connect to external MM controller, to allow
+-- external monitoring of the TSE.
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.tech_tse_pkg.ALL;
+
+ENTITY tech_tse_setup IS
+ GENERIC (
+ g_sim : BOOLEAN;
+ -- Nios 1GbE-I uses ETH_FRAME_LENGTH = 1518 in inbos_eth.h. Use g_jumbo_en
+ -- = FALSE for frame_len <= 1500 octets. If frame is longer then this
+ -- yields invalid length flag in rx_sosi.err, but data is still received.
+ -- Use g_jumbo_en = TRUE for frame_len <= 9000 octets (jumbo frames).
+ g_jumbo_en : BOOLEAN := FALSE
+ );
+ PORT (
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ -- TSE setup
+ src_mac : IN STD_LOGIC_VECTOR(c_48-1 DOWNTO 0);
+ setup_done : OUT STD_LOGIC;
+
+ -- Memory Mapped Peripheral
+ -- . Controller side
+ mm_ctlr_copi : IN t_mem_copi;
+ mm_ctlr_cipo : OUT t_mem_cipo;
+ -- . Peripheral side
+ mm_peri_copi : OUT t_mem_copi;
+ mm_peri_cipo : IN t_mem_cipo
+ );
+END tech_tse_setup;
+
+ARCHITECTURE rtl OF tech_tse_setup IS
+
+ -- FALSE receive only frames for this src_mac and broadcast, TRUE receive all
+ CONSTANT c_promis_en : BOOLEAN := FALSE;
+
+ -- Access the MM bus
+ TYPE t_state IS (s_rd_pcs_rev, s_wr_if_mode, s_rd_control, s_rd_status, s_wr_control,
+ s_rd_mac_rev, s_wr_promis_en, s_wr_mac_0, s_wr_mac_1, s_wr_tx_ipg_len, s_wr_frm_len,
+ s_wr_rx_section_empty, s_wr_rx_section_full, s_wr_tx_section_empty, s_wr_tx_section_full,
+ s_wr_rx_almost_empty, s_wr_rx_almost_full, s_wr_tx_almost_empty, s_wr_tx_almost_full,
+ s_rd_tx_cmd_stat, s_rd_rx_cmd_stat,
+ s_done);
+
+ SIGNAL state : t_state;
+ SIGNAL next_state : t_state;
+ SIGNAL psc_access : STD_LOGIC; -- active during PCS registers access, for view in Wave window
+ SIGNAL fifo_access : STD_LOGIC; -- active during FIFO registers access, for view in Wave window
+
+ -- Memory Mapped Slave
+ SIGNAL tse_init : STD_LOGIC := '1';
+ SIGNAL tse_ctlr_copi : t_mem_copi;
+ SIGNAL tse_ctlr_cipo : t_mem_cipo;
+ SIGNAL tse_waitrequest : STD_LOGIC;
+ SIGNAL tse_wrdata : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- for view in Wave window
+ SIGNAL tse_rddata : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- for view in Wave window
+
+ SIGNAL src_mac_0 : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+ SIGNAL src_mac_1 : STD_LOGIC_VECTOR(c_16-1 DOWNTO 0);
+
+BEGIN
+
+ setup_done <= NOT tse_init;
+
+ src_mac_0 <= hton(src_mac(c_48-1 DOWNTO c_16), 4);
+ src_mac_1 <= hton(src_mac(c_16-1 DOWNTO 0), 2);
+
+ -- Select MM interface controller
+ -- ___
+ -- | |
+ -- mm_ctlr ----| 0 |
+ -- | |---- mm_peri
+ -- tse_ctlr ----| 1 |
+ -- |___|
+ -- |
+ -- tse_init ------/
+ --
+ mm_peri_copi <= tse_ctlr_copi WHEN tse_init = '1' ELSE mm_ctlr_copi;
+ mm_ctlr_cipo <= c_mem_cipo_rst WHEN tse_init = '1' ELSE mm_peri_cipo;
+ tse_ctlr_cipo <= mm_peri_cipo;
+ tse_waitrequest <= tse_ctlr_cipo.waitrequest;
+ tse_wrdata <= tse_ctlr_copi.wrdata(c_word_w-1 DOWNTO 0);
+ tse_rddata <= tse_ctlr_cipo.rddata(c_word_w-1 DOWNTO 0);
+
+ p_state : PROCESS(mm_rst, mm_clk)
+ BEGIN
+ IF mm_rst = '1' THEN
+ state <= s_rd_pcs_rev;
+ next_state <= s_rd_pcs_rev;
+ tse_init <= '1';
+ tse_ctlr_copi <= c_mem_copi_rst;
+ psc_access <= '0';
+ fifo_access <= '0';
+ ELSIF rising_edge(mm_clk) THEN
+ tse_init <= '1';
+ psc_access <= '0';
+ fifo_access <= '0';
+
+ -- Issue MM access
+ CASE state IS
+ -- PSC control
+ WHEN s_rd_pcs_rev =>
+ psc_access <= '1';
+ proc_mem_bus_rd(func_tech_tse_map_pcs_addr(16#22#), tse_ctlr_copi); -- REV --> 0x0901, 0x1304
+ next_state <= s_wr_if_mode;
+
+ WHEN s_wr_if_mode =>
+ psc_access <= '1';
+ proc_mem_bus_wr(func_tech_tse_map_pcs_addr(16#28#), 16#0008#, tse_ctlr_copi); -- IF_MODE <-- Force 1GbE,
+ next_state <= s_rd_control;
+
+ WHEN s_rd_control =>
+ psc_access <= '1';
+ proc_mem_bus_rd(func_tech_tse_map_pcs_addr(16#00#), tse_ctlr_copi); -- CONTROL --> 0x1140
+ next_state <= s_rd_status;
+
+ WHEN s_rd_status =>
+ psc_access <= '1';
+ proc_mem_bus_rd(func_tech_tse_map_pcs_addr(16#02#), tse_ctlr_copi); -- STATUS --> 0x000D
+ next_state <= s_wr_control;
+
+ WHEN s_wr_control =>
+ psc_access <= '1';
+ IF g_sim = FALSE THEN
+ proc_mem_bus_wr(func_tech_tse_map_pcs_addr(16#00#), 16#1140#, tse_ctlr_copi); -- CONTROL <-- Keep auto negotiate enabled (is reset default)
+ ELSE
+ proc_mem_bus_wr(func_tech_tse_map_pcs_addr(16#00#), 16#0140#, tse_ctlr_copi); -- CONTROL <-- In simulation disable auto negotiate
+ END IF;
+ next_state <= s_rd_mac_rev;
+
+ -- MAC control
+ WHEN s_rd_mac_rev =>
+ proc_mem_bus_rd(16#000#, tse_ctlr_copi); -- REV --> CUST_VERSION & 0x0901
+ next_state <= s_wr_promis_en;
+
+ WHEN s_wr_promis_en =>
+ IF c_promis_en = FALSE THEN
+ proc_mem_bus_wr(16#008#, 16#0100004B#, tse_ctlr_copi); -- COMMAND_CONFIG
+ ELSE
+ proc_mem_bus_wr(16#008#, 16#0100005B#, tse_ctlr_copi);
+ END IF;
+ next_state <= s_wr_mac_0;
+
+ WHEN s_wr_mac_0 =>
+ proc_mem_bus_wr(16#00C#, src_mac_0, tse_ctlr_copi); -- MAC_0
+ next_state <= s_wr_mac_1;
+
+ WHEN s_wr_mac_1 =>
+ proc_mem_bus_wr(16#010#, src_mac_1, tse_ctlr_copi); -- MAC_1 <-- SRC_MAC
+ next_state <= s_wr_tx_ipg_len;
+
+ WHEN s_wr_tx_ipg_len =>
+ proc_mem_bus_wr(16#05C#, 16#0000000C#, tse_ctlr_copi); -- TX_IPG_LENGTH <-- interpacket gap = 12
+ next_state <= s_wr_frm_len;
+
+ WHEN s_wr_frm_len =>
+ IF g_jumbo_en = FALSE THEN
+ proc_mem_bus_wr(16#014#, 16#000005EE#, tse_ctlr_copi); -- FRM_LENGTH <-- receive max frame length = 1518
+ ELSE
+ proc_mem_bus_wr(16#014#, 16#0000233A#, tse_ctlr_copi); -- FRM_LENGTH <-- receive max frame length = 9018
+ END IF;
+ next_state <= s_wr_rx_section_empty;
+
+ -- MAC FIFO
+ WHEN s_wr_rx_section_empty =>
+ fifo_access <= '1';
+ proc_mem_bus_wr(16#01C#, c_tech_tse_rx_fifo_depth-16, tse_ctlr_copi); -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ next_state <= s_wr_rx_section_full;
+
+ WHEN s_wr_rx_section_full =>
+ fifo_access <= '1';
+ proc_mem_bus_wr(16#020#, 16, tse_ctlr_copi); -- RX_SECTION_FULL <-- default 16
+ next_state <= s_wr_tx_section_empty;
+
+ WHEN s_wr_tx_section_empty =>
+ fifo_access <= '1';
+ proc_mem_bus_wr(16#024#, c_tech_tse_tx_fifo_depth-16, tse_ctlr_copi); -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ next_state <= s_wr_tx_section_full;
+
+ WHEN s_wr_tx_section_full =>
+ fifo_access <= '1';
+ proc_mem_bus_wr(16#028#, 16, tse_ctlr_copi); -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
+ next_state <= s_wr_rx_almost_empty;
+
+ WHEN s_wr_rx_almost_empty =>
+ fifo_access <= '1';
+ proc_mem_bus_wr(16#02C#, 8, tse_ctlr_copi); -- RX_ALMOST_EMPTY <-- default 8
+ next_state <= s_wr_rx_almost_full;
+
+ WHEN s_wr_rx_almost_full =>
+ fifo_access <= '1';
+ proc_mem_bus_wr(16#030#, 8, tse_ctlr_copi); -- RX_ALMOST_FULL <-- default 8
+ next_state <= s_wr_tx_almost_empty;
+
+ WHEN s_wr_tx_almost_empty =>
+ fifo_access <= '1';
+ proc_mem_bus_wr(16#034#, 8, tse_ctlr_copi); -- TX_ALMOST_EMPTY <-- default 8
+ next_state <= s_wr_tx_almost_full;
+
+ WHEN s_wr_tx_almost_full =>
+ fifo_access <= '1';
+ proc_mem_bus_wr(16#038#, c_tech_tse_tx_ready_latency + 3, tse_ctlr_copi); -- TX_ALMOST_FULL <-- default 3
+ next_state <= s_rd_tx_cmd_stat;
+
+ -- MAC status
+ WHEN s_rd_tx_cmd_stat =>
+ proc_mem_bus_rd(16#0E8#, tse_ctlr_copi); -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
+ next_state <= s_rd_rx_cmd_stat;
+
+ WHEN s_rd_rx_cmd_stat =>
+ proc_mem_bus_rd(16#0EC#, tse_ctlr_copi); -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+ next_state <= s_done;
+
+ WHEN OTHERS => -- s_done
+ tse_init <= '0';
+ END CASE;
+
+ -- Go to next state when MM access was accepted
+ IF state /= next_state AND tse_waitrequest = '0' THEN
+ tse_ctlr_copi.wr <= '0';
+ tse_ctlr_copi.rd <= '0';
+ state <= next_state;
+ END IF;
+
+ END IF;
+ END PROCESS;
+
+END ARCHITECTURE;
diff --git a/libraries/technology/tse/tech_tse_with_setup.vhd b/libraries/technology/tse/tech_tse_with_setup.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..41173fa0a9df5c51c9e9a618d751bfb88fed9e2b
--- /dev/null
+++ b/libraries/technology/tse/tech_tse_with_setup.vhd
@@ -0,0 +1,173 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- AUthor: E. Kooistra
+-- Purpose: Instantiate and setup TSE via MM
+-- Description:
+-- . Based on tech_tse instance in eth.vhd
+-- . Set up TSE in state machnine and then switch to external mm_ctlr, to
+-- allow external monitoring of the TSE.
+
+LIBRARY IEEE, technology_lib, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.tech_tse_pkg.ALL;
+
+ENTITY tech_tse_with_setup IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
+ g_ETH_PHY : STRING := "LVDS"; -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+ g_jumbo_en : BOOLEAN := FALSE;
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
+ g_sim_tx : BOOLEAN := TRUE;
+ g_sim_rx : BOOLEAN := TRUE
+ );
+ PORT (
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC; -- MM
+ eth_clk : IN STD_LOGIC; -- 125 MHz
+ tx_snk_clk : IN STD_LOGIC; -- DP
+ rx_src_clk : IN STD_LOGIC; -- DP
+
+ -- TSE setup
+ src_mac : IN STD_LOGIC_VECTOR(c_48-1 DOWNTO 0);
+ setup_done : OUT STD_LOGIC;
+
+ -- Calibration & reconfig clock
+ cal_rec_clk : IN STD_LOGIC := '0';
+
+ -- Memory Mapped Peripheral
+ mm_ctlr_copi : IN t_mem_copi;
+ mm_ctlr_cipo : OUT t_mem_cipo;
+
+ -- MAC transmit interface
+ -- . ST sink
+ tx_snk_in : IN t_dp_sosi;
+ tx_snk_out : OUT t_dp_siso;
+
+ -- MAC receive interface
+ -- . ST Source
+ rx_src_in : IN t_dp_siso;
+ rx_src_out : OUT t_dp_sosi;
+
+ -- PHY interface
+ eth_txp : OUT STD_LOGIC;
+ eth_rxp : IN STD_LOGIC;
+
+ tse_led : OUT t_tech_tse_led
+ );
+END tech_tse_with_setup;
+
+ARCHITECTURE str OF tech_tse_with_setup IS
+
+ -- Peripheral side
+ SIGNAL mm_peri_copi : t_mem_copi;
+ SIGNAL mm_peri_cipo : t_mem_cipo;
+
+ -- MAC specific
+ SIGNAL tx_mac_in : t_tech_tse_tx_mac;
+ SIGNAL tx_mac_out : t_tech_tse_tx_mac;
+ SIGNAL rx_mac_out : t_tech_tse_rx_mac;
+
+ SIGNAL tx_sosi : t_dp_sosi;
+
+BEGIN
+
+ -- Set up TSE as in unb_osy/unbos_eth.c
+ u_tech_tse_setup : ENTITY work.tech_tse_setup
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_jumbo_en => g_jumbo_en
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- TSE setup
+ src_mac => src_mac,
+ setup_done => setup_done,
+
+ -- Memory Mapped Peripheral
+ -- . Controller side
+ mm_ctlr_copi => mm_ctlr_copi,
+ mm_ctlr_cipo => mm_ctlr_cipo,
+ -- . Peripheral side
+ mm_peri_copi => mm_peri_copi,
+ mm_peri_cipo => mm_peri_cipo
+ );
+
+ -- Force defaults as in eth.vhd
+ tx_sosi <= func_dp_stream_error_set(tx_snk_in, 0); -- force err field (value 0 for OK)
+
+ tx_mac_in.crc_fwd <= '0'; -- when '0' then TSE MAC generates the TX CRC field
+
+ u_tech_tse : ENTITY work.tech_tse
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_ETH_PHY => g_ETH_PHY,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_sim_tx => g_sim_tx,
+ g_sim_rx => g_sim_rx
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ eth_clk => eth_clk,
+ tx_snk_clk => tx_snk_clk,
+ rx_src_clk => rx_src_clk,
+
+ -- Calibration & reconfig clock
+ cal_rec_clk => cal_rec_clk,
+
+ -- Memory Mapped Peripheral
+ mm_sla_in => mm_peri_copi,
+ mm_sla_out => mm_peri_cipo,
+
+ -- MAC transmit interface
+ -- . ST sink
+ tx_snk_in => tx_sosi,
+ tx_snk_out => tx_snk_out,
+ -- . MAC specific
+ tx_mac_in => tx_mac_in,
+ tx_mac_out => tx_mac_out,
+
+ -- MAC receive interface
+ -- . ST Source
+ rx_src_in => rx_src_in,
+ rx_src_out => rx_src_out,
+ -- . MAC specific
+ rx_mac_out => rx_mac_out,
+
+ -- PHY interface
+ eth_txp => eth_txp,
+ eth_rxp => eth_rxp,
+
+ tse_led => tse_led
+ );
+
+END ARCHITECTURE;