From 4bfb1f422812c71a6a1244b18662c933c40bb8cd Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 16 Oct 2015 13:16:38 +0000
Subject: [PATCH] On hardware always generate 1GbE for MM control. In
simulation only use 1GbE for streaming DP data offload (or on load) via 1GbE.
---
.../unb2_board/src/vhdl/ctrl_unb2_board.vhd | 41 ++++++++-----------
1 file changed, 18 insertions(+), 23 deletions(-)
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index e707ccbdad..fb88b3d556 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -265,8 +265,6 @@ ARCHITECTURE str OF ctrl_unb2_board IS
SIGNAL clk50 : STD_LOGIC := '1';
SIGNAL mm_wdi : STD_LOGIC;
- SIGNAL eth1g_st_clk : STD_LOGIC;
- SIGNAL eth1g_st_rst : STD_LOGIC;
SIGNAL mm_pulse_ms : STD_LOGIC;
SIGNAL mm_pulse_s : STD_LOGIC;
@@ -463,7 +461,7 @@ BEGIN
u_unb2_board_node_ctrl : ENTITY work.unb2_board_node_ctrl
GENERIC MAP (
- g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
PORT MAP (
-- MM clock domain reset
@@ -743,27 +741,24 @@ BEGIN
END GENERATE;
-
- gen_same_clk: IF g_udp_offload=TRUE GENERATE
- eth1g_st_clk <= dp_clk_in;
- eth1g_st_rst <= dp_rst_in;
-
- gen_offload_io: FOR i IN 0 TO g_udp_offload_nof_streams-1 GENERATE
- eth1g_udp_tx_sosi_arr(i) <= udp_tx_sosi_arr(i);
- udp_tx_siso_arr(i) <= eth1g_udp_tx_siso_arr(i);
+ wire_udp_offload: FOR i IN 0 TO g_udp_offload_nof_streams-1 GENERATE
+ eth1g_udp_tx_sosi_arr(i) <= udp_tx_sosi_arr(i);
+ udp_tx_siso_arr(i) <= eth1g_udp_tx_siso_arr(i);
- udp_rx_sosi_arr(i) <= eth1g_udp_rx_sosi_arr(i);
- eth1g_udp_rx_siso_arr(i) <= udp_rx_siso_arr(i);
- END GENERATE;
+ udp_rx_sosi_arr(i) <= eth1g_udp_rx_sosi_arr(i);
+ eth1g_udp_rx_siso_arr(i) <= udp_rx_siso_arr(i);
END GENERATE;
- gen_separate_clk: IF g_udp_offload=FALSE GENERATE
- eth1g_st_clk <= i_mm_clk;
- eth1g_st_rst <= eth1g_mm_rst;
+ -- In simulation use file IO for MM control. In simulation only use 1GbE for streaming DP data offload (or on load) via 1GbE.
+ no_eth1g : IF g_sim=TRUE AND g_udp_offload=FALSE GENERATE
+ eth1g_reg_interrupt <= '0';
+ eth1g_tse_miso <= c_mem_miso_rst;
+ eth1g_reg_miso <= c_mem_miso_rst;
+ eth1g_ram_miso <= c_mem_miso_rst;
END GENERATE;
-
-
--- gen_eth: IF g_sim = FALSE GENERATE
+
+ --On hardware always generate 1GbE for MM control. In simulation only use 1GbE for streaming DP data offload (or on load) via 1GbE.
+ gen_eth: IF g_sim=FALSE OR g_udp_offload=TRUE GENERATE
u_eth : ENTITY eth_lib.eth
GENERIC MAP (
g_technology => g_technology,
@@ -775,8 +770,8 @@ BEGIN
mm_rst => eth1g_mm_rst, -- use reset from QSYS
mm_clk => i_mm_clk, -- use mm_clk direct
eth_clk => i_tse_clk, -- 125 MHz clock
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
-- UDP transmit interface
udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
@@ -801,6 +796,6 @@ BEGIN
-- LED interface
tse_led => eth1g_led
);
--- END GENERATE;
+ END GENERATE;
END str;
--
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