diff --git a/libraries/technology/ip_stratixiv/hdllib.cfg b/libraries/technology/ip_stratixiv/hdllib.cfg
index 9aa47f4d2b3edab0207a5cd90f55c63bd6cf9360..5f87c50a5ca555105f67ef4f60a8e78f489034de 100644
--- a/libraries/technology/ip_stratixiv/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/hdllib.cfg
@@ -23,16 +23,16 @@ synth_files =
ip_stratixiv_asmi_parallel.vhd
ip_stratixiv_remote_update.vhd
- ip_stratixiv_gx_reconfig_4.vhd
- ip_stratixiv_gx_reconfig_8.vhd
- ip_stratixiv_gx_reconfig_12.vhd
- ip_stratixiv_gx_reconfig.vhd
+ ip_stratixiv_gxb_reconfig_v91_2.vhd
+ ip_stratixiv_gxb_reconfig_v91_4.vhd
+ ip_stratixiv_gxb_reconfig_v91_8.vhd
+ ip_stratixiv_gxb_reconfig_v91_12.vhd
+ ip_stratixiv_gxb_reconfig_v91.vhd
- ip_stratixiv_gxb_reconfig_2.vhd
- ip_stratixiv_gxb_reconfig_4.vhd
- ip_stratixiv_gxb_reconfig_8.vhd
- ip_stratixiv_gxb_reconfig_12.vhd
- ip_stratixiv_gxb_reconfig.vhd
+ ip_stratixiv_gxb_reconfig_v101_4.vhd
+ ip_stratixiv_gxb_reconfig_v101_8.vhd
+ ip_stratixiv_gxb_reconfig_v101_12.vhd
+ ip_stratixiv_gxb_reconfig_v101.vhd
ip_stratixiv_hssi_gx_32b_generic.vhd
ip_stratixiv_hssi_tx_32b_generic.vhd
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v101.vhd
similarity index 82%
rename from libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v101.vhd
index b840b4f14cbf0f034cb06f17513095eb362e85b1..73570cf50157e1f4b0b297ac7c38fd1f5c21f04d 100644
--- a/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v101.vhd
@@ -20,14 +20,14 @@
-------------------------------------------------------------------------------
--- Purpose : Create one gx_reconfig module for all ALTGX instances.
+-- Purpose : Create one gxb_reconfig module for all ALTGX instances.
LIBRARY ieee, technology_lib;
USE ieee.std_logic_1164.ALL;
USE technology_lib.technology_pkg.ALL;
-ENTITY ip_stratixiv_gx_reconfig IS
+ENTITY ip_stratixiv_gxb_reconfig_v101 IS
GENERIC (
g_nof_gx : NATURAL;
g_fromgxb_bus_w : NATURAL := 17;
@@ -39,14 +39,14 @@ ENTITY ip_stratixiv_gx_reconfig IS
busy : OUT STD_LOGIC;
reconfig_togxb : OUT STD_LOGIC_VECTOR(g_togxb_bus_w-1 DOWNTO 0)
);
-END ip_stratixiv_gx_reconfig;
+END ip_stratixiv_gxb_reconfig_v101;
-ARCHITECTURE str OF ip_stratixiv_gx_reconfig IS
+ARCHITECTURE str OF ip_stratixiv_gxb_reconfig_v101 IS
BEGIN
gen_gx_reconfig_4 : IF g_nof_gx = 4 GENERATE
- u_gx_reconfig_4 : ENTITY work.ip_stratixiv_gx_reconfig_4
+ u_gx_reconfig_4 : ENTITY work.ip_stratixiv_gxb_reconfig_v101_4
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -56,7 +56,7 @@ BEGIN
END GENERATE;
gen_gx_reconfig_8 : IF g_nof_gx = 8 GENERATE
- u_gx_reconfig_8 : ENTITY work.ip_stratixiv_gx_reconfig_8
+ u_gx_reconfig_8 : ENTITY work.ip_stratixiv_gxb_reconfig_v101_8
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -66,7 +66,7 @@ BEGIN
END GENERATE;
gen_gx_reconfig_12 : IF g_nof_gx = 12 GENERATE
- u_gx_reconfig_12 : ENTITY work.ip_stratixiv_gx_reconfig_12
+ u_gx_reconfig_12 : ENTITY work.ip_stratixiv_gxb_reconfig_v101_12
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_12.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v101_12.vhd
similarity index 95%
rename from libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_12.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v101_12.vhd
index 706dc714665b97aacad5a15e13c49bcfd5e8aa0d..214ccc4f9f3d217e4663f5cb6d7cb726721c127e 100644
--- a/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_12.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v101_12.vhd
@@ -4,7 +4,7 @@
-- MODULE: alt2gxb_reconfig
-- ============================================================
--- File Name: ip_stratixiv_gx_reconfig_12.vhd
+-- File Name: ip_stratixiv_gxb_reconfig_v101_12.vhd
-- Megafunction Name(s):
-- alt2gxb_reconfig
--
@@ -47,7 +47,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gx_reconfig_12_alt_dprio_2vj IS
+ ENTITY ip_stratixiv_gxb_reconfig_v101_12_alt_dprio_2vj IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
@@ -65,9 +65,9 @@
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
- END ip_stratixiv_gx_reconfig_12_alt_dprio_2vj;
+ END ip_stratixiv_gxb_reconfig_v101_12_alt_dprio_2vj;
- ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_12_alt_dprio_2vj IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v101_12_alt_dprio_2vj IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1226,7 +1226,7 @@
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state223w226w227w(0) OR (wire_pre_amble_cmpr_w_lg_agb224w(0) AND wire_dprio_w_lg_wr_addr_state223w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state337w338w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb224w336w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state402w403w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb224w401w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
- END RTL; --ip_stratixiv_gx_reconfig_12_alt_dprio_2vj
+ END RTL; --ip_stratixiv_gxb_reconfig_v101_12_alt_dprio_2vj
--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=3 LPM_WIDTH=1 LPM_WIDTHS=2 data result sel
@@ -1236,16 +1236,16 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gx_reconfig_12_mux_66a IS
+ ENTITY ip_stratixiv_gxb_reconfig_v101_12_mux_66a IS
PORT
(
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0')
);
- END ip_stratixiv_gx_reconfig_12_mux_66a;
+ END ip_stratixiv_gxb_reconfig_v101_12_mux_66a;
- ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_12_mux_66a IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v101_12_mux_66a IS
SIGNAL wire_dprioout_mux_w_lg_w_data_range486w487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprioout_mux_w_lg_w_sel_range484w485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -1267,7 +1267,7 @@
wire_dprioout_mux_w_data_range486w(0) <= data(0);
wire_dprioout_mux_w_sel_range484w(0) <= sel(0);
- END RTL; --ip_stratixiv_gx_reconfig_12_mux_66a
+ END RTL; --ip_stratixiv_gxb_reconfig_v101_12_mux_66a
LIBRARY altera_mf;
USE altera_mf.all;
@@ -1276,7 +1276,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gx_reconfig_12_alt2gxb_reconfig_shm IS
+ ENTITY ip_stratixiv_gxb_reconfig_v101_12_alt2gxb_reconfig_shm IS
PORT
(
busy : OUT STD_LOGIC;
@@ -1284,9 +1284,9 @@
reconfig_fromgxb : IN STD_LOGIC_VECTOR (50 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
- END ip_stratixiv_gx_reconfig_12_alt2gxb_reconfig_shm;
+ END ip_stratixiv_gxb_reconfig_v101_12_alt2gxb_reconfig_shm;
- ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_12_alt2gxb_reconfig_shm IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v101_12_alt2gxb_reconfig_shm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1367,7 +1367,7 @@
transceiver_init : IN STD_LOGIC
);
END COMPONENT;
- COMPONENT ip_stratixiv_gx_reconfig_12_alt_dprio_2vj
+ COMPONENT ip_stratixiv_gxb_reconfig_v101_12_alt_dprio_2vj
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -1386,7 +1386,7 @@
wren_data : IN STD_LOGIC := '0'
);
END COMPONENT;
- COMPONENT ip_stratixiv_gx_reconfig_12_mux_66a
+ COMPONENT ip_stratixiv_gxb_reconfig_v101_12_mux_66a
PORT
(
data : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
@@ -1445,7 +1445,7 @@
wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
- dprio : ip_stratixiv_gx_reconfig_12_alt_dprio_2vj
+ dprio : ip_stratixiv_gxb_reconfig_v101_12_alt_dprio_2vj
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
@@ -1468,21 +1468,21 @@
ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
END IF;
END PROCESS;
- dprioout_mux : ip_stratixiv_gx_reconfig_12_mux_66a
+ dprioout_mux : ip_stratixiv_gxb_reconfig_v101_12_mux_66a
PORT MAP (
data => cal_dprioout_wire,
result => wire_dprioout_mux_result,
sel => quad_address(1 DOWNTO 0)
);
- END RTL; --ip_stratixiv_gx_reconfig_12_alt2gxb_reconfig_shm
+ END RTL; --ip_stratixiv_gxb_reconfig_v101_12_alt2gxb_reconfig_shm
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-ENTITY ip_stratixiv_gx_reconfig_12 IS
+ENTITY ip_stratixiv_gxb_reconfig_v101_12 IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
@@ -1490,10 +1490,10 @@ ENTITY ip_stratixiv_gx_reconfig_12 IS
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
-END ip_stratixiv_gx_reconfig_12;
+END ip_stratixiv_gxb_reconfig_v101_12;
-ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_12 IS
+ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v101_12 IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
@@ -1506,7 +1506,7 @@ ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_12 IS
- COMPONENT ip_stratixiv_gx_reconfig_12_alt2gxb_reconfig_shm
+ COMPONENT ip_stratixiv_gxb_reconfig_v101_12_alt2gxb_reconfig_shm
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
@@ -1519,7 +1519,7 @@ BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
- ip_stratixiv_gx_reconfig_12_alt2gxb_reconfig_shm_component : ip_stratixiv_gx_reconfig_12_alt2gxb_reconfig_shm
+ ip_stratixiv_gxb_reconfig_v101_12_alt2gxb_reconfig_shm_component : ip_stratixiv_gxb_reconfig_v101_12_alt2gxb_reconfig_shm
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -1556,10 +1556,10 @@ END RTL;
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 51 0 reconfig_fromgxb 0 0 51 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_12.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_12.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_12.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_12.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_12_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_12.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_12.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_12.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_12.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_12_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_4.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v101_4.vhd
similarity index 95%
rename from libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_4.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v101_4.vhd
index 7bb2d99f9eaa736813b596654a564a30941f4bd9..93f33e77eed58b0d605b298f0bfe322148f30bd7 100644
--- a/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_4.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v101_4.vhd
@@ -4,7 +4,7 @@
-- MODULE: alt2gxb_reconfig
-- ============================================================
--- File Name: ip_stratixiv_gx_reconfig_4.vhd
+-- File Name: ip_stratixiv_gxb_reconfig_v101_4.vhd
-- Megafunction Name(s):
-- alt2gxb_reconfig
--
@@ -47,7 +47,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gx_reconfig_4_alt_dprio_2vj IS
+ ENTITY ip_stratixiv_gxb_reconfig_v101_4_alt_dprio_2vj IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
@@ -65,9 +65,9 @@
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
- END ip_stratixiv_gx_reconfig_4_alt_dprio_2vj;
+ END ip_stratixiv_gxb_reconfig_v101_4_alt_dprio_2vj;
- ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_4_alt_dprio_2vj IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v101_4_alt_dprio_2vj IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1226,7 +1226,7 @@
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state214w217w218w(0) OR (wire_pre_amble_cmpr_w_lg_agb215w(0) AND wire_dprio_w_lg_wr_addr_state214w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state328w329w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb215w327w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state393w394w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb215w392w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
- END RTL; --ip_stratixiv_gx_reconfig_4_alt_dprio_2vj
+ END RTL; --ip_stratixiv_gxb_reconfig_v101_4_alt_dprio_2vj
LIBRARY altera_mf;
USE altera_mf.all;
@@ -1235,7 +1235,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gx_reconfig_4_alt2gxb_reconfig_dgm IS
+ ENTITY ip_stratixiv_gxb_reconfig_v101_4_alt2gxb_reconfig_dgm IS
PORT
(
busy : OUT STD_LOGIC;
@@ -1243,9 +1243,9 @@
reconfig_fromgxb : IN STD_LOGIC_VECTOR (16 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
- END ip_stratixiv_gx_reconfig_4_alt2gxb_reconfig_dgm;
+ END ip_stratixiv_gxb_reconfig_v101_4_alt2gxb_reconfig_dgm;
- ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_4_alt2gxb_reconfig_dgm IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v101_4_alt2gxb_reconfig_dgm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1325,7 +1325,7 @@
transceiver_init : IN STD_LOGIC
);
END COMPONENT;
- COMPONENT ip_stratixiv_gx_reconfig_4_alt_dprio_2vj
+ COMPONENT ip_stratixiv_gxb_reconfig_v101_4_alt_dprio_2vj
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -1395,7 +1395,7 @@
wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
- dprio : ip_stratixiv_gx_reconfig_4_alt_dprio_2vj
+ dprio : ip_stratixiv_gxb_reconfig_v101_4_alt_dprio_2vj
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
@@ -1419,14 +1419,14 @@
END IF;
END PROCESS;
- END RTL; --ip_stratixiv_gx_reconfig_4_alt2gxb_reconfig_dgm
+ END RTL; --ip_stratixiv_gxb_reconfig_v101_4_alt2gxb_reconfig_dgm
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-ENTITY ip_stratixiv_gx_reconfig_4 IS
+ENTITY ip_stratixiv_gxb_reconfig_v101_4 IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
@@ -1434,10 +1434,10 @@ ENTITY ip_stratixiv_gx_reconfig_4 IS
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
-END ip_stratixiv_gx_reconfig_4;
+END ip_stratixiv_gxb_reconfig_v101_4;
-ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_4 IS
+ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v101_4 IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
@@ -1450,7 +1450,7 @@ ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_4 IS
- COMPONENT ip_stratixiv_gx_reconfig_4_alt2gxb_reconfig_dgm
+ COMPONENT ip_stratixiv_gxb_reconfig_v101_4_alt2gxb_reconfig_dgm
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
@@ -1463,7 +1463,7 @@ BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
- ip_stratixiv_gx_reconfig_4_alt2gxb_reconfig_dgm_component : ip_stratixiv_gx_reconfig_4_alt2gxb_reconfig_dgm
+ ip_stratixiv_gxb_reconfig_v101_4_alt2gxb_reconfig_dgm_component : ip_stratixiv_gxb_reconfig_v101_4_alt2gxb_reconfig_dgm
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -1500,10 +1500,10 @@ END RTL;
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 17 0 reconfig_fromgxb 0 0 17 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_4.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_4.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_4.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_4.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_4_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_4.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_4.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_4_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_8.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v101_8.vhd
similarity index 95%
rename from libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_8.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v101_8.vhd
index be0e6f442359f7bb951c1d2519c366bdc1486a86..4014c33a01baa816c165b05a3a8bf633a57b02e0 100644
--- a/libraries/technology/ip_stratixiv/ip_stratixiv_gx_reconfig_8.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v101_8.vhd
@@ -4,7 +4,7 @@
-- MODULE: alt2gxb_reconfig
-- ============================================================
--- File Name: ip_stratixiv_gx_reconfig_8.vhd
+-- File Name: ip_stratixiv_gxb_reconfig_v101_8.vhd
-- Megafunction Name(s):
-- alt2gxb_reconfig
--
@@ -47,7 +47,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gx_reconfig_8_alt_dprio_2vj IS
+ ENTITY ip_stratixiv_gxb_reconfig_v101_8_alt_dprio_2vj IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
@@ -65,9 +65,9 @@
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
- END ip_stratixiv_gx_reconfig_8_alt_dprio_2vj;
+ END ip_stratixiv_gxb_reconfig_v101_8_alt_dprio_2vj;
- ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_8_alt_dprio_2vj IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v101_8_alt_dprio_2vj IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1226,7 +1226,7 @@
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state219w222w223w(0) OR (wire_pre_amble_cmpr_w_lg_agb220w(0) AND wire_dprio_w_lg_wr_addr_state219w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state333w334w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb220w332w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state398w399w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb220w397w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
- END RTL; --ip_stratixiv_gx_reconfig_8_alt_dprio_2vj
+ END RTL; --ip_stratixiv_gxb_reconfig_v101_8_alt_dprio_2vj
--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=2 LPM_WIDTH=1 LPM_WIDTHS=1 data result sel
@@ -1236,16 +1236,16 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gx_reconfig_8_mux_46a IS
+ ENTITY ip_stratixiv_gxb_reconfig_v101_8_mux_46a IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0')
);
- END ip_stratixiv_gx_reconfig_8_mux_46a;
+ END ip_stratixiv_gxb_reconfig_v101_8_mux_46a;
- ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_8_mux_46a IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v101_8_mux_46a IS
SIGNAL wire_l1_w0_n0_mux_dataout : STD_LOGIC;
SIGNAL data_wire : STD_LOGIC_VECTOR (1 DOWNTO 0);
@@ -1259,7 +1259,7 @@
sel_wire(0) <= ( sel(0));
wire_l1_w0_n0_mux_dataout <= data_wire(1) WHEN sel_wire(0) = '1' ELSE data_wire(0);
- END RTL; --ip_stratixiv_gx_reconfig_8_mux_46a
+ END RTL; --ip_stratixiv_gxb_reconfig_v101_8_mux_46a
LIBRARY altera_mf;
USE altera_mf.all;
@@ -1268,7 +1268,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gx_reconfig_8_alt2gxb_reconfig_hgm IS
+ ENTITY ip_stratixiv_gxb_reconfig_v101_8_alt2gxb_reconfig_hgm IS
PORT
(
busy : OUT STD_LOGIC;
@@ -1276,9 +1276,9 @@
reconfig_fromgxb : IN STD_LOGIC_VECTOR (33 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
- END ip_stratixiv_gx_reconfig_8_alt2gxb_reconfig_hgm;
+ END ip_stratixiv_gxb_reconfig_v101_8_alt2gxb_reconfig_hgm;
- ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_8_alt2gxb_reconfig_hgm IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v101_8_alt2gxb_reconfig_hgm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1359,7 +1359,7 @@
transceiver_init : IN STD_LOGIC
);
END COMPONENT;
- COMPONENT ip_stratixiv_gx_reconfig_8_alt_dprio_2vj
+ COMPONENT ip_stratixiv_gxb_reconfig_v101_8_alt_dprio_2vj
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -1378,7 +1378,7 @@
wren_data : IN STD_LOGIC := '0'
);
END COMPONENT;
- COMPONENT ip_stratixiv_gx_reconfig_8_mux_46a
+ COMPONENT ip_stratixiv_gxb_reconfig_v101_8_mux_46a
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
@@ -1437,7 +1437,7 @@
wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
- dprio : ip_stratixiv_gx_reconfig_8_alt_dprio_2vj
+ dprio : ip_stratixiv_gxb_reconfig_v101_8_alt_dprio_2vj
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
@@ -1460,21 +1460,21 @@
ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
END IF;
END PROCESS;
- dprioout_mux : ip_stratixiv_gx_reconfig_8_mux_46a
+ dprioout_mux : ip_stratixiv_gxb_reconfig_v101_8_mux_46a
PORT MAP (
data => cal_dprioout_wire,
result => wire_dprioout_mux_result,
sel => quad_address(0 DOWNTO 0)
);
- END RTL; --ip_stratixiv_gx_reconfig_8_alt2gxb_reconfig_hgm
+ END RTL; --ip_stratixiv_gxb_reconfig_v101_8_alt2gxb_reconfig_hgm
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-ENTITY ip_stratixiv_gx_reconfig_8 IS
+ENTITY ip_stratixiv_gxb_reconfig_v101_8 IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
@@ -1482,10 +1482,10 @@ ENTITY ip_stratixiv_gx_reconfig_8 IS
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
-END ip_stratixiv_gx_reconfig_8;
+END ip_stratixiv_gxb_reconfig_v101_8;
-ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_8 IS
+ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v101_8 IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
@@ -1498,7 +1498,7 @@ ARCHITECTURE RTL OF ip_stratixiv_gx_reconfig_8 IS
- COMPONENT ip_stratixiv_gx_reconfig_8_alt2gxb_reconfig_hgm
+ COMPONENT ip_stratixiv_gxb_reconfig_v101_8_alt2gxb_reconfig_hgm
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
@@ -1511,7 +1511,7 @@ BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
- ip_stratixiv_gx_reconfig_8_alt2gxb_reconfig_hgm_component : ip_stratixiv_gx_reconfig_8_alt2gxb_reconfig_hgm
+ ip_stratixiv_gxb_reconfig_v101_8_alt2gxb_reconfig_hgm_component : ip_stratixiv_gxb_reconfig_v101_8_alt2gxb_reconfig_hgm
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -1548,10 +1548,10 @@ END RTL;
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 34 0 reconfig_fromgxb 0 0 34 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_8.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_8.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_8.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_8.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gx_reconfig_8_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_8.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_8.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_8.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_8.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v101_8_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91.vhd
similarity index 81%
rename from libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91.vhd
index 7a32d00ad8f56d04a2076723bee8cb7692d6a019..fa90e94e92e026732f3aacaf5d3aa4efc07e4225 100644
--- a/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91.vhd
@@ -20,13 +20,12 @@
-------------------------------------------------------------------------------
--- Purpose : Create one reconfig module for all ALTGX instances.
-
+-- Purpose : Create one gxb_reconfig module for all ALTGX instances.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-ENTITY ip_stratixiv_gxb_reconfig IS
+ENTITY ip_stratixiv_gxb_reconfig_v91 IS
GENERIC (
g_nof_gx : NATURAL;
g_fromgxb_bus_w : NATURAL := 17;
@@ -38,14 +37,14 @@ ENTITY ip_stratixiv_gxb_reconfig IS
busy : OUT STD_LOGIC;
reconfig_togxb : OUT STD_LOGIC_VECTOR(g_togxb_bus_w-1 DOWNTO 0)
);
-END ip_stratixiv_gxb_reconfig;
+END ip_stratixiv_gxb_reconfig_v91;
-ARCHITECTURE str OF ip_stratixiv_gxb_reconfig IS
+ARCHITECTURE str OF ip_stratixiv_gxb_reconfig_v91 IS
BEGIN
gen_gxb_reconfig_2 : IF g_nof_gx = 2 GENERATE
- u_gxb_reconfig_2 : ENTITY work.ip_stratixiv_gxb_reconfig_2
+ u_gxb_reconfig_2 : ENTITY work.ip_stratixiv_gxb_reconfig_v91_2
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -55,7 +54,7 @@ BEGIN
END GENERATE;
gen_gxb_reconfig_4 : IF g_nof_gx = 4 GENERATE
- u_gxb_reconfig_4 : ENTITY work.ip_stratixiv_gxb_reconfig_4
+ u_gxb_reconfig_4 : ENTITY work.ip_stratixiv_gxb_reconfig_v91_4
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -65,7 +64,7 @@ BEGIN
END GENERATE;
gen_gxb_reconfig_8 : IF g_nof_gx = 8 GENERATE
- u_gxb_reconfig_8 : ENTITY work.ip_stratixiv_gxb_reconfig_8
+ u_gxb_reconfig_8 : ENTITY work.ip_stratixiv_gxb_reconfig_v91_8
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -75,7 +74,7 @@ BEGIN
END GENERATE;
gen_gxb_reconfig_12 : IF g_nof_gx = 12 GENERATE
- u_gxb_reconfig_12 : ENTITY work.ip_stratixiv_gxb_reconfig_12
+ u_gxb_reconfig_12 : ENTITY work.ip_stratixiv_gxb_reconfig_v91_12
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_12.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91_12.vhd
similarity index 95%
rename from libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_12.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91_12.vhd
index 52c32fa048888d727b78d282f9d81c8fa57052ac..3bcec7bbd556e35bd6a2e0645696e72b46684ca7 100644
--- a/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_12.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91_12.vhd
@@ -4,7 +4,7 @@
-- MODULE: alt2gxb_reconfig
-- ============================================================
--- File Name: ip_stratixiv_gxb_reconfig_12.vhd
+-- File Name: ip_stratixiv_gxb_reconfig_v91_12.vhd
-- Megafunction Name(s):
-- alt2gxb_reconfig
--
@@ -47,7 +47,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_12_alt_dprio_2vj IS
+ ENTITY ip_stratixiv_gxb_reconfig_v91_12_alt_dprio_2vj IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
@@ -65,9 +65,9 @@
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
- END ip_stratixiv_gxb_reconfig_12_alt_dprio_2vj;
+ END ip_stratixiv_gxb_reconfig_v91_12_alt_dprio_2vj;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_12_alt_dprio_2vj IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_12_alt_dprio_2vj IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1226,7 +1226,7 @@
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state259w262w263w(0) OR (wire_pre_amble_cmpr_w_lg_agb260w(0) AND wire_dprio_w_lg_wr_addr_state259w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state373w374w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb260w372w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state438w439w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb260w437w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
- END RTL; --ip_stratixiv_gxb_reconfig_12_alt_dprio_2vj
+ END RTL; --ip_stratixiv_gxb_reconfig_v91_12_alt_dprio_2vj
--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=12 LPM_WIDTH=1 LPM_WIDTHS=4 data result sel
@@ -1236,16 +1236,16 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_12_mux_o7a IS
+ ENTITY ip_stratixiv_gxb_reconfig_v91_12_mux_o7a IS
PORT
(
data : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0')
);
- END ip_stratixiv_gxb_reconfig_12_mux_o7a;
+ END ip_stratixiv_gxb_reconfig_v91_12_mux_o7a;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_12_mux_o7a IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_12_mux_o7a IS
SIGNAL wire_l1_w0_n0_mux_dataout : STD_LOGIC;
SIGNAL wire_l1_w0_n1_mux_dataout : STD_LOGIC;
@@ -1287,7 +1287,7 @@
wire_l3_w0_n1_mux_dataout <= data_wire(27) WHEN sel_wire(10) = '1' ELSE data_wire(26);
wire_l4_w0_n0_mux_dataout <= data_wire(29) WHEN sel_wire(15) = '1' ELSE data_wire(28);
- END RTL; --ip_stratixiv_gxb_reconfig_12_mux_o7a
+ END RTL; --ip_stratixiv_gxb_reconfig_v91_12_mux_o7a
LIBRARY altera_mf;
USE altera_mf.all;
@@ -1296,7 +1296,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_12_alt2gxb_reconfig_5lm IS
+ ENTITY ip_stratixiv_gxb_reconfig_v91_12_alt2gxb_reconfig_5lm IS
PORT
(
busy : OUT STD_LOGIC;
@@ -1304,9 +1304,9 @@
reconfig_fromgxb : IN STD_LOGIC_VECTOR (203 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
- END ip_stratixiv_gxb_reconfig_12_alt2gxb_reconfig_5lm;
+ END ip_stratixiv_gxb_reconfig_v91_12_alt2gxb_reconfig_5lm;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_12_alt2gxb_reconfig_5lm IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_12_alt2gxb_reconfig_5lm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1386,7 +1386,7 @@
transceiver_init : IN STD_LOGIC
);
END COMPONENT;
- COMPONENT ip_stratixiv_gxb_reconfig_12_alt_dprio_2vj
+ COMPONENT ip_stratixiv_gxb_reconfig_v91_12_alt_dprio_2vj
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -1405,7 +1405,7 @@
wren_data : IN STD_LOGIC := '0'
);
END COMPONENT;
- COMPONENT ip_stratixiv_gxb_reconfig_12_mux_o7a
+ COMPONENT ip_stratixiv_gxb_reconfig_v91_12_mux_o7a
PORT
(
data : IN STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
@@ -1462,7 +1462,7 @@
wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
- dprio : ip_stratixiv_gxb_reconfig_12_alt_dprio_2vj
+ dprio : ip_stratixiv_gxb_reconfig_v91_12_alt_dprio_2vj
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
@@ -1485,21 +1485,21 @@
ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
END IF;
END PROCESS;
- dprioout_mux : ip_stratixiv_gxb_reconfig_12_mux_o7a
+ dprioout_mux : ip_stratixiv_gxb_reconfig_v91_12_mux_o7a
PORT MAP (
data => cal_dprioout_wire,
result => wire_dprioout_mux_result,
sel => quad_address(3 DOWNTO 0)
);
- END RTL; --ip_stratixiv_gxb_reconfig_12_alt2gxb_reconfig_5lm
+ END RTL; --ip_stratixiv_gxb_reconfig_v91_12_alt2gxb_reconfig_5lm
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-ENTITY ip_stratixiv_gxb_reconfig_12 IS
+ENTITY ip_stratixiv_gxb_reconfig_v91_12 IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
@@ -1507,10 +1507,10 @@ ENTITY ip_stratixiv_gxb_reconfig_12 IS
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
-END ip_stratixiv_gxb_reconfig_12;
+END ip_stratixiv_gxb_reconfig_v91_12;
-ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_12 IS
+ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_12 IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
@@ -1523,7 +1523,7 @@ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_12 IS
- COMPONENT ip_stratixiv_gxb_reconfig_12_alt2gxb_reconfig_5lm
+ COMPONENT ip_stratixiv_gxb_reconfig_v91_12_alt2gxb_reconfig_5lm
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
@@ -1536,7 +1536,7 @@ BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
- ip_stratixiv_gxb_reconfig_12_alt2gxb_reconfig_5lm_component : ip_stratixiv_gxb_reconfig_12_alt2gxb_reconfig_5lm
+ ip_stratixiv_gxb_reconfig_v91_12_alt2gxb_reconfig_5lm_component : ip_stratixiv_gxb_reconfig_v91_12_alt2gxb_reconfig_5lm
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -1573,10 +1573,10 @@ END RTL;
-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_12.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_12.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_12.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_12.bsf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_12_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_12.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_12.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_12.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_12.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_12_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_2.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91_2.vhd
similarity index 95%
rename from libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_2.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91_2.vhd
index 7c402d026da23ba3c998734b05746cbb5baa01bb..6d66bea88017dad5fb95cff46e17fd2c88debe29 100644
--- a/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_2.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91_2.vhd
@@ -4,7 +4,7 @@
-- MODULE: alt2gxb_reconfig
-- ============================================================
--- File Name: ip_stratixiv_gxb_reconfig_2.vhd
+-- File Name: ip_stratixiv_gxb_reconfig_v91_2.vhd
-- Megafunction Name(s):
-- alt2gxb_reconfig
--
@@ -47,7 +47,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_2_alt_dprio_2vj IS
+ ENTITY ip_stratixiv_gxb_reconfig_v91_2_alt_dprio_2vj IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
@@ -65,9 +65,9 @@
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
- END ip_stratixiv_gxb_reconfig_2_alt_dprio_2vj;
+ END ip_stratixiv_gxb_reconfig_v91_2_alt_dprio_2vj;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_2_alt_dprio_2vj IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_2_alt_dprio_2vj IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1226,7 +1226,7 @@
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state219w222w223w(0) OR (wire_pre_amble_cmpr_w_lg_agb220w(0) AND wire_dprio_w_lg_wr_addr_state219w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state333w334w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb220w332w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state398w399w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb220w397w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
- END RTL; --ip_stratixiv_gxb_reconfig_2_alt_dprio_2vj
+ END RTL; --ip_stratixiv_gxb_reconfig_v91_2_alt_dprio_2vj
--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=2 LPM_WIDTH=1 LPM_WIDTHS=1 data result sel
@@ -1236,16 +1236,16 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_2_mux_46a IS
+ ENTITY ip_stratixiv_gxb_reconfig_v91_2_mux_46a IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0')
);
- END ip_stratixiv_gxb_reconfig_2_mux_46a;
+ END ip_stratixiv_gxb_reconfig_v91_2_mux_46a;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_2_mux_46a IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_2_mux_46a IS
SIGNAL wire_l1_w0_n0_mux_dataout : STD_LOGIC;
SIGNAL data_wire : STD_LOGIC_VECTOR (1 DOWNTO 0);
@@ -1259,7 +1259,7 @@
sel_wire(0) <= ( sel(0));
wire_l1_w0_n0_mux_dataout <= data_wire(1) WHEN sel_wire(0) = '1' ELSE data_wire(0);
- END RTL; --ip_stratixiv_gxb_reconfig_2_mux_46a
+ END RTL; --ip_stratixiv_gxb_reconfig_v91_2_mux_46a
LIBRARY altera_mf;
USE altera_mf.all;
@@ -1268,7 +1268,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_2_alt2gxb_reconfig_hgm IS
+ ENTITY ip_stratixiv_gxb_reconfig_v91_2_alt2gxb_reconfig_hgm IS
PORT
(
busy : OUT STD_LOGIC;
@@ -1276,9 +1276,9 @@
reconfig_fromgxb : IN STD_LOGIC_VECTOR (33 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
- END ip_stratixiv_gxb_reconfig_2_alt2gxb_reconfig_hgm;
+ END ip_stratixiv_gxb_reconfig_v91_2_alt2gxb_reconfig_hgm;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_2_alt2gxb_reconfig_hgm IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_2_alt2gxb_reconfig_hgm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1358,7 +1358,7 @@
transceiver_init : IN STD_LOGIC
);
END COMPONENT;
- COMPONENT ip_stratixiv_gxb_reconfig_2_alt_dprio_2vj
+ COMPONENT ip_stratixiv_gxb_reconfig_v91_2_alt_dprio_2vj
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -1377,7 +1377,7 @@
wren_data : IN STD_LOGIC := '0'
);
END COMPONENT;
- COMPONENT ip_stratixiv_gxb_reconfig_2_mux_46a
+ COMPONENT ip_stratixiv_gxb_reconfig_v91_2_mux_46a
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
@@ -1434,7 +1434,7 @@
wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
- dprio : ip_stratixiv_gxb_reconfig_2_alt_dprio_2vj
+ dprio : ip_stratixiv_gxb_reconfig_v91_2_alt_dprio_2vj
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
@@ -1457,21 +1457,21 @@
ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
END IF;
END PROCESS;
- dprioout_mux : ip_stratixiv_gxb_reconfig_2_mux_46a
+ dprioout_mux : ip_stratixiv_gxb_reconfig_v91_2_mux_46a
PORT MAP (
data => cal_dprioout_wire,
result => wire_dprioout_mux_result,
sel => quad_address(0 DOWNTO 0)
);
- END RTL; --ip_stratixiv_gxb_reconfig_2_alt2gxb_reconfig_hgm
+ END RTL; --ip_stratixiv_gxb_reconfig_v91_2_alt2gxb_reconfig_hgm
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-ENTITY ip_stratixiv_gxb_reconfig_2 IS
+ENTITY ip_stratixiv_gxb_reconfig_v91_2 IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
@@ -1479,10 +1479,10 @@ ENTITY ip_stratixiv_gxb_reconfig_2 IS
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
-END ip_stratixiv_gxb_reconfig_2;
+END ip_stratixiv_gxb_reconfig_v91_2;
-ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_2 IS
+ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_2 IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
@@ -1495,7 +1495,7 @@ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_2 IS
- COMPONENT ip_stratixiv_gxb_reconfig_2_alt2gxb_reconfig_hgm
+ COMPONENT ip_stratixiv_gxb_reconfig_v91_2_alt2gxb_reconfig_hgm
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
@@ -1508,7 +1508,7 @@ BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
- ip_stratixiv_gxb_reconfig_2_alt2gxb_reconfig_hgm_component : ip_stratixiv_gxb_reconfig_2_alt2gxb_reconfig_hgm
+ ip_stratixiv_gxb_reconfig_v91_2_alt2gxb_reconfig_hgm_component : ip_stratixiv_gxb_reconfig_v91_2_alt2gxb_reconfig_hgm
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -1545,10 +1545,10 @@ END RTL;
-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_2.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_2.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_2.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_2.bsf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_2_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_2.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_2.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_4.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91_4.vhd
similarity index 97%
rename from libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_4.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91_4.vhd
index 549dd580d66a5305c94404c0446ea710873888b7..79a2eaabe81a0ecddf3f3721a6cb61be07cd0336 100644
--- a/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_4.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91_4.vhd
@@ -4,7 +4,7 @@
-- MODULE: alt2gxb_reconfig
-- ============================================================
--- File Name: ip_stratixiv_gxb_reconfig_4.vhd
+-- File Name: ip_stratixiv_gxb_reconfig_v91_4.vhd
-- Megafunction Name(s):
-- alt2gxb_reconfig
--
@@ -47,7 +47,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_4_alt_dprio_2vj IS
+ ENTITY ip_stratixiv_gxb_reconfig_v91_4_alt_dprio_2vj IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
@@ -65,9 +65,9 @@
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
- END ip_stratixiv_gxb_reconfig_4_alt_dprio_2vj;
+ END ip_stratixiv_gxb_reconfig_v91_4_alt_dprio_2vj;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_4_alt_dprio_2vj IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_4_alt_dprio_2vj IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1226,7 +1226,7 @@
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state226w230w231w(0) OR (wire_pre_amble_cmpr_w_lg_agb227w(0) AND wire_dprio_w_lg_wr_addr_state226w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state341w342w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb227w339w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state406w407w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb227w404w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
- END RTL; --ip_stratixiv_gxb_reconfig_4_alt_dprio_2vj
+ END RTL; --ip_stratixiv_gxb_reconfig_v91_4_alt_dprio_2vj
--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=4 LPM_WIDTH=1 LPM_WIDTHS=2 data result sel
@@ -1236,16 +1236,16 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_4_mux_76a IS
+ ENTITY ip_stratixiv_gxb_reconfig_v91_4_mux_76a IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0')
);
- END ip_stratixiv_gxb_reconfig_4_mux_76a;
+ END ip_stratixiv_gxb_reconfig_v91_4_mux_76a;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_4_mux_76a IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_4_mux_76a IS
SIGNAL wire_l1_w0_n0_mux_dataout : STD_LOGIC;
SIGNAL wire_l1_w0_n1_mux_dataout : STD_LOGIC;
@@ -1263,7 +1263,7 @@
wire_l1_w0_n1_mux_dataout <= data_wire(3) WHEN sel_wire(0) = '1' ELSE data_wire(2);
wire_l2_w0_n0_mux_dataout <= data_wire(5) WHEN sel_wire(3) = '1' ELSE data_wire(4);
- END RTL; --ip_stratixiv_gxb_reconfig_4_mux_76a
+ END RTL; --ip_stratixiv_gxb_reconfig_v91_4_mux_76a
LIBRARY altera_mf;
USE altera_mf.all;
@@ -1272,7 +1272,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_4_alt2gxb_reconfig_9im IS
+ ENTITY ip_stratixiv_gxb_reconfig_v91_4_alt2gxb_reconfig_9im IS
PORT
(
busy : OUT STD_LOGIC;
@@ -1280,9 +1280,9 @@
reconfig_fromgxb : IN STD_LOGIC_VECTOR (67 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
- END ip_stratixiv_gxb_reconfig_4_alt2gxb_reconfig_9im;
+ END ip_stratixiv_gxb_reconfig_v91_4_alt2gxb_reconfig_9im;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_4_alt2gxb_reconfig_9im IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_4_alt2gxb_reconfig_9im IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1363,7 +1363,7 @@
transceiver_init : IN STD_LOGIC
);
END COMPONENT;
- COMPONENT ip_stratixiv_gxb_reconfig_4_alt_dprio_2vj
+ COMPONENT ip_stratixiv_gxb_reconfig_v91_4_alt_dprio_2vj
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -1382,7 +1382,7 @@
wren_data : IN STD_LOGIC := '0'
);
END COMPONENT;
- COMPONENT ip_stratixiv_gxb_reconfig_4_mux_76a
+ COMPONENT ip_stratixiv_gxb_reconfig_v91_4_mux_76a
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
@@ -1441,7 +1441,7 @@
wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
- dprio : ip_stratixiv_gxb_reconfig_4_alt_dprio_2vj
+ dprio : ip_stratixiv_gxb_reconfig_v91_4_alt_dprio_2vj
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
@@ -1464,21 +1464,21 @@
ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
END IF;
END PROCESS;
- dprioout_mux : ip_stratixiv_gxb_reconfig_4_mux_76a
+ dprioout_mux : ip_stratixiv_gxb_reconfig_v91_4_mux_76a
PORT MAP (
data => cal_dprioout_wire,
result => wire_dprioout_mux_result,
sel => quad_address(1 DOWNTO 0)
);
- END RTL; --ip_stratixiv_gxb_reconfig_4_alt2gxb_reconfig_9im
+ END RTL; --ip_stratixiv_gxb_reconfig_v91_4_alt2gxb_reconfig_9im
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-ENTITY ip_stratixiv_gxb_reconfig_4 IS
+ENTITY ip_stratixiv_gxb_reconfig_v91_4 IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
@@ -1486,10 +1486,10 @@ ENTITY ip_stratixiv_gxb_reconfig_4 IS
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
-END ip_stratixiv_gxb_reconfig_4;
+END ip_stratixiv_gxb_reconfig_v91_4;
-ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_4 IS
+ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_4 IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
@@ -1502,7 +1502,7 @@ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_4 IS
- COMPONENT ip_stratixiv_gxb_reconfig_4_alt2gxb_reconfig_9im
+ COMPONENT ip_stratixiv_gxb_reconfig_v91_4_alt2gxb_reconfig_9im
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
@@ -1515,7 +1515,7 @@ BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
- ip_stratixiv_gxb_reconfig_4_alt2gxb_reconfig_9im_component : ip_stratixiv_gxb_reconfig_4_alt2gxb_reconfig_9im
+ ip_stratixiv_gxb_reconfig_v91_4_alt2gxb_reconfig_9im_component : ip_stratixiv_gxb_reconfig_v91_4_alt2gxb_reconfig_9im
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -1552,10 +1552,10 @@ END RTL;
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 68 0 reconfig_fromgxb 0 0 68 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_4.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_4.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_4.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_4.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_4_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_4.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_4.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_4.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_4_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_8.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91_8.vhd
similarity index 97%
rename from libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_8.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91_8.vhd
index c06ffc17cb72db6f555bd2a786d228144ba5e76d..a1e89b5d740dd0843b52b4c3fbb275b68e65489e 100644
--- a/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_8.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v91_8.vhd
@@ -4,7 +4,7 @@
-- MODULE: alt2gxb_reconfig
-- ============================================================
--- File Name: ip_stratixiv_gxb_reconfig_8.vhd
+-- File Name: ip_stratixiv_gxb_reconfig_v91_8.vhd
-- Megafunction Name(s):
-- alt2gxb_reconfig
--
@@ -47,7 +47,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_8_alt_dprio_2vj IS
+ ENTITY ip_stratixiv_gxb_reconfig_v91_8_alt_dprio_2vj IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
@@ -65,9 +65,9 @@
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
- END ip_stratixiv_gxb_reconfig_8_alt_dprio_2vj;
+ END ip_stratixiv_gxb_reconfig_v91_8_alt_dprio_2vj;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_8_alt_dprio_2vj IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_8_alt_dprio_2vj IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1226,7 +1226,7 @@
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state242w246w247w(0) OR (wire_pre_amble_cmpr_w_lg_agb243w(0) AND wire_dprio_w_lg_wr_addr_state242w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state357w358w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb243w355w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state422w423w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb243w420w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
- END RTL; --ip_stratixiv_gxb_reconfig_8_alt_dprio_2vj
+ END RTL; --ip_stratixiv_gxb_reconfig_v91_8_alt_dprio_2vj
--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=8 LPM_WIDTH=1 LPM_WIDTHS=3 data result sel
@@ -1236,16 +1236,16 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_8_mux_c6a IS
+ ENTITY ip_stratixiv_gxb_reconfig_v91_8_mux_c6a IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0')
);
- END ip_stratixiv_gxb_reconfig_8_mux_c6a;
+ END ip_stratixiv_gxb_reconfig_v91_8_mux_c6a;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_8_mux_c6a IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_8_mux_c6a IS
SIGNAL wire_l1_w0_n0_mux_dataout : STD_LOGIC;
SIGNAL wire_l1_w0_n1_mux_dataout : STD_LOGIC;
@@ -1271,7 +1271,7 @@
wire_l2_w0_n1_mux_dataout <= data_wire(11) WHEN sel_wire(4) = '1' ELSE data_wire(10);
wire_l3_w0_n0_mux_dataout <= data_wire(13) WHEN sel_wire(8) = '1' ELSE data_wire(12);
- END RTL; --ip_stratixiv_gxb_reconfig_8_mux_c6a
+ END RTL; --ip_stratixiv_gxb_reconfig_v91_8_mux_c6a
LIBRARY altera_mf;
USE altera_mf.all;
@@ -1280,7 +1280,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_8_alt2gxb_reconfig_njm IS
+ ENTITY ip_stratixiv_gxb_reconfig_v91_8_alt2gxb_reconfig_njm IS
PORT
(
busy : OUT STD_LOGIC;
@@ -1288,9 +1288,9 @@
reconfig_fromgxb : IN STD_LOGIC_VECTOR (135 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
- END ip_stratixiv_gxb_reconfig_8_alt2gxb_reconfig_njm;
+ END ip_stratixiv_gxb_reconfig_v91_8_alt2gxb_reconfig_njm;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_8_alt2gxb_reconfig_njm IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_8_alt2gxb_reconfig_njm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1371,7 +1371,7 @@
transceiver_init : IN STD_LOGIC
);
END COMPONENT;
- COMPONENT ip_stratixiv_gxb_reconfig_8_alt_dprio_2vj
+ COMPONENT ip_stratixiv_gxb_reconfig_v91_8_alt_dprio_2vj
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -1390,7 +1390,7 @@
wren_data : IN STD_LOGIC := '0'
);
END COMPONENT;
- COMPONENT ip_stratixiv_gxb_reconfig_8_mux_c6a
+ COMPONENT ip_stratixiv_gxb_reconfig_v91_8_mux_c6a
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
@@ -1449,7 +1449,7 @@
wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
- dprio : ip_stratixiv_gxb_reconfig_8_alt_dprio_2vj
+ dprio : ip_stratixiv_gxb_reconfig_v91_8_alt_dprio_2vj
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
@@ -1472,21 +1472,21 @@
ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
END IF;
END PROCESS;
- dprioout_mux : ip_stratixiv_gxb_reconfig_8_mux_c6a
+ dprioout_mux : ip_stratixiv_gxb_reconfig_v91_8_mux_c6a
PORT MAP (
data => cal_dprioout_wire,
result => wire_dprioout_mux_result,
sel => quad_address(2 DOWNTO 0)
);
- END RTL; --ip_stratixiv_gxb_reconfig_8_alt2gxb_reconfig_njm
+ END RTL; --ip_stratixiv_gxb_reconfig_v91_8_alt2gxb_reconfig_njm
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-ENTITY ip_stratixiv_gxb_reconfig_8 IS
+ENTITY ip_stratixiv_gxb_reconfig_v91_8 IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
@@ -1494,10 +1494,10 @@ ENTITY ip_stratixiv_gxb_reconfig_8 IS
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
-END ip_stratixiv_gxb_reconfig_8;
+END ip_stratixiv_gxb_reconfig_v91_8;
-ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_8 IS
+ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v91_8 IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
@@ -1510,7 +1510,7 @@ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_8 IS
- COMPONENT ip_stratixiv_gxb_reconfig_8_alt2gxb_reconfig_njm
+ COMPONENT ip_stratixiv_gxb_reconfig_v91_8_alt2gxb_reconfig_njm
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
@@ -1523,7 +1523,7 @@ BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
- ip_stratixiv_gxb_reconfig_8_alt2gxb_reconfig_njm_component : ip_stratixiv_gxb_reconfig_8_alt2gxb_reconfig_njm
+ ip_stratixiv_gxb_reconfig_v91_8_alt2gxb_reconfig_njm_component : ip_stratixiv_gxb_reconfig_v91_8_alt2gxb_reconfig_njm
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -1560,10 +1560,10 @@ END RTL;
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 136 0 reconfig_fromgxb 0 0 136 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_8.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_8.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_8.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_8.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_8_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_8.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_8.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_8.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_8.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v91_8_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/ip_stratixiv/readme_ip_stratixiv.txt b/libraries/technology/ip_stratixiv/readme_ip_stratixiv.txt
new file mode 100644
index 0000000000000000000000000000000000000000..5b4ff54f2d34372efa2d3a0213354f15d5fffddc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/readme_ip_stratixiv.txt
@@ -0,0 +1,67 @@
+README: Description of the ip_stratixiv library
+
+Contents:
+1) Single file IP
+ a) ip_stratixiv_fifo*
+ b) ip_stratixiv_ram*
+ c) ip_stratixiv_ddio*
+ d) ip_stratixiv_hssi*
+ e) ip_stratixiv_gxb_reconfig*
+ f) ip_stratixiv_asmi_parallel
+ g) ip_stratixiv_remote_update
+2) Multi file IP
+ a) tse_sgmii*
+
+
+
+
+
+1) Single file IP
+
+The single file IP is kept flat in the top level ip_<device_name> directory.
+
+a) ip_stratixiv_fifo*
+
+
+b) ip_stratixiv_ram*
+
+
+c) ip_stratixiv_ddio*
+
+
+d) ip_stratixiv_hssi*
+
+
+e) ip_stratixiv_gxb_reconfig*
+
+ In theory the gxb_reconfig IP are the same, but in practise they can differ
+ slightly between different Quartus versions. The tr_nonbonded, tse_sgmii_gx
+ and tr_xaui libraries each use a newly generated gxb_reconfig. Trying to let
+ them all use the latest version of the gxb_reconfig IP would require
+ validation on hardware. To avoid having to do this preserve the various
+ versions of gxb_reconfig that were created in time. Versions overview:
+
+ reconfig_fromgxb used in library
+ bus width
+ v9.1 : g_nof_gx * 17 tr_nonbonded
+ v10.1 : ceil(g_nof_gx/4) * 17 tse_sgmii_gx
+ v11.1 : ceil(g_nof_gx/4) * 17 tr_xaui
+
+ . The gxb_reconfig for v9.1 uses wider reconfig_fromgxb bus width.
+ . The reconfig_fromgxb for v10.1 and v11.1 seem idendical except for
+ different internal signal namings.
+
+
+f) ip_stratixiv_asmi_parallel
+
+
+g) ip_stratixiv_remote_update
+
+
+
+
+2) Multi file IP
+
+The multi file IP is kept in sub directories in the top level ip_<device_name>
+directory to be able to keep the generated files together.
+
diff --git a/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd b/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
index 6137374ce8c6928277a8ff4881eded617c024406..38f46e9c42c16a9a0a5fecddb11afc40dd349d4e 100644
--- a/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
@@ -486,7 +486,7 @@ BEGIN
-- ALTGX_RECONFIG Megafunction
------------------------------------------------------------------------------
- u_gxb_reconfig : ip_stratixiv_gxb_reconfig -- Create one gxb_reconfig module for all ALTGX instances
+ u_gxb_reconfig : ip_stratixiv_gxb_reconfig_v91 -- Create one gxb_reconfig module for all ALTGX instances
GENERIC MAP (
g_nof_gx => g_nof_gx,
g_fromgxb_bus_w => c_reconf_fromgxb_bus_w, -- = 17
diff --git a/libraries/technology/tse/tech_tse_stratixiv.vhd b/libraries/technology/tse/tech_tse_stratixiv.vhd
index 0b69c46c5c2bd8de13d600058a684a731fe1a46d..a056fc34f1f78770eac7a96a1b12a5c6f7baf7a9 100644
--- a/libraries/technology/tse/tech_tse_stratixiv.vhd
+++ b/libraries/technology/tse/tech_tse_stratixiv.vhd
@@ -249,7 +249,7 @@ BEGIN
rxp => eth_rxp
);
- u_gx_reconfig : ip_stratixiv_gx_reconfig
+ u_gx_reconfig : ip_stratixiv_gxb_reconfig_v101
GENERIC MAP (
g_nof_gx => c_nof_gx,
g_fromgxb_bus_w => reconfig_fromgxb'LENGTH,