From 4bb66cbb9c37d70be46511d4206c4f819c1c29ed Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Mon, 14 Feb 2022 13:40:36 +0100
Subject: [PATCH] fixed 10gbase_r_3 component definition + other minor
improvements
---
.../tb_lofar2_unb2b_sdp_station_xsub_ring.vhd | 4 +
.../lofar2_unb2c_sdp_station.fpga.yaml | 154 +++++------
.../qsys_lofar2_unb2c_sdp_station_cpu_0.ip | 4 +-
...2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip | 28 +-
...far2_unb2c_sdp_station_reg_tr_10gbe_mac.ip | 18 +-
.../quartus/lofar2_unb2c_sdp_station_pins.tcl | 98 -------
.../qsys_lofar2_unb2c_sdp_station.qsys | 252 +++++++++---------
.../lofar2_unb2c_sdp_station_full/hdllib.cfg | 2 +-
.../lofar2_unb2c_sdp_station_full_pins.tcl | 120 +++++++++
.../hdllib.cfg | 2 +-
...ofar2_unb2c_sdp_station_xsub_ring_pins.tcl | 96 +++++++
.../qsys_lofar2_unb2c_sdp_station_pkg.vhd | 33 ++-
.../sdp/src/vhdl/node_sdp_correlator.vhd | 4 +-
.../lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd | 5 +-
.../base/dp/src/vhdl/dp_fifo_fill_eop.vhd | 1 +
.../tech_10gbase_r_component_pkg.vhd | 120 ++++-----
16 files changed, 536 insertions(+), 405 deletions(-)
create mode 100644 applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl
create mode 100644 applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
index 9ae1074186..70f33ea248 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -462,6 +462,8 @@ BEGIN
REPORT "nof_valid = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT", J * 8+5, rd_data, tb_clk); --nof_err
REPORT "nof_err = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT", J * 8+6, rd_data, tb_clk); --latency
+ REPORT "latency = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
END LOOP;
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT", 0, rd_data, tb_clk); --status bits
REPORT "sync_timeout = " & INTEGER'IMAGE(TO_UINT(rd_data(2 DOWNTO 2))) & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
@@ -473,6 +475,8 @@ BEGIN
REPORT "nof_valid = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT", 5, rd_data, tb_clk); --nof_err
REPORT "nof_err = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT", 6, rd_data, tb_clk); --latency
+ REPORT "latency = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
END LOOP;
---------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
index a0a5c66397..1ed97e4462 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
@@ -337,80 +337,80 @@ peripherals:
#############################################################################
# BF = Beamformer (from node_sdp_beamformer.vhd)
#############################################################################
-
- - peripheral_name: reorder/reorder_col_wide
- number_of_peripherals: c_N_beamsets
- peripheral_span: ceil_pow2(c_P_pfb) * ceil_pow2(c_S_sub_bf * c_Q_fft) * MM_BUS_SIZE # number_of_ports = c_P_pfb, mm_port_span = ceil_pow2(c_S_sub_bf * c_Q_fft) words
- parameter_overrides:
- - { name: g_wb_factor, value: c_P_pfb }
- - { name: g_nof_ch_in, value: c_N_sub * c_Q_fft }
- - { name: g_nof_ch_sel, value: c_S_sub_bf * c_Q_fft }
- mm_port_names:
- - RAM_SS_SS_WIDE
-
- - peripheral_name: sdp/sdp_bf_weights
- number_of_peripherals: c_N_beamsets
- peripheral_span: ceil_pow2(c_N_pol_bf * c_P_pfb) * ceil_pow2(c_Q_fft * c_S_sub_bf) * MM_BUS_SIZE # number_of_ports = c_N_pol_bf * c_P_pfb, mm_port_span = ceil_pow2(c_Q_fft * c_S_sub_bf) words
- mm_port_names:
- - RAM_BF_WEIGHTS
-
- - peripheral_name: sdp/sdp_bf_scale
- number_of_peripherals: c_N_beamsets
- peripheral_span: 2 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 2 words
- parameter_overrides:
- - { name: g_gain_w, value: c_W_beamlet_scale }
- - { name: g_lsb_w, value: 0 - c_W_beamlet_resolution}
- mm_port_names:
- - REG_BF_SCALE
-
- - peripheral_name: sdp/sdp_beamformer_output_hdr_dat
- number_of_peripherals: c_N_beamsets
- peripheral_span: 64 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 64 words
- mm_port_names:
- - REG_HDR_DAT
-
- - peripheral_name: dp/dp_xonoff
- number_of_peripherals: c_N_beamsets
- peripheral_span: 2 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 2 words
- parameter_overrides:
- - { name: g_nof_streams, value: 1 }
- - { name: g_combine_streams, value: False }
- mm_port_names:
- - REG_DP_XONOFF
-
- - peripheral_name: st/st_bst_for_sdp
- number_of_peripherals: c_N_beamsets
- peripheral_span: ceil_pow2(c_stat_data_sz * c_S_sub_bf * c_N_pol_bf) * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = ceil_pow2(c_stat_data_sz * c_S_sub_bf * c_N_pol_bf) words
- mm_port_names:
- - RAM_ST_BST
-
- - peripheral_name: common/common_variable_delay
- peripheral_group: bst
- number_of_peripherals: c_N_beamsets
- peripheral_span: 2 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 2 words
- mm_port_names:
- - REG_STAT_ENABLE_BST
-
- - peripheral_name: sdp/sdp_statistics_offload_hdr_dat_bst
- peripheral_group: bst
- number_of_peripherals: c_N_beamsets
- peripheral_span: 64 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 64 words
- mm_port_names:
- - REG_STAT_HDR_DAT_BST
-
- - peripheral_name: nw_10GbE/nw_10GbE_unb2legacy # For beamlet output
- peripheral_group: beamlet_output
- parameter_overrides:
- - { name: g_nof_macs, value: 1 }
- mm_port_names:
- - REG_NW_10GBE_MAC
-
- - peripheral_name: nw_10GbE/nw_10GbE_eth10g # For beamlet output
- peripheral_group: beamlet_output
- parameter_overrides:
- - { name: g_nof_macs, value: 1 }
- mm_port_names:
- - REG_NW_10GBE_ETH10G
-
-
-
+#
+# - peripheral_name: reorder/reorder_col_wide
+# number_of_peripherals: c_N_beamsets
+# peripheral_span: ceil_pow2(c_P_pfb) * ceil_pow2(c_S_sub_bf * c_Q_fft) * MM_BUS_SIZE # number_of_ports = c_P_pfb, mm_port_span = ceil_pow2(c_S_sub_bf * c_Q_fft) words
+# parameter_overrides:
+# - { name: g_wb_factor, value: c_P_pfb }
+# - { name: g_nof_ch_in, value: c_N_sub * c_Q_fft }
+# - { name: g_nof_ch_sel, value: c_S_sub_bf * c_Q_fft }
+# mm_port_names:
+# - RAM_SS_SS_WIDE
+#
+# - peripheral_name: sdp/sdp_bf_weights
+# number_of_peripherals: c_N_beamsets
+# peripheral_span: ceil_pow2(c_N_pol_bf * c_P_pfb) * ceil_pow2(c_Q_fft * c_S_sub_bf) * MM_BUS_SIZE # number_of_ports = c_N_pol_bf * c_P_pfb, mm_port_span = ceil_pow2(c_Q_fft * c_S_sub_bf) words
+# mm_port_names:
+# - RAM_BF_WEIGHTS
+#
+# - peripheral_name: sdp/sdp_bf_scale
+# number_of_peripherals: c_N_beamsets
+# peripheral_span: 2 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 2 words
+# parameter_overrides:
+# - { name: g_gain_w, value: c_W_beamlet_scale }
+# - { name: g_lsb_w, value: 0 - c_W_beamlet_resolution}
+# mm_port_names:
+# - REG_BF_SCALE
+#
+# - peripheral_name: sdp/sdp_beamformer_output_hdr_dat
+# number_of_peripherals: c_N_beamsets
+# peripheral_span: 64 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 64 words
+# mm_port_names:
+# - REG_HDR_DAT
+#
+# - peripheral_name: dp/dp_xonoff
+# number_of_peripherals: c_N_beamsets
+# peripheral_span: 2 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 2 words
+# parameter_overrides:
+# - { name: g_nof_streams, value: 1 }
+# - { name: g_combine_streams, value: False }
+# mm_port_names:
+# - REG_DP_XONOFF
+#
+# - peripheral_name: st/st_bst_for_sdp
+# number_of_peripherals: c_N_beamsets
+# peripheral_span: ceil_pow2(c_stat_data_sz * c_S_sub_bf * c_N_pol_bf) * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = ceil_pow2(c_stat_data_sz * c_S_sub_bf * c_N_pol_bf) words
+# mm_port_names:
+# - RAM_ST_BST
+#
+# - peripheral_name: common/common_variable_delay
+# peripheral_group: bst
+# number_of_peripherals: c_N_beamsets
+# peripheral_span: 2 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 2 words
+# mm_port_names:
+# - REG_STAT_ENABLE_BST
+#
+# - peripheral_name: sdp/sdp_statistics_offload_hdr_dat_bst
+# peripheral_group: bst
+# number_of_peripherals: c_N_beamsets
+# peripheral_span: 64 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 64 words
+# mm_port_names:
+# - REG_STAT_HDR_DAT_BST
+#
+# - peripheral_name: nw_10GbE/nw_10GbE_unb2legacy # For beamlet output
+# peripheral_group: beamlet_output
+# parameter_overrides:
+# - { name: g_nof_macs, value: 1 }
+# mm_port_names:
+# - REG_NW_10GBE_MAC
+#
+# - peripheral_name: nw_10GbE/nw_10GbE_eth10g # For beamlet output
+# peripheral_group: beamlet_output
+# parameter_overrides:
+# - { name: g_nof_macs, value: 1 }
+# mm_port_names:
+# - REG_NW_10GBE_ETH10G
+#
+#
+#
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
index fd3789c8a4..e0b793d115 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
@@ -2302,7 +2302,7 @@
<ipxact:parameter parameterId="dataSlaveMapParam" type="string">
<ipxact:name>dataSlaveMapParam</ipxact:name>
<ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_input.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE8000' end='0xF0000' datawidth='32' /><slave name='jesd204b.mem' start='0xF0000' end='0xF4000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0xF4000' end='0xF4200' datawidth='32' /><slave name='reg_wg.mem' start='0xF4200' end='0xF4300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0xF4300' end='0xF4400' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0xF4400' end='0xF4440' datawidth='32' /><slave name='reg_bsn_align.mem' start='0xF4440' end='0xF4480' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xF4480' end='0xF44C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xF44C0' end='0xF4500' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xF4500' end='0xF4540' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xF4540' end='0xF4580' datawidth='32' /><slave name='reg_xst_udp_monitor.mem' start='0xF4580' end='0xF45A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_output.mem' start='0xF45A0' end='0xF45C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xF45C0' end='0xF45E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xF45E0' end='0xF4600' datawidth='32' /><slave name='reg_epcs.mem' start='0xF4600' end='0xF4620' datawidth='32' /><slave name='reg_remu.mem' start='0xF4620' end='0xF4640' datawidth='32' /><slave name='reg_ring_info.mem' start='0xF4640' end='0xF4650' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0xF4650' end='0xF4660' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xF4660' end='0xF4670' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xF4670' end='0xF4680' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xF4680' end='0xF4690' datawidth='32' /><slave name='pio_pps.mem' start='0xF4690' end='0xF46A0' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0xF46A0' end='0xF46A8' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0xF46A8' end='0xF46B0' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0xF46B0' end='0xF46B8' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xF46B8' end='0xF46C0' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xF46C0' end='0xF46C8' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xF46C8' end='0xF46D0' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xF46D0' end='0xF46D8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xF46D8' end='0xF46E0' datawidth='32' /><slave name='reg_si.mem' start='0xF46E0' end='0xF46E8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xF46E8' end='0xF46F0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xF46F0' end='0xF46F8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xF46F8' end='0xF4700' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xF4700' end='0xF4708' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xF4708' end='0xF4710' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_input.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C400' end='0x10C440' datawidth='32' /><slave name='reg_bsn_align.mem' start='0x10C440' end='0x10C480' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C480' end='0x10C4C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C4C0' end='0x10C500' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C500' end='0x10C540' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C540' end='0x10C580' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C580' end='0x10C5A0' datawidth='32' /><slave name='reg_xst_udp_monitor.mem' start='0x10C5A0' end='0x10C5C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_output.mem' start='0x10C5C0' end='0x10C5E0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C5E0' end='0x10C600' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C600' end='0x10C620' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C620' end='0x10C640' datawidth='32' /><slave name='reg_remu.mem' start='0x10C640' end='0x10C660' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C660' end='0x10C670' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C670' end='0x10C680' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C680' end='0x10C690' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C690' end='0x10C6A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C6A0' end='0x10C6B0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C6B0' end='0x10C6C0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C6C0' end='0x10C6C8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C6C8' end='0x10C6D0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C6D0' end='0x10C6D8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C6D8' end='0x10C6E0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C6E0' end='0x10C6E8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C6E8' end='0x10C6F0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C6F0' end='0x10C6F8' datawidth='32' /><slave name='reg_si.mem' start='0x10C6F8' end='0x10C700' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C700' end='0x10C708' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C708' end='0x10C710' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10C710' end='0x10C718' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10C718' end='0x10C720' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C720' end='0x10C728' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
<ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -3589,7 +3589,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bsn_align_input.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0xE0000' end='0xE8000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0xE8000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0xF0000' end='0xF4000' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0xF4000' end='0xF4200' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0xF4200' end='0xF4300' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0xF4300' end='0xF4400' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0xF4400' end='0xF4440' datawidth='32' /&gt;&lt;slave name='reg_bsn_align.mem' start='0xF4440' end='0xF4480' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xF4480' end='0xF44C0' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0xF44C0' end='0xF4500' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0xF4500' end='0xF4540' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xF4540' end='0xF4580' datawidth='32' /&gt;&lt;slave name='reg_xst_udp_monitor.mem' start='0xF4580' end='0xF45A0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bsn_align_output.mem' start='0xF45A0' end='0xF45C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0xF45C0' end='0xF45E0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0xF45E0' end='0xF4600' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0xF4600' end='0xF4620' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0xF4620' end='0xF4640' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0xF4640' end='0xF4650' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0xF4650' end='0xF4660' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0xF4660' end='0xF4670' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0xF4670' end='0xF4680' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0xF4680' end='0xF4690' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0xF4690' end='0xF46A0' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0xF46A0' end='0xF46A8' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0xF46A8' end='0xF46B0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0xF46B0' end='0xF46B8' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0xF46B8' end='0xF46C0' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0xF46C0' end='0xF46C8' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0xF46C8' end='0xF46D0' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0xF46D0' end='0xF46D8' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0xF46D8' end='0xF46E0' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0xF46E0' end='0xF46E8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0xF46E8' end='0xF46F0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0xF46F0' end='0xF46F8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0xF46F8' end='0xF4700' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0xF4700' end='0xF4708' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0xF4708' end='0xF4710' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bsn_align_input.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10C400' end='0x10C440' datawidth='32' /&gt;&lt;slave name='reg_bsn_align.mem' start='0x10C440' end='0x10C480' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C480' end='0x10C4C0' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x10C4C0' end='0x10C500' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x10C500' end='0x10C540' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x10C540' end='0x10C580' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10C580' end='0x10C5A0' datawidth='32' /&gt;&lt;slave name='reg_xst_udp_monitor.mem' start='0x10C5A0' end='0x10C5C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bsn_align_output.mem' start='0x10C5C0' end='0x10C5E0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x10C5E0' end='0x10C600' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x10C600' end='0x10C620' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x10C620' end='0x10C640' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x10C640' end='0x10C660' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x10C660' end='0x10C670' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C670' end='0x10C680' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x10C680' end='0x10C690' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x10C690' end='0x10C6A0' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x10C6A0' end='0x10C6B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x10C6B0' end='0x10C6C0' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x10C6C0' end='0x10C6C8' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x10C6C8' end='0x10C6D0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x10C6D0' end='0x10C6D8' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x10C6D8' end='0x10C6E0' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10C6E0' end='0x10C6E8' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x10C6E8' end='0x10C6F0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x10C6F0' end='0x10C6F8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x10C6F8' end='0x10C700' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x10C700' end='0x10C708' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x10C708' end='0x10C710' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x10C710' end='0x10C718' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x10C718' end='0x10C720' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C720' end='0x10C728' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
index c01a20bd3f..93611a76b1 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
+ <ipxact:value>32</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -664,7 +664,12 @@
<ipxact:name>avs_mem_address</ipxact:name>
<ipxact:wire>
<ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>2</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
@@ -765,7 +770,12 @@
<ipxact:name>coe_address_export</ipxact:name>
<ipxact:wire>
<ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>2</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
@@ -850,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
+ <ipxact:value>3</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -987,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1056,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1285,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1452,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
index 92da1e6003..d4050cec45 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>32768</ipxact:value>
+ <ipxact:value>131072</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>12</ipxact:right>
+ <ipxact:right>14</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>12</ipxact:right>
+ <ipxact:right>14</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -860,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>13</ipxact:value>
+ <ipxact:value>15</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -997,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1066,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1295,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1462,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
index 83b9a584a0..2d6b00be0a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
@@ -39,61 +39,12 @@ set_instance_assignment -name IO_STANDARD LVDS -to SB_CLK
# internal termination should be enabled.
set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SB_CLK
-
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
-
set_location_assignment PIN_AT31 -to QSFP_RST
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST
-
-### QSFP_0_0
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[0]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0]
-
-### QSFP_1_0
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[0]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[0]
-
# QSFP_0_RX
set_location_assignment PIN_AN38 -to QSFP_0_RX[0]
set_location_assignment PIN_AM40 -to QSFP_0_RX[1]
@@ -137,55 +88,6 @@ set_location_assignment PIN_J42 -to RING_1_TX[1]
set_location_assignment PIN_G42 -to RING_1_TX[2]
set_location_assignment PIN_F44 -to RING_1_TX[3]
-#RING_0 RX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[0]
-
-#RING_1 RX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0]
-
-#RING_0 TX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
-
-#RING_1 TX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0]
-
-
#=====================
# JESD pins
# ====================
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
index d9a3aae9d9..576264761a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
@@ -83,7 +83,7 @@
{
datum baseAddress
{
- value = "983040";
+ value = "1081344";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "1001224";
+ value = "1099552";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "1001152";
+ value = "1099480";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "1001104";
+ value = "1099440";
type = "String";
}
}
@@ -218,7 +218,7 @@
{
datum baseAddress
{
- value = "524288";
+ value = "655360";
type = "String";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "950272";
+ value = "1048576";
type = "String";
}
}
@@ -266,7 +266,7 @@
{
datum baseAddress
{
- value = "786432";
+ value = "917504";
type = "String";
}
}
@@ -298,7 +298,7 @@
{
datum baseAddress
{
- value = "655360";
+ value = "786432";
type = "String";
}
}
@@ -330,7 +330,7 @@
{
datum baseAddress
{
- value = "98304";
+ value = "32768";
type = "String";
}
}
@@ -346,7 +346,7 @@
{
datum baseAddress
{
- value = "851968";
+ value = "983040";
type = "String";
}
}
@@ -378,7 +378,7 @@
{
datum baseAddress
{
- value = "720896";
+ value = "851968";
type = "String";
}
}
@@ -394,7 +394,7 @@
{
datum baseAddress
{
- value = "1000192";
+ value = "1098496";
type = "String";
}
}
@@ -410,7 +410,7 @@
{
datum baseAddress
{
- value = "1001088";
+ value = "1099424";
type = "String";
}
}
@@ -426,7 +426,7 @@
{
datum baseAddress
{
- value = "1000512";
+ value = "1098816";
type = "String";
}
}
@@ -458,7 +458,7 @@
{
datum baseAddress
{
- value = "13312";
+ value = "512";
type = "String";
}
}
@@ -474,7 +474,7 @@
{
datum baseAddress
{
- value = "1000864";
+ value = "1099200";
type = "String";
}
}
@@ -490,7 +490,7 @@
{
datum baseAddress
{
- value = "12800";
+ value = "13312";
type = "String";
}
}
@@ -506,7 +506,7 @@
{
datum baseAddress
{
- value = "512";
+ value = "12800";
type = "String";
}
}
@@ -522,7 +522,7 @@
{
datum baseAddress
{
- value = "1001176";
+ value = "1099504";
type = "String";
}
}
@@ -538,7 +538,7 @@
{
datum baseAddress
{
- value = "1000896";
+ value = "1099232";
type = "String";
}
}
@@ -554,7 +554,7 @@
{
datum baseAddress
{
- value = "1000576";
+ value = "1098880";
type = "String";
}
}
@@ -570,7 +570,7 @@
{
datum baseAddress
{
- value = "1000640";
+ value = "1098944";
type = "String";
}
}
@@ -602,7 +602,7 @@
{
datum baseAddress
{
- value = "1001040";
+ value = "1099376";
type = "String";
}
}
@@ -618,7 +618,7 @@
{
datum baseAddress
{
- value = "1000448";
+ value = "1098752";
type = "String";
}
}
@@ -634,7 +634,7 @@
{
datum baseAddress
{
- value = "1001168";
+ value = "1099496";
type = "String";
}
}
@@ -666,7 +666,7 @@
{
datum baseAddress
{
- value = "1001072";
+ value = "1099408";
type = "String";
}
}
@@ -687,7 +687,7 @@
{
datum baseAddress
{
- value = "1001216";
+ value = "1099544";
type = "String";
}
}
@@ -708,7 +708,7 @@
{
datum baseAddress
{
- value = "1001208";
+ value = "1099536";
type = "String";
}
}
@@ -729,7 +729,7 @@
{
datum baseAddress
{
- value = "1000960";
+ value = "1099296";
type = "String";
}
}
@@ -745,7 +745,7 @@
{
datum baseAddress
{
- value = "1000928";
+ value = "1099264";
type = "String";
}
}
@@ -766,7 +766,7 @@
{
datum baseAddress
{
- value = "1000768";
+ value = "1099072";
type = "String";
}
}
@@ -782,7 +782,7 @@
{
datum baseAddress
{
- value = "999424";
+ value = "1097728";
type = "String";
}
}
@@ -803,7 +803,7 @@
{
datum baseAddress
{
- value = "1001200";
+ value = "1099528";
type = "String";
}
}
@@ -824,7 +824,7 @@
{
datum baseAddress
{
- value = "1001192";
+ value = "1099520";
type = "String";
}
}
@@ -840,7 +840,7 @@
{
datum baseAddress
{
- value = "1001128";
+ value = "1099456";
type = "String";
}
}
@@ -856,7 +856,7 @@
{
datum baseAddress
{
- value = "1001160";
+ value = "1099488";
type = "String";
}
}
@@ -872,7 +872,7 @@
{
datum baseAddress
{
- value = "917504";
+ value = "98304";
type = "String";
}
}
@@ -893,7 +893,7 @@
{
datum baseAddress
{
- value = "1000992";
+ value = "1099328";
type = "String";
}
}
@@ -909,7 +909,7 @@
{
datum baseAddress
{
- value = "1001024";
+ value = "1099360";
type = "String";
}
}
@@ -925,7 +925,7 @@
{
datum baseAddress
{
- value = "1001120";
+ value = "12296";
type = "String";
}
}
@@ -941,7 +941,7 @@
{
datum baseAddress
{
- value = "1000704";
+ value = "1099008";
type = "String";
}
}
@@ -957,7 +957,7 @@
{
datum baseAddress
{
- value = "1001184";
+ value = "1099512";
type = "String";
}
}
@@ -973,7 +973,7 @@
{
datum baseAddress
{
- value = "1001056";
+ value = "1099392";
type = "String";
}
}
@@ -989,7 +989,7 @@
{
datum baseAddress
{
- value = "1001144";
+ value = "1099472";
type = "String";
}
}
@@ -1005,7 +1005,7 @@
{
datum baseAddress
{
- value = "1001136";
+ value = "1099464";
type = "String";
}
}
@@ -1069,7 +1069,7 @@
{
datum baseAddress
{
- value = "12296";
+ value = "1099136";
type = "String";
}
}
@@ -1085,7 +1085,7 @@
{
datum baseAddress
{
- value = "32768";
+ value = "524288";
type = "String";
}
}
@@ -1127,7 +1127,7 @@
{
datum baseAddress
{
- value = "999936";
+ value = "1098240";
type = "String";
}
}
@@ -1143,7 +1143,7 @@
{
datum baseAddress
{
- value = "1000832";
+ value = "1099168";
type = "String";
}
}
@@ -7936,7 +7936,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_input.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE8000' end='0xF0000' datawidth='32' /><slave name='jesd204b.mem' start='0xF0000' end='0xF4000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0xF4000' end='0xF4200' datawidth='32' /><slave name='reg_wg.mem' start='0xF4200' end='0xF4300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0xF4300' end='0xF4400' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0xF4400' end='0xF4440' datawidth='32' /><slave name='reg_bsn_align.mem' start='0xF4440' end='0xF4480' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0xF4480' end='0xF44C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xF44C0' end='0xF4500' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xF4500' end='0xF4540' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xF4540' end='0xF4580' datawidth='32' /><slave name='reg_xst_udp_monitor.mem' start='0xF4580' end='0xF45A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_output.mem' start='0xF45A0' end='0xF45C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xF45C0' end='0xF45E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xF45E0' end='0xF4600' datawidth='32' /><slave name='reg_epcs.mem' start='0xF4600' end='0xF4620' datawidth='32' /><slave name='reg_remu.mem' start='0xF4620' end='0xF4640' datawidth='32' /><slave name='reg_ring_info.mem' start='0xF4640' end='0xF4650' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0xF4650' end='0xF4660' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xF4660' end='0xF4670' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xF4670' end='0xF4680' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xF4680' end='0xF4690' datawidth='32' /><slave name='pio_pps.mem' start='0xF4690' end='0xF46A0' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0xF46A0' end='0xF46A8' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0xF46A8' end='0xF46B0' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0xF46B0' end='0xF46B8' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xF46B8' end='0xF46C0' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xF46C0' end='0xF46C8' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xF46C8' end='0xF46D0' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xF46D0' end='0xF46D8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xF46D8' end='0xF46E0' datawidth='32' /><slave name='reg_si.mem' start='0xF46E0' end='0xF46E8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xF46E8' end='0xF46F0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xF46F0' end='0xF46F8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xF46F8' end='0xF4700' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xF4700' end='0xF4708' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xF4708' end='0xF4710' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_input.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C400' end='0x10C440' datawidth='32' /><slave name='reg_bsn_align.mem' start='0x10C440' end='0x10C480' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C480' end='0x10C4C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C4C0' end='0x10C500' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C500' end='0x10C540' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C540' end='0x10C580' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C580' end='0x10C5A0' datawidth='32' /><slave name='reg_xst_udp_monitor.mem' start='0x10C5A0' end='0x10C5C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_output.mem' start='0x10C5C0' end='0x10C5E0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C5E0' end='0x10C600' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C600' end='0x10C620' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C620' end='0x10C640' datawidth='32' /><slave name='reg_remu.mem' start='0x10C640' end='0x10C660' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C660' end='0x10C670' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C670' end='0x10C680' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C680' end='0x10C690' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C690' end='0x10C6A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C6A0' end='0x10C6B0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C6B0' end='0x10C6C0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C6C0' end='0x10C6C8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C6C8' end='0x10C6D0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C6D0' end='0x10C6D8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C6D8' end='0x10C6E0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C6E0' end='0x10C6E8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C6E8' end='0x10C6F0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C6F0' end='0x10C6F8' datawidth='32' /><slave name='reg_si.mem' start='0x10C6F8' end='0x10C700' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C700' end='0x10C708' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C708' end='0x10C710' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10C710' end='0x10C718' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10C718' end='0x10C720' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C720' end='0x10C728' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -35589,17 +35589,21 @@
</ports>
<assignments>
<assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -35639,6 +35643,7 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
+ <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -64109,21 +64114,17 @@
</ports>
<assignments>
<assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -64163,7 +64164,6 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
- <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -74900,7 +74900,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -74969,7 +74969,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -75198,7 +75198,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -75376,11 +75376,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -75480,7 +75480,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -75549,7 +75549,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -75778,7 +75778,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -76041,7 +76041,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -76110,7 +76110,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -76339,7 +76339,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -76517,11 +76517,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -76621,7 +76621,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -76690,7 +76690,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -76919,7 +76919,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -82976,7 +82976,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4708" />
+ <parameter name="baseAddress" value="0x0010c720" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83056,7 +83056,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4690" />
+ <parameter name="baseAddress" value="0x0010c6b0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83096,7 +83096,7 @@
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4620" />
+ <parameter name="baseAddress" value="0x0010c640" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83116,7 +83116,7 @@
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4600" />
+ <parameter name="baseAddress" value="0x0010c620" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83136,7 +83136,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4700" />
+ <parameter name="baseAddress" value="0x0010c718" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83156,7 +83156,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f46f8" />
+ <parameter name="baseAddress" value="0x0010c710" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83176,7 +83176,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f46f0" />
+ <parameter name="baseAddress" value="0x0010c708" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83196,7 +83196,7 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f46e8" />
+ <parameter name="baseAddress" value="0x0010c700" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83216,7 +83216,7 @@
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f45e0" />
+ <parameter name="baseAddress" value="0x0010c600" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83236,7 +83236,7 @@
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4540" />
+ <parameter name="baseAddress" value="0x0010c540" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83256,7 +83256,7 @@
start="cpu_0.data_master"
end="ram_st_sst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000d0000" />
+ <parameter name="baseAddress" value="0x000f0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83276,7 +83276,7 @@
start="cpu_0.data_master"
end="reg_si.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f46e0" />
+ <parameter name="baseAddress" value="0x0010c6f8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83296,7 +83296,7 @@
start="cpu_0.data_master"
end="ram_fil_coefs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000c0000" />
+ <parameter name="baseAddress" value="0x000e0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83336,7 +83336,7 @@
start="cpu_0.data_master"
end="reg_aduh_monitor.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4300" />
+ <parameter name="baseAddress" value="0x0010c300" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83356,7 +83356,7 @@
start="cpu_0.data_master"
end="ram_wg.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000b0000" />
+ <parameter name="baseAddress" value="0x000d0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83396,7 +83396,7 @@
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f46d8" />
+ <parameter name="baseAddress" value="0x0010c6f0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83416,7 +83416,7 @@
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f45c0" />
+ <parameter name="baseAddress" value="0x0010c5e0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83436,7 +83436,7 @@
start="cpu_0.data_master"
end="reg_wg.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4200" />
+ <parameter name="baseAddress" value="0x0010c200" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83476,7 +83476,7 @@
start="cpu_0.data_master"
end="jesd204b.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f0000" />
+ <parameter name="baseAddress" value="0x00108000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83496,7 +83496,7 @@
start="cpu_0.data_master"
end="reg_dp_selector.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f46d0" />
+ <parameter name="baseAddress" value="0x0010c6e8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83516,7 +83516,7 @@
start="cpu_0.data_master"
end="ram_equalizer_gains.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000e8000" />
+ <parameter name="baseAddress" value="0x00100000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83536,7 +83536,7 @@
start="cpu_0.data_master"
end="ram_ss_ss_wide.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000a0000" />
+ <parameter name="baseAddress" value="0x000c0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83556,7 +83556,7 @@
start="cpu_0.data_master"
end="ram_bf_weights.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00080000" />
+ <parameter name="baseAddress" value="0x000a0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83576,7 +83576,7 @@
start="cpu_0.data_master"
end="reg_bf_scale.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4680" />
+ <parameter name="baseAddress" value="0x0010c6a0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83596,7 +83596,7 @@
start="cpu_0.data_master"
end="reg_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4000" />
+ <parameter name="baseAddress" value="0x0010c000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83616,7 +83616,7 @@
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4670" />
+ <parameter name="baseAddress" value="0x0010c690" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83656,7 +83656,7 @@
start="cpu_0.data_master"
end="reg_sdp_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4500" />
+ <parameter name="baseAddress" value="0x0010c500" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83676,7 +83676,7 @@
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f46c8" />
+ <parameter name="baseAddress" value="0x0010c6e0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83696,7 +83696,7 @@
start="cpu_0.data_master"
end="reg_nw_10gbe_mac.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000e0000" />
+ <parameter name="baseAddress" value="0x00018000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83756,7 +83756,7 @@
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f46c0" />
+ <parameter name="baseAddress" value="0x0010c6d8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83776,7 +83776,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f46b8" />
+ <parameter name="baseAddress" value="0x0010c6d0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83816,7 +83816,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_bst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4660" />
+ <parameter name="baseAddress" value="0x0010c680" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83856,7 +83856,7 @@
start="cpu_0.data_master"
end="reg_crosslets_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f44c0" />
+ <parameter name="baseAddress" value="0x0010c4c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83896,7 +83896,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f46b0" />
+ <parameter name="baseAddress" value="0x0010c6c8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83936,7 +83936,7 @@
start="cpu_0.data_master"
end="reg_bsn_sync_scheduler_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4480" />
+ <parameter name="baseAddress" value="0x0010c480" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83956,7 +83956,7 @@
start="cpu_0.data_master"
end="ram_st_histogram.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00018000" />
+ <parameter name="baseAddress" value="0x8000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83976,7 +83976,7 @@
start="cpu_0.data_master"
end="reg_nof_crosslets.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f46a8" />
+ <parameter name="baseAddress" value="0x0010c6c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83996,7 +83996,7 @@
start="cpu_0.data_master"
end="reg_bsn_align.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4440" />
+ <parameter name="baseAddress" value="0x0010c440" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84016,7 +84016,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_bsn_align_output.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f45a0" />
+ <parameter name="baseAddress" value="0x0010c5c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84036,7 +84036,7 @@
start="cpu_0.data_master"
end="reg_xst_udp_monitor.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4580" />
+ <parameter name="baseAddress" value="0x0010c5a0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84056,7 +84056,7 @@
start="cpu_0.data_master"
end="reg_ring_lane_info_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f46a0" />
+ <parameter name="baseAddress" value="0x3008" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84076,7 +84076,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_rx_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3200" />
+ <parameter name="baseAddress" value="0x3400" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84096,7 +84096,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_tx_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0200" />
+ <parameter name="baseAddress" value="0x3200" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84116,7 +84116,7 @@
start="cpu_0.data_master"
end="reg_dp_block_validate_err_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4400" />
+ <parameter name="baseAddress" value="0x0010c400" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84136,7 +84136,7 @@
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4650" />
+ <parameter name="baseAddress" value="0x0010c670" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84156,7 +84156,7 @@
start="cpu_0.data_master"
end="reg_ring_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f4640" />
+ <parameter name="baseAddress" value="0x0010c660" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84176,7 +84176,7 @@
start="cpu_0.data_master"
end="reg_tr_10gbe_eth10g.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3008" />
+ <parameter name="baseAddress" value="0x0010c580" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84196,7 +84196,7 @@
start="cpu_0.data_master"
end="reg_tr_10gbe_mac.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0x00080000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84216,7 +84216,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_bsn_align_input.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3400" />
+ <parameter name="baseAddress" value="0x0200" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
index afdba82f37..303b2ff966 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
@@ -36,7 +36,7 @@ quartus_sdc_files =
#$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
- ../../quartus/lofar2_unb2c_sdp_station_pins.tcl
+ lofar2_unb2c_sdp_station_full_pins.tcl
quartus_vhdl_files =
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl
new file mode 100644
index 0000000000..d73951bdcc
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl
@@ -0,0 +1,120 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+
+# Define extra pins for this revision.
+### QSFP_0_0 For ring
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0]
+
+### QSFP_1_0 For BF
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[0]
+
+
+#RING_0 RX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[0]
+
+#RING_1 RX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0]
+
+#RING_0 TX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
+
+#RING_1 TX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0]
+
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
index 9acb80183e..c0ad06a755 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
@@ -36,7 +36,7 @@ quartus_sdc_files =
#$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
- ../../quartus/lofar2_unb2c_sdp_station_pins.tcl
+ lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
quartus_vhdl_files =
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
new file mode 100644
index 0000000000..040b494415
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
@@ -0,0 +1,96 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+
+# Define extra pins for this revision.
+### QSFP_0_0 For ring
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0]
+
+#RING_0 RX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[0]
+
+#RING_1 RX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0]
+
+#RING_0 TX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
+
+#RING_1 TX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0]
+
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index 2c1fb0955b..e98fce91c7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -183,6 +183,20 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
reg_bsn_monitor_input_reset_export : out std_logic; -- export
reg_bsn_monitor_input_write_export : out std_logic; -- export
reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bsn_align_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_input_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_bsn_align_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bsn_align_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_bsn_align_output_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_output_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_output_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_bsn_align_output_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_output_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bsn_align_output_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bsn_align_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
@@ -309,13 +323,6 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
reg_hdr_dat_reset_export : out std_logic; -- export
reg_hdr_dat_write_export : out std_logic; -- export
reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_input_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_input_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bsn_align_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_input_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_input_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
reg_mmdp_ctrl_clk_export : out std_logic; -- export
reg_mmdp_ctrl_read_export : out std_logic; -- export
@@ -351,13 +358,6 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
reg_nw_10gbe_mac_reset_export : out std_logic; -- export
reg_nw_10gbe_mac_write_export : out std_logic; -- export
reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_output_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_output_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_output_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bsn_align_output_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_output_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_output_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
reg_remu_clk_export : out std_logic; -- export
reg_remu_read_export : out std_logic; -- export
@@ -437,14 +437,14 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_tr_10gbe_mac_reset_export : out std_logic; -- export
reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
reg_tr_10gbe_mac_write_export : out std_logic; -- export
reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_tr_10gbe_mac_read_export : out std_logic; -- export
@@ -479,6 +479,5 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2c_sdp_station;
-
END qsys_lofar2_unb2c_sdp_station_pkg;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index 65ff3452cc..35dd7db50e 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -274,7 +274,7 @@ BEGIN
-- for dp_bsn_align_v2
g_nof_streams => g_P_sq,
g_bsn_latency_max => 2,
- g_nof_aligners_max => c_sdp_N_pn_max,
+ g_nof_aligners_max => 1, -- 1 for Access scheme 3.
g_block_size => c_block_size,
g_data_w => c_data_w,
g_use_mm_output => TRUE,
@@ -302,8 +302,6 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
- node_index => TO_UINT(gn_id),
-
-- Streaming input
in_sosi_arr => dispatch_sosi_arr,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index a1eede5e5e..9685d5b35c 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -109,6 +109,7 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_W_bf_weight : NATURAL := 16; -- = w in s(w, p), s = signed
CONSTANT c_sdp_W_bf_weight_fraction : NATURAL := 14; -- = p in s(w, p)
CONSTANT c_sdp_W_bf_weight_magnitude : NATURAL := c_sdp_W_bf_weight - c_sdp_W_bf_weight_fraction - 1; -- = 1
+ CONSTANT c_sdp_N_ring_mac : NATURAL := 3; -- for sdp_station_xsub_ring design.
-- Derived constants
CONSTANT c_sdp_FS_adc : NATURAL := 2**(c_sdp_W_adc - 1); -- full scale FS corresponds to amplitude 1.0
@@ -494,8 +495,8 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_reg_dp_block_validate_err_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 4;
CONSTANT c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 2;
CONSTANT c_sdp_reg_ring_info_addr_w : NATURAL := 2;
- CONSTANT c_sdp_reg_tr_10GbE_mac_addr_w : NATURAL := 13;
- CONSTANT c_sdp_reg_tr_10GbE_eth10g_addr_w : NATURAL := 1;
+ CONSTANT c_sdp_reg_tr_10GbE_mac_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_mac) + 13;
+ CONSTANT c_sdp_reg_tr_10GbE_eth10g_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_mac) + 1;
CONSTANT c_sdp_reg_diag_bg_addr_w : NATURAL := 3;
CONSTANT c_sdp_ram_diag_bg_addr_w : NATURAL := 7;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index 17c93d891f..56b49e0e1c 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -254,6 +254,7 @@ BEGIN
-- No need to transfer eop counter across clock domains for single clock
ELSE
wr_eop_busy <= '0'; -- To prevent inferred latch.
+ wr_eop_new <= '0'; -- To prevent inferred latch.
IF snk_in.eop = '1' THEN
wr_eop_cnt <= 1; -- wr_eop_cnt can simply be set to 1 instead of counting as it is immidiatly processed due to having a single clock.
ELSE
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
index fa7196f732..fab924bab0 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
@@ -846,21 +846,21 @@ PACKAGE tech_10gbase_r_component_pkg IS
component ip_arria10_e1sg_phy_10gbase_r_3 is
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- read
- reconfig_address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- write
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- read
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => '0'); -- address
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata
reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
reconfig_waitrequest : out std_logic_vector(0 downto 0); -- waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset
- rx_analogreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_analogreset
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- clk
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reset
+ rx_analogreset : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_analogreset
rx_cal_busy : out std_logic_vector(2 downto 0); -- rx_cal_busy
- rx_cdr_refclk0 : in std_logic := 'X'; -- clk
+ rx_cdr_refclk0 : in std_logic := '0'; -- clk
rx_clkout : out std_logic_vector(2 downto 0); -- clk
rx_control : out std_logic_vector(23 downto 0); -- rx_control
- rx_coreclkin : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
- rx_digitalreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_coreclkin : in std_logic_vector(2 downto 0) := (others => '0'); -- clk
+ rx_digitalreset : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_digitalreset
rx_enh_blk_lock : out std_logic_vector(2 downto 0); -- rx_enh_blk_lock
rx_enh_data_valid : out std_logic_vector(2 downto 0); -- rx_enh_data_valid
rx_enh_fifo_del : out std_logic_vector(2 downto 0); -- rx_enh_fifo_del
@@ -873,28 +873,28 @@ PACKAGE tech_10gbase_r_component_pkg IS
rx_parallel_data : out std_logic_vector(191 downto 0); -- rx_parallel_data
rx_prbs_done : out std_logic_vector(2 downto 0); -- rx_prbs_done
rx_prbs_err : out std_logic_vector(2 downto 0); -- rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_serial_data
- rx_seriallpbken : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_seriallpbken
- tx_analogreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_analogreset
+ rx_prbs_err_clr : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_prbs_err_clr
+ rx_serial_data : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_serial_data
+ rx_seriallpbken : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_seriallpbken
+ tx_analogreset : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_analogreset
tx_cal_busy : out std_logic_vector(2 downto 0); -- tx_cal_busy
tx_clkout : out std_logic_vector(2 downto 0); -- clk
- tx_control : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_control
- tx_coreclkin : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
- tx_digitalreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_enh_data_valid
+ tx_control : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_control
+ tx_coreclkin : in std_logic_vector(2 downto 0) := (others => '0'); -- clk
+ tx_digitalreset : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_digitalreset
+ tx_enh_data_valid : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_enh_data_valid
tx_enh_fifo_empty : out std_logic_vector(2 downto 0); -- tx_enh_fifo_empty
tx_enh_fifo_full : out std_logic_vector(2 downto 0); -- tx_enh_fifo_full
tx_enh_fifo_pempty : out std_logic_vector(2 downto 0); -- tx_enh_fifo_pempty
tx_enh_fifo_pfull : out std_logic_vector(2 downto 0); -- tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_err_ins
- tx_parallel_data : in std_logic_vector(191 downto 0) := (others => 'X'); -- tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
+ tx_err_ins : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_err_ins
+ tx_parallel_data : in std_logic_vector(191 downto 0) := (others => '0'); -- tx_parallel_data
+ tx_serial_clk0 : in std_logic_vector(2 downto 0) := (others => '0'); -- clk
tx_serial_data : out std_logic_vector(2 downto 0); -- tx_serial_data
unused_rx_control : out std_logic_vector(35 downto 0); -- unused_rx_control
unused_rx_parallel_data : out std_logic_vector(191 downto 0); -- unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(26 downto 0) := (others => 'X'); -- unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(191 downto 0) := (others => 'X') -- unused_tx_parallel_data
+ unused_tx_control : in std_logic_vector(26 downto 0) := (others => '0'); -- unused_tx_control
+ unused_tx_parallel_data : in std_logic_vector(191 downto 0) := (others => '0') -- unused_tx_parallel_data
);
end component ip_arria10_e1sg_phy_10gbase_r_3;
@@ -1162,18 +1162,18 @@ PACKAGE tech_10gbase_r_component_pkg IS
component ip_arria10_e1sg_transceiver_reset_controller_3 is
port (
- clock : in std_logic := 'X'; -- clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ clock : in std_logic := '0'; -- clk
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
- reset : in std_logic := 'X'; -- reset
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select
+ reset : in std_logic := '0'; -- reset
rx_analogreset : out std_logic_vector(2 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_cal_busy
+ rx_cal_busy : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_cal_busy
rx_digitalreset : out std_logic_vector(2 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_is_lockedtodata
rx_ready : out std_logic_vector(2 downto 0); -- rx_ready
tx_analogreset : out std_logic_vector(2 downto 0); -- tx_analogreset
- tx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_cal_busy
+ tx_cal_busy : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_cal_busy
tx_digitalreset : out std_logic_vector(2 downto 0); -- tx_digitalreset
tx_ready : out std_logic_vector(2 downto 0) -- tx_ready
);
@@ -1307,21 +1307,21 @@ PACKAGE tech_10gbase_r_component_pkg IS
component ip_arria10_e2sg_phy_10gbase_r_3 is
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- read
- reconfig_address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- write
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- read
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => '0'); -- address
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata
reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
reconfig_waitrequest : out std_logic_vector(0 downto 0); -- waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset
- rx_analogreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_analogreset
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- clk
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reset
+ rx_analogreset : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_analogreset
rx_cal_busy : out std_logic_vector(2 downto 0); -- rx_cal_busy
- rx_cdr_refclk0 : in std_logic := 'X'; -- clk
+ rx_cdr_refclk0 : in std_logic := '0'; -- clk
rx_clkout : out std_logic_vector(2 downto 0); -- clk
rx_control : out std_logic_vector(23 downto 0); -- rx_control
- rx_coreclkin : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
- rx_digitalreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_coreclkin : in std_logic_vector(2 downto 0) := (others => '0'); -- clk
+ rx_digitalreset : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_digitalreset
rx_enh_blk_lock : out std_logic_vector(2 downto 0); -- rx_enh_blk_lock
rx_enh_data_valid : out std_logic_vector(2 downto 0); -- rx_enh_data_valid
rx_enh_fifo_del : out std_logic_vector(2 downto 0); -- rx_enh_fifo_del
@@ -1334,28 +1334,28 @@ PACKAGE tech_10gbase_r_component_pkg IS
rx_parallel_data : out std_logic_vector(191 downto 0); -- rx_parallel_data
rx_prbs_done : out std_logic_vector(2 downto 0); -- rx_prbs_done
rx_prbs_err : out std_logic_vector(2 downto 0); -- rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_serial_data
- rx_seriallpbken : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_seriallpbken
- tx_analogreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_analogreset
+ rx_prbs_err_clr : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_prbs_err_clr
+ rx_serial_data : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_serial_data
+ rx_seriallpbken : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_seriallpbken
+ tx_analogreset : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_analogreset
tx_cal_busy : out std_logic_vector(2 downto 0); -- tx_cal_busy
tx_clkout : out std_logic_vector(2 downto 0); -- clk
- tx_control : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_control
- tx_coreclkin : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
- tx_digitalreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_enh_data_valid
+ tx_control : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_control
+ tx_coreclkin : in std_logic_vector(2 downto 0) := (others => '0'); -- clk
+ tx_digitalreset : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_digitalreset
+ tx_enh_data_valid : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_enh_data_valid
tx_enh_fifo_empty : out std_logic_vector(2 downto 0); -- tx_enh_fifo_empty
tx_enh_fifo_full : out std_logic_vector(2 downto 0); -- tx_enh_fifo_full
tx_enh_fifo_pempty : out std_logic_vector(2 downto 0); -- tx_enh_fifo_pempty
tx_enh_fifo_pfull : out std_logic_vector(2 downto 0); -- tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_err_ins
- tx_parallel_data : in std_logic_vector(191 downto 0) := (others => 'X'); -- tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
+ tx_err_ins : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_err_ins
+ tx_parallel_data : in std_logic_vector(191 downto 0) := (others => '0'); -- tx_parallel_data
+ tx_serial_clk0 : in std_logic_vector(2 downto 0) := (others => '0'); -- clk
tx_serial_data : out std_logic_vector(2 downto 0); -- tx_serial_data
unused_rx_control : out std_logic_vector(35 downto 0); -- unused_rx_control
unused_rx_parallel_data : out std_logic_vector(191 downto 0); -- unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(26 downto 0) := (others => 'X'); -- unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(191 downto 0) := (others => 'X') -- unused_tx_parallel_data
+ unused_tx_control : in std_logic_vector(26 downto 0) := (others => '0'); -- unused_tx_control
+ unused_tx_parallel_data : in std_logic_vector(191 downto 0) := (others => '0') -- unused_tx_parallel_data
);
end component;
@@ -1623,18 +1623,18 @@ PACKAGE tech_10gbase_r_component_pkg IS
component ip_arria10_e2sg_transceiver_reset_controller_3 is
port (
- clock : in std_logic := 'X'; -- clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ clock : in std_logic := '0'; -- clk
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
- reset : in std_logic := 'X'; -- reset
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select
+ reset : in std_logic := '0'; -- reset
rx_analogreset : out std_logic_vector(2 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_cal_busy
+ rx_cal_busy : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_cal_busy
rx_digitalreset : out std_logic_vector(2 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_is_lockedtodata
rx_ready : out std_logic_vector(2 downto 0); -- rx_ready
tx_analogreset : out std_logic_vector(2 downto 0); -- tx_analogreset
- tx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_cal_busy
+ tx_cal_busy : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_cal_busy
tx_digitalreset : out std_logic_vector(2 downto 0); -- tx_digitalreset
tx_ready : out std_logic_vector(2 downto 0) -- tx_ready
);
--
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