From 4ad339fb6abe2d68aabb9918ddd24debafc41c72 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 16 Oct 2015 11:50:50 +0000
Subject: [PATCH] SVN copied common_pulser.vhd to RadioHDL.

---
 libraries/base/common/hdllib.cfg              |  4 +-
 .../base/common/src/vhdl/common_pulser.vhd    | 90 +++++++++++++++++++
 2 files changed, 92 insertions(+), 2 deletions(-)
 create mode 100644 libraries/base/common/src/vhdl/common_pulser.vhd

diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
index 6460fa6d67..e29770930a 100644
--- a/libraries/base/common/hdllib.cfg
+++ b/libraries/base/common/hdllib.cfg
@@ -68,9 +68,9 @@ synth_files =
     $UNB/Firmware/modules/common/src/vhdl/common_spulse.vhd
     $UNB/Firmware/modules/common/src/vhdl/common_counter.vhd
     $UNB/Firmware/modules/common/src/vhdl/common_init.vhd
-    $UNB/Firmware/modules/common/src/vhdl/common_pulser.vhd
-    src/vhdl/common_led_controller.vhd
+    src/vhdl/common_pulser.vhd
     src/vhdl/common_pulser_us_ms_s.vhd
+    src/vhdl/common_led_controller.vhd
     $UNB/Firmware/modules/common/src/vhdl/common_debounce.vhd
     $UNB/Firmware/modules/common/src/vhdl/common_frame_busy.vhd
     $UNB/Firmware/modules/common/src/vhdl/common_stable_delayed.vhd
diff --git a/libraries/base/common/src/vhdl/common_pulser.vhd b/libraries/base/common/src/vhdl/common_pulser.vhd
new file mode 100644
index 0000000000..019ef371cf
--- /dev/null
+++ b/libraries/base/common/src/vhdl/common_pulser.vhd
@@ -0,0 +1,90 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+
+-- Purpose: Output a one cycle pulse every period
+-- Description:
+--   The pulse period can dynamically be set via the input pulse_period.
+--   Default pulse_period = g_pulse_period, to also support static setting of
+--   the pulse period. The pulse_clr can be used to synchronise the pulser.
+ENTITY common_pulser IS
+  GENERIC (
+    g_pulse_period : NATURAL := 25000  -- nof clk cycles to get pulse period
+  );
+  PORT (
+    rst            : IN  STD_LOGIC;
+    clk            : IN  STD_LOGIC;
+    clken          : IN  STD_LOGIC := '1';  -- support running on clken freq
+    pulse_period   : IN  STD_LOGIC_VECTOR(ceil_log2(g_pulse_period+1)-1 DOWNTO 0) := TO_UVEC(g_pulse_period, ceil_log2(g_pulse_period+1));
+    pulse_en       : IN  STD_LOGIC := '1';  -- enable the pulse interval timer
+    pulse_clr      : IN  STD_LOGIC := '0';  -- restart the pulse interval timer
+    pulse_out      : OUT STD_LOGIC
+  );
+END common_pulser;
+
+
+ARCHITECTURE rtl OF common_pulser IS
+
+  CONSTANT c_pulse_period_w  : NATURAL := ceil_log2(g_pulse_period+1);
+  
+  SIGNAL cnt           : STD_LOGIC_VECTOR(c_pulse_period_w-1 DOWNTO 0) := (OTHERS=>'0');
+  SIGNAL cnt_en        : STD_LOGIC;
+  SIGNAL cnt_clr       : STD_LOGIC;
+  SIGNAL cnt_period    : STD_LOGIC;
+  
+BEGIN
+
+  p_clk : PROCESS(clk, rst)
+  BEGIN
+    IF rst='1' THEN
+      pulse_out <= '0';
+    ELSIF rising_edge(clk) THEN
+      IF clken='1' THEN
+        pulse_out <= cnt_period;
+      END IF;
+    END IF;
+  END PROCESS;
+
+  -- pulse period counter
+  cnt_period <= '1' WHEN pulse_en='1' AND UNSIGNED(cnt)=UNSIGNED(pulse_period)-1 ELSE '0';  
+  
+  cnt_en     <= pulse_en;
+  cnt_clr    <= pulse_clr OR cnt_period;
+  
+  u_cnt : ENTITY common_lib.common_counter
+  GENERIC MAP (
+    g_width     => c_pulse_period_w
+  )
+  PORT MAP (
+    rst     => rst,
+    clk     => clk,
+    clken   => clken,
+    cnt_clr => cnt_clr,
+    cnt_en  => cnt_en,
+    count   => cnt
+  );
+  
+END rtl;
-- 
GitLab