From 4ac97b5ed0816520e2e13983eb2c8726758b06b2 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Tue, 23 May 2023 16:23:49 +0200
Subject: [PATCH] Clarified MM port for io_ddr.vhd + io_ddr_reg.vhd.
---
libraries/io/ddr/ddr.peripheral.yaml | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/libraries/io/ddr/ddr.peripheral.yaml b/libraries/io/ddr/ddr.peripheral.yaml
index 98a9f8b2e2..25d432dfd9 100644
--- a/libraries/io/ddr/ddr.peripheral.yaml
+++ b/libraries/io/ddr/ddr.peripheral.yaml
@@ -9,13 +9,14 @@ peripherals:
- peripheral_name: io_ddr # pi_io_ddr.py
peripheral_description: "DDR controller"
mm_ports:
- # MM port for io_ddr_reg.vhd
+ # MM port for io_ddr.vhd + io_ddr_reg.vhd
- mm_port_name: REG_IO_DDR
mm_port_type: REG
mm_port_span: 8 * MM_BUS_SIZE
mm_port_description: "DDR controller registers."
number_of_mm_ports: 1
fields:
+ # Register part of io_ddr.vhd for status of DDR4 interface
- - field_name: reg_io_ddr
field_description: |
"IO DDR status bits concatenated:
@@ -34,9 +35,10 @@ peripherals:
address_offset: 2 * MM_BUS_SIZE
access_mode: RO
- - field_name: reg_fifo_full
- field_description: "Read FIFO full bit & Write FIFO full bit"
+ field_description: "Read FIFO full bit & Write FIFO full bit, read both bits together because they get cleared upon read"
address_offset: 3 * MM_BUS_SIZE
access_mode: RO
+ # Register part of io_ddr_reg.vhd used in mms_io_ddr.vhd for write and read access to DDR memory via MM
- - field_name: reg_burstbegin
field_description: "Start write or read access to DDR when reg_burstbegin = 1."
address_offset: 8 * MM_BUS_SIZE
@@ -60,7 +62,7 @@ peripherals:
- - field_name: reg_flush
field_description: |
"Flush the write FIFO
- The user input to the write FIFO sohuld be off. Internally the method waits sufficient us to
+ The user input to the write FIFO should be off. Internally the method waits sufficient us to
ensure that the write FIFO is read empty."
address_offset: 15 * MM_BUS_SIZE
--
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