diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
index b9e7e59011f2f8c712d115364a3abc7d8a1c2e44..383e7956da49c6c8c6c2f0cc8627c03896cd324d 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
@@ -67,6 +67,10 @@ ENTITY unb2_test_all IS
SB_CLK : IN STD_LOGIC; -- Clock 10GbE back upper 24 lines
BCK_REF_CLK : IN STD_LOGIC; -- Clock 10GbE back lower 24 lines
+ -- DDR reference clocks
+ MB_I_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_I
+ MB_II_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_II
+
-- back transceivers
BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
@@ -156,6 +160,10 @@ BEGIN
SB_CLK => SB_CLK,
BCK_REF_CLK => BCK_REF_CLK,
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
-- back transceivers
BCK_RX => BCK_RX,
BCK_TX => BCK_TX,
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/unb2_test_ddr.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/unb2_test_ddr.vhd
index 1d0a58989c050eb5b9387cf78a6f347e34e4f4e4..a7ea8386df61437665b2ba4c4bb7354b884dc5ce 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/unb2_test_ddr.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/unb2_test_ddr.vhd
@@ -62,6 +62,10 @@ ENTITY unb2_test_ddr IS
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+ -- DDR reference clocks
+ MB_I_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_I
+ MB_II_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_II
+
-- SO-DIMM Memory Bank I
MB_I_IN : IN t_tech_ddr4_phy_in;
MB_I_IO : INOUT t_tech_ddr4_phy_io;
@@ -113,6 +117,10 @@ BEGIN
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
-- SO-DIMM Memory Bank I
MB_I_IN => MB_I_IN,
MB_I_IO => MB_I_IO,
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 87a2029fc5442233643a309a035451b95e80f594..366a2971a27df64f7342547f7e1de375112439be 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -79,6 +79,10 @@ ENTITY unb2_test IS
SB_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE back upper 24 lines
BCK_REF_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE back lower 24 lines
+ -- DDR reference clocks
+ MB_I_REF_CLK : IN STD_LOGIC := '0'; -- Reference clock for MB_I
+ MB_II_REF_CLK : IN STD_LOGIC := '0'; -- Reference clock for MB_II
+
-- back transceivers
--BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0) := (OTHERS=>'0');
--BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
@@ -114,13 +118,11 @@ ENTITY unb2_test IS
QSFP_RST : INOUT STD_LOGIC;
-- SO-DIMM Memory Bank I
- -- FIXME: verify/edit quartus pinning list to conform t_tech_ddr4_phy_in,t_tech_ddr4_phy_io,t_tech_ddr4_phy_ou records defined in technology/ddr/tech_ddr_pkg.vhd
MB_I_IN : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
MB_I_IO : INOUT t_tech_ddr4_phy_io;
MB_I_OU : OUT t_tech_ddr4_phy_ou;
-- SO-DIMM Memory Bank II
- -- FIXME: verify/edit quartus pinning list to conform t_tech_ddr4_phy_in,t_tech_ddr4_phy_io,t_tech_ddr4_phy_ou records defined in technology/ddr/tech_ddr_pkg.vhd
MB_II_IN : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
MB_II_IO : INOUT t_tech_ddr4_phy_io;
MB_II_OU : OUT t_tech_ddr4_phy_ou;
@@ -217,6 +219,9 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL SA_CLK_buf : STD_LOGIC;
+ SIGNAL mb_I_ref_rst : STD_LOGIC;
+ SIGNAL mb_II_ref_rst : STD_LOGIC;
+
SIGNAL ddr_I_clk200 : STD_LOGIC;
SIGNAL ddr_I_rst200 : STD_LOGIC;
SIGNAL ddr_II_clk200 : STD_LOGIC;
@@ -955,9 +960,9 @@ BEGIN
-- IO_DDR
---------------------------------------------------------------------------
-- DDR reference clock
- ctlr_ref_clk => ext_clk200,
- ctlr_ref_rst => ext_rst200,
-
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+
-- DDR controller clock domain
ctlr_clk_out => ddr_I_clk200,
ctlr_rst_out => ddr_I_rst200,
diff --git a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
index 85e5b0f46c282c501ceedaa01055156d08df631c..7c3260bcaf28b4a35fdb7e71372d73aafa66deba 100644
--- a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2012
+-- Copyright (C) 2012-2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -55,8 +55,6 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY tb_unb2_test IS
GENERIC (
g_design_name : STRING := "unb2_test";
- g_sim_unb_nr : NATURAL := 0; -- UniBoard 0
- g_sim_node_nr : NATURAL := 3; -- Node 3
g_sim_model_ddr : BOOLEAN := FALSE
);
END tb_unb2_test;
@@ -75,13 +73,15 @@ ARCHITECTURE tb OF tb_unb2_test IS
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 0);
- CONSTANT c_cable_delay : TIME := 12 ns;
- CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
- CONSTANT c_clk_period : TIME := 5 ns;
- CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644 MHz
- CONSTANT c_sb_clk_period : TIME := tech_pll_clk_644_period; -- 644 MHz
- CONSTANT c_bck_ref_clk_period : TIME := tech_pll_clk_644_period; -- 644 MHz
- CONSTANT c_pps_period : NATURAL := 1000;
+ CONSTANT c_cable_delay : TIME := 12 ns;
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_clk_period : TIME := 5 ns;
+ CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644 MHz
+ CONSTANT c_sb_clk_period : TIME := tech_pll_clk_644_period; -- 644 MHz
+ CONSTANT c_bck_ref_clk_period : TIME := tech_pll_clk_644_period; -- 644 MHz
+ CONSTANT c_mb_I_ref_clk_period : TIME := 40 ns; -- 25 MHz
+ CONSTANT c_mb_II_ref_clk_period : TIME := 40 ns; -- 25 MHz
+ CONSTANT c_pps_period : NATURAL := 1000;
-- DUT
SIGNAL clk : STD_LOGIC := '0';
@@ -105,6 +105,10 @@ ARCHITECTURE tb OF tb_unb2_test IS
SIGNAL qsfp_led : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+ -- DDR reference clocks
+ SIGNAL mb_I_ref_clk : STD_LOGIC := '1'; -- Reference clock for MB_I
+ SIGNAL mb_II_ref_clk : STD_LOGIC := '1'; -- Reference clock for MB_II
+
-- DDR4 PHY interface
SIGNAL MB_I_IN : t_tech_ddr4_phy_in;
SIGNAL MB_I_IO : t_tech_ddr4_phy_io;
@@ -150,11 +154,13 @@ BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
- sa_clk <= NOT sa_clk AFTER c_sa_clk_period/2; -- sa clock (644 MHz)
- sb_clk <= NOT sb_clk AFTER c_sb_clk_period/2; -- sb clock (644 MHz)
- bck_ref_clk <= NOT bck_ref_clk AFTER c_bck_ref_clk_period/2; -- bck_ref clock (644 MHz)
+ clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ sa_clk <= NOT sa_clk AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+ sb_clk <= NOT sb_clk AFTER c_sb_clk_period/2; -- Serial Gigabit IO sb clock (644 MHz)
+ bck_ref_clk <= NOT bck_ref_clk AFTER c_bck_ref_clk_period/2; -- Serial Gigabit IO bck_ref clock (644 MHz)
+ mb_I_ref_clk <= NOT mb_I_ref_clk AFTER c_mb_I_ref_clk_period/2; -- MB I reference clock (25 MHz)
+ mb_II_ref_clk <= NOT mb_II_ref_clk AFTER c_mb_II_ref_clk_period/2; -- MB II reference clock (25 MHz)
INTA <= 'H'; -- pull up
@@ -216,6 +222,10 @@ BEGIN
SB_CLK => sb_clk,
BCK_REF_CLK => bck_ref_clk,
+ -- DDR reference clocks
+ MB_I_REF_CLK => mb_I_ref_clk,
+ MB_II_REF_CLK => mb_II_ref_clk,
+
PMBUS_ALERT => '0',
-- Serial I/O