From 4a5a2be6208d463cccdefc43b673bc7e65631186 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 12 May 2016 13:40:10 +0000
Subject: [PATCH] Added regression_test_vhdl key, with tb_tech_10gbase_r.vhd
that is not self checking yet and not applicable to unb1.
---
libraries/technology/10gbase_r/hdllib.cfg | 3 +++
.../technology/10gbase_r/tb_tech_10gbase_r.vhd | 13 +++++++++++++
2 files changed, 16 insertions(+)
diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index 4ad799bc9a..cec76fbbab 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -26,6 +26,9 @@ synth_files =
test_bench_files =
tb_tech_10gbase_r.vhd
+regression_test_vhdl =
+ tb_tech_10gbase_r.vhd # no self checking yet
+
[modelsim_project_file]
diff --git a/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd b/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
index 7e08b08c08..aff446ead1 100644
--- a/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
@@ -91,6 +91,19 @@ BEGIN
link_fault <= '0';
WAIT FOR 10 us;
tb_end <= '1';
+
+ WAIT FOR 10 us; -- this line seems necessary to ensure that -label will stop the simulation
+ -- before the FAILURE when p_tb_end is the only process that is still active,
+ -- which is the case for g_technology that do not support the pll and dut.
+ -- Only using 1 us >> tech_pll_clk_644_period in p_tb_end, instead of 1 ns does
+ -- not help to avoid the FAILURE.
+ WAIT;
+ END PROCESS;
+
+ p_tb_end : PROCESS
+ BEGIN
+ WAIT UNTIL tb_end='1';
+ WAIT FOR 1 us;
REPORT "Tb simulation finished." SEVERITY FAILURE;
WAIT;
END PROCESS;
--
GitLab