diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 38214e72d7c3202a66b85fe2fed3e064fda6f004..6af5fab043102e74303bf063f837676da6f99846 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -124,9 +124,7 @@ ARCHITECTURE str OF ddrctrl IS
SIGNAL stop : STD_LOGIC;
SIGNAL rd_fifo_usedw : STD_LOGIC_VECTOR(c_rd_fifo_uw_w-1 DOWNTO 0);
SIGNAL rd_ready : STD_LOGIC;
- SIGNAL inp_ds : NATURAL;
SIGNAL inp_bsn_adr : NATURAL;
- SIGNAL outp_ds : NATURAL;
SIGNAL outp_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
SIGNAL data_stopped : STD_LOGIC;
@@ -153,7 +151,6 @@ BEGIN
in_stop => stop,
out_sosi => out_sosi,
out_adr => out_adr,
- out_bsn_ds => inp_ds,
out_bsn_adr => inp_bsn_adr,
out_data_stopped => data_stopped
);
@@ -247,8 +244,6 @@ BEGIN
rst => rst,
in_sosi => rd_sosi,
- in_ds => outp_ds,
- in_bsn => outp_bsn,
out_sosi_arr => out_sosi_arr,
out_ready => rd_ready
@@ -269,7 +264,8 @@ BEGIN
g_max_adr => c_nof_adr,
g_burstsize => g_burstsize,
g_last_burstsize => c_last_burstsize,
- g_adr_per_b => c_adr_per_b
+ g_adr_per_b => c_adr_per_b,
+ g_bim => c_bim
)
PORT MAP(
clk => clk,
@@ -279,7 +275,6 @@ BEGIN
inp_of => out_of,
inp_sosi => out_sosi,
inp_adr => out_adr,
- inp_ds => inp_ds,
inp_bsn_adr => inp_bsn_adr,
inp_data_stopped => data_stopped,
rst_ddrctrl_input => rst_ddrctrl_input,
@@ -290,10 +285,6 @@ BEGIN
wr_sosi => wr_sosi,
rd_fifo_usedw => rd_fifo_usedw,
- -- ddrctrl_output
- outp_ds => outp_ds,
- outp_bsn => outp_bsn,
-
-- ddrctrl_controller
stop_in => stop_in,
stop_out => stop
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 3f4cab12b7d991c5abd15ddc3fe2030bb5ff222e..3a2b66fd63d8e87508770d7d5902ebff4ec8ae7b 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -50,7 +50,8 @@ ENTITY ddrctrl_controller IS
g_max_adr : NATURAL; -- 16128
g_burstsize : NATURAL; -- 64
g_last_burstsize : NATURAL; -- 18
- g_adr_per_b : NATURAL -- 299
+ g_adr_per_b : NATURAL; -- 299
+ g_bim : NATURAL -- 54
);
PORT (
clk : IN STD_LOGIC;
@@ -60,7 +61,6 @@ ENTITY ddrctrl_controller IS
inp_of : IN NATURAL;
inp_sosi : IN t_dp_sosi;
inp_adr : IN NATURAL;
- inp_ds : IN NATURAL;
inp_bsn_adr : IN NATURAL;
inp_data_stopped : IN STD_LOGIC;
rst_ddrctrl_input : OUT STD_LOGIC;
@@ -72,7 +72,6 @@ ENTITY ddrctrl_controller IS
rd_fifo_usedw : IN STD_LOGIC_VECTOR(g_rd_fifo_uw_w-1 DOWNTO 0);
-- ddrctrl_output
- outp_ds : OUT NATURAL;
outp_bsn : OUT STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS => '0');
-- ddrctrl_controller
@@ -96,7 +95,6 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
CONSTANT c_rest : NATURAL := c_rd_data_w-(g_wr_data_w mod c_rd_data_w); -- 96
CONSTANT c_max_read_cnt : NATURAL := (g_max_adr+1)/g_burstsize; -- 256
CONSTANT c_io_ddr_data_w : NATURAL := func_tech_ddr_ctlr_data_w(g_tech_ddr); -- 576
- CONSTANT c_proportion : NATURAL := (c_io_ddr_data_w/c_rd_data_w)+1;
-- type for statemachine
TYPE t_state IS (RESET, WRITING, SET_STOP, STOP_WRITING, LAST_WRITE_BURST, START_READING, READING, STOP_READING, IDLE);
@@ -119,7 +117,6 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
need_burst : STD_LOGIC;
-- reading signals
- outp_ds : NATURAL;
outp_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
read_cnt : NATURAL;
rd_burst_en : STD_LOGIC;
@@ -129,19 +126,21 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
wr_sosi : t_dp_sosi;
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, '0', '0', TO_UVEC(g_max_adr, c_adr_w), (OTHERS => '0'), 0, '1', '1', '0', 0, (OTHERS => '0'), 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
+ CONSTANT c_t_reg_init : t_reg := (RESET, '0', '0', TO_UVEC(g_max_adr, c_adr_w), (OTHERS => '0'), 0, '1', '1', '0', (OTHERS => '0'), 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
-- signals for readability
SIGNAL d_reg : t_reg := c_t_reg_init;
SIGNAL q_reg : t_reg := c_t_reg_init;
+ SIGNAL s_bim : NATURAL := g_bim;
+
BEGIN
q_reg <= d_reg WHEN rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
- p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr, inp_ds, inp_bsn_adr, inp_data_stopped, dvr_miso, rd_fifo_usedw, stop_in)
+ p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr, inp_bsn_adr, inp_data_stopped, dvr_miso, rd_fifo_usedw, stop_in)
VARIABLE v : t_reg := c_t_reg_init;
@@ -152,10 +151,10 @@ BEGIN
CASE q_reg.state IS
WHEN RESET =>
- v := c_t_reg_init;
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := (OTHERS => '0');
- v.dvr_mosi.wr := '1';
+ v := c_t_reg_init;
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := (OTHERS => '0');
+ v.dvr_mosi.wr := '1';
@@ -279,28 +278,18 @@ BEGIN
WHEN START_READING =>
v.dvr_mosi.burstbegin := '0';
v.rd_burst_en := '1';
- v.outp_ds := inp_ds;
v.read_cnt := 0;
-
- FOR I IN 0 TO inp_bsn_adr+(g_max_adr-TO_UINT(q_reg.stop_adr)) LOOP -- takes a while WRONG, wil be fixed after L2SDP-705, 706 and 70
- IF v.outp_ds-c_rest <= 0 THEN
- v.outp_ds := v.outp_ds+c_rd_data_w-c_rest;
- ELSE
- v.outp_ds := v.outp_ds-c_rest;
- END IF;
- END LOOP;
- v.outp_bsn := TO_UVEC(TO_UINT(inp_sosi.bsn), c_dp_stream_bsn_w); -- WRONG, wil be fixed after L2SDP-705, 706 and 707
- v.state := READING;
+ v.outp_bsn := TO_UVEC(TO_UINT(inp_sosi.bsn)-g_bim, c_dp_stream_bsn_w);
+ v.state := READING;
WHEN READING =>
-- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
- IF TO_UINT(rd_fifo_usedw) <= 10 AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' AND dvr_miso.done = '1' THEN
+ IF TO_UINT(rd_fifo_usedw) <= g_burstsize AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' THEN
v.dvr_mosi.burstbegin := '0';
v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
v.dvr_mosi.wr := '0';
v.dvr_mosi.rd := '1';
- v.outp_ds := inp_ds;
IF TO_UINT(q_reg.stop_adr(c_adr_w-1 DOWNTO 0))+g_burstsize*q_reg.read_cnt >= g_max_adr THEN
v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC((TO_UINT(q_reg.stop_adr(c_adr_w-1 DOWNTO 0))+g_burstsize*q_reg.read_cnt)-g_max_adr-1, c_adr_w);
ELSE
@@ -314,7 +303,7 @@ BEGIN
END IF;
-- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
- IF TO_UINT(rd_fifo_usedw) = 11 THEN
+ IF dvr_miso.done = '0' THEN
v.rd_burst_en := '1';
END IF;
@@ -385,7 +374,6 @@ BEGIN
wr_sosi <= q_reg.wr_sosi;
stop_out <= q_reg.stopped;
outp_bsn <= q_reg.outp_bsn;
- outp_ds <= q_reg.outp_ds;
rst_ddrctrl_input <= q_reg.rst_ddrctrl_input OR rst;
END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
index 208780472a0e4df9cfc607de8f8f3e87e0ffb783..c27c54acd3401cc8996d26e5dcebcd664ab65fb3 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
@@ -59,7 +59,6 @@ ENTITY ddrctrl_input IS
in_stop : IN STD_LOGIC;
out_sosi : OUT t_dp_sosi; -- output data
out_adr : OUT NATURAL;
- out_bsn_ds : OUT NATURAL;
out_bsn_adr : OUT NATURAL;
out_data_stopped : OUT STD_LOGIC
);
@@ -76,7 +75,6 @@ ARCHITECTURE str OF ddrctrl_input IS
SIGNAL sosi_p_rp : t_dp_sosi := c_dp_sosi_init;
SIGNAL sosi_rp_ac : t_dp_sosi := c_dp_sosi_init;
SIGNAL adr : NATURAL := 0;
- SIGNAL bsn_ds : NATURAL := 0;
SIGNAL valid : STD_LOGIC := '0';
SIGNAL data_stopped_rp_ac : STD_LOGIC := '0';
@@ -110,7 +108,6 @@ BEGIN
in_sosi => sosi_p_rp, -- input data
in_stop => in_stop,
out_sosi => sosi_rp_ac, -- output data
- out_bsn_ds => bsn_ds, -- amount of bits between adr [0] and sosi_arr[0][0] where bsn is assigned to
out_data_stopped => data_stopped_rp_ac
);
@@ -124,12 +121,10 @@ BEGIN
clk => clk,
rst => rst,
in_sosi => sosi_rp_ac, -- input data
- in_bsn_ds => bsn_ds,
in_data_stopped => data_stopped_rp_ac,
out_sosi => out_sosi, -- output data
out_adr => adr,
out_bsn_adr => out_bsn_adr,
- out_bsn_ds => out_bsn_ds,
out_data_stopped => out_data_stopped
);
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
index 916bbb2a18196a555303ca81f99dc0f79b188292..1fa66ab59c981b7249f3568a099cde1d3d4c1ba4 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
@@ -48,12 +48,10 @@ ENTITY ddrctrl_input_address_counter IS
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
in_sosi : IN t_dp_sosi; -- input data
- in_bsn_ds : IN NATURAL;
in_data_stopped : IN STD_LOGIC;
out_sosi : OUT t_dp_sosi := c_dp_sosi_init; -- output data
out_adr : OUT NATURAL;
out_bsn_adr : OUT NATURAL;
- out_bsn_ds : OUT NATURAL;
out_data_stopped : OUT STD_LOGIC
);
END ddrctrl_input_address_counter;
@@ -73,15 +71,13 @@ ARCHITECTURE rtl OF ddrctrl_input_address_counter IS
bsn_passed : STD_LOGIC;
out_sosi : t_dp_sosi;
out_bsn_adr : NATURAL;
- out_bsn_ds : NATURAL;
out_data_stopped : STD_LOGIC;
s_in_sosi : t_dp_sosi;
- s_in_bsn_ds : NATURAL;
s_in_data_stopped : STD_LOGIC;
s_adr : NATURAL;
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, '0', c_dp_sosi_init, 0, 0, '0', c_dp_sosi_init, 0, '0', 0);
+ CONSTANT c_t_reg_init : t_reg := (RESET, '0', c_dp_sosi_init, 0, '0', c_dp_sosi_init, '0', 0);
-- signals for readability
@@ -93,7 +89,7 @@ BEGIN
q_reg <= d_reg WHEN rising_edge(clk);
-- Increments the address each time in_sosi.valid = '1', if address = g_max_adr the address is reset to 0.
- p_adr : PROCESS(rst, in_sosi, in_bsn_ds, in_data_stopped, q_reg)
+ p_adr : PROCESS(rst, in_sosi, in_data_stopped, q_reg)
VARIABLE v : t_reg;
@@ -102,10 +98,8 @@ BEGIN
-- compensate for delay in ddrctrl_input_address_counter
v.out_sosi := q_reg.s_in_sosi;
- v.out_bsn_ds := q_reg.s_in_bsn_ds;
v.out_data_stopped := q_reg.s_in_data_stopped;
v.s_in_sosi := in_sosi;
- v.s_in_bsn_ds := in_bsn_ds;
v.s_in_data_stopped := in_data_stopped;
@@ -160,7 +154,6 @@ BEGIN
out_sosi <= q_reg.out_sosi;
out_adr <= q_reg.s_adr;
out_bsn_adr <= q_reg.out_bsn_adr;
- out_bsn_ds <= q_reg.out_bsn_ds;
out_sosi.bsn <= q_reg.out_sosi.bsn;
out_data_stopped <= q_reg.out_data_stopped;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
index 7b7a3ed0d98c5229929b4d25982b3aa41910a258..0a429f473357cbb9bc9b43743d335455e1427949 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
@@ -48,7 +48,6 @@ ENTITY ddrctrl_input_repack IS
in_sosi : IN t_dp_sosi; -- input data
in_stop : IN STD_LOGIC := '0';
out_sosi : OUT t_dp_sosi := c_dp_sosi_init; -- output data
- out_bsn_ds : OUT NATURAL := 0;
out_bsn_wr : OUT STD_LOGIC := '0';
out_data_stopped : OUT STD_LOGIC := '0'
);
@@ -71,17 +70,15 @@ ARCHITECTURE rtl OF ddrctrl_input_repack IS
c_v_count : NATURAL; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
a_of : NATURAL; -- this is the amount of bits that the first data word(168) is shifted from the first bit in the data word(576)
q_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
- q_sop : STD_LOGIC;
- q_out_bsn_ds : NATURAL;
+ q_sop : STD_LOGIC;
s_input_cnt : NATURAL;
out_of : NATURAL;
out_data_count : STD_LOGIC; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
out_sosi : t_dp_sosi; -- this is the sosi stream that contains the data
- out_bsn_ds : NATURAL; -- this is the amount of bits that the data corresponding to out_bsn is shifted from the first bit in that data word
out_data_stopped : STD_LOGIC; -- this signal is '1' when there is no more data comming form ddrctrl_input_pack
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, (OTHERS => '0'), 0, 0, (OTHERS => '0'), '0', 0, 0, 0, '0', c_dp_sosi_init, 0, '0');
+ CONSTANT c_t_reg_init : t_reg := (RESET, (OTHERS => '0'), 0, 0, (OTHERS => '0'), '0', 0, 0, '0', c_dp_sosi_init, '0');
-- signals for readability
@@ -139,7 +136,6 @@ BEGIN
v.out_data_count := '1'; -- increase the counter of out_sosi.data with 1
v.s_input_cnt := q_reg.s_input_cnt+1;
v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := q_reg.q_bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
- v.out_bsn_ds := q_reg.q_out_bsn_ds;
v.out_sosi.sop := q_reg.q_sop;
v.out_sosi.eop := '0';
v.out_data_stopped := '0';
@@ -205,11 +201,6 @@ BEGIN
-- BSN_INPUT
v.q_bsn := in_sosi.bsn; -- a bsn number is saved when the bsn changes
- IF g_in_data_w*q_reg.c_v_count+q_reg.out_of >= c_out_data_w THEN
- v.q_out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w; -- the amount of bits between word[0] and data[0] where data is the data with the bsn
- ELSE
- v.q_out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of; -- the amount of bits between word[0] and data[0] where data is the data with the bsn
- END IF;
v.q_sop := '1'; -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
v.a_of := 0;
v.c_v(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0); -- fill c_v
@@ -270,7 +261,6 @@ BEGIN
-- fill outputs
out_sosi <= q_reg.out_sosi;
- out_bsn_ds <= q_reg.out_bsn_ds;
out_data_stopped <= q_reg.out_data_stopped;
END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
index 7896dad2a2c726a34178cab7509d3d598e2ccbf0..edc789a36a3372b9f4a910beb8ecad45f95ef6d2 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
@@ -52,8 +52,6 @@ ENTITY ddrctrl_output IS
clk : IN STD_LOGIC := '0';
rst : IN STD_LOGIC;
in_sosi : IN t_dp_sosi := c_dp_sosi_init; -- input data
- in_ds : IN NATURAL; -- amount of internal overflow this output
- in_bsn : IN STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0); -- bsn corresponding to the data at in_data[in_of]
out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init); -- output data
out_ready : OUT STD_LOGIC
);
@@ -82,8 +80,6 @@ BEGIN
clk => clk,
rst => rst,
in_sosi => in_sosi, -- input data
- in_ds => in_ds,
- in_bsn => in_bsn,
out_sosi => sosi, -- output data
out_ready => out_ready
);
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
index 823f5e3ec6ae6e3ad0d25bafedd34b46b25af57e..0951666e6b72fe130b415f6a4226727c7b74df60 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
@@ -48,8 +48,6 @@ ENTITY ddrctrl_output_unpack IS
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
in_sosi : IN t_dp_sosi := c_dp_sosi_init;
- in_ds : IN NATURAL;
- in_bsn : IN STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
out_sosi : OUT t_dp_sosi := c_dp_sosi_init;
out_ready : OUT STD_LOGIC := '0'
);
@@ -87,7 +85,7 @@ BEGIN
q_reg <= d_reg WHEN rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
- p_state : PROCESS(q_reg, rst, in_sosi, in_ds, in_bsn)
+ p_state : PROCESS(q_reg, rst, in_sosi)
VARIABLE v : t_reg;
@@ -165,7 +163,7 @@ BEGIN
v.dd_fresh := '0';
v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := v.c_v(g_out_data_w+v.a_of-1 DOWNTO v.a_of);
v.out_sosi.valid := '1';
- v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := in_bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
+ v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
IF in_sosi.valid = '1' THEN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 422c72f091f333e4dc5d57da568da322917e21c5..9c0675b7390f6d6e061a3cfd3804a8ad65f9a817 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -59,7 +59,7 @@ ARCHITECTURE tb OF tb_ddrctrl IS
-- constants for readability
CONSTANT c_ctrl_data_w : NATURAL := func_tech_ddr_ctlr_data_w(c_tech_ddr); -- 576
- CONSTANT c_in_data_w : NATURAL := g_nof_streams * g_data_w; -- output data with, 168
+ CONSTANT c_in_data_w : NATURAL := g_nof_streams*g_data_w; -- output data with, 168
-- constants for testbench
CONSTANT c_clk_freq : NATURAL := 200; -- clock frequency in MHz
@@ -176,7 +176,7 @@ BEGIN
-- wr fifo has delay of 4 clockcylces after reset
-- filling the input data vectors with the corresponding numbers
- run_multiple_times : FOR K in 0 TO 3 LOOP
+ run_multiple_times : FOR K in 0 TO 1 LOOP
make_data : FOR J IN 0 TO c_bim*g_block_size-1 LOOP
in_data_cnt <= in_data_cnt+1;
fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP
@@ -202,7 +202,7 @@ BEGIN
END LOOP;
END IF;
END LOOP;
- IF K = 1 AND J = c_bim*g_block_size-1 THEN
+ IF K = 0 AND J = c_bim*g_block_size-1 THEN
stop_in <= '1';
ELSE
stop_in <= '0';