diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/control_if/1/control_if.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/control_if/1/control_if.vhd
index 970a05f0e5c01a313d5cefa06ac470a711526551..da9db70dd741abff1dd7c4c85399be892977ccb7 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/control_if/1/control_if.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/control_if/1/control_if.vhd
@@ -19,7 +19,7 @@ entity control_if is
 		RST      : in  std_logic;
 		CLK      : in  std_logic;
 		PARAM_LD : out std_logic;
-		PARAM_DT : out std_logic_vector((QUANT-1) downto 0);
+		PARAM_DT : out std_logic_vector((32-1) downto 0);
 		--
 		PARAMETERS_IN_LD : in std_logic;
 		PARAMETERS_IN    : in  std_logic_vector((QUANT-1) downto 0)
@@ -31,7 +31,7 @@ architecture fsl_test of control_if is
 
 	signal sl_RST  : std_logic;
 	signal sl_load : std_logic;
-	signal sl_data : std_logic_vector((QUANT-1) downto 0);
+	signal sl_data : std_logic_vector((32-1) downto 0);
 
 begin
 
@@ -49,7 +49,7 @@ begin
 				else
 					if (PARAMETERS_IN_LD='1') then
 						sl_load <= '1';
-						sl_data <= PARAMETERS_IN((QUANT-1) downto 0);
+						sl_data <= PARAMETERS_IN((32-1) downto 0);
 					end if;
 				end if;
 			end if;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1.vhd
index c6041567ddde212dc7586ab8f9e15699ae6f1c90..b6b3e6533a8afb47ba7a7c84e2b99bf97f52d43b 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1.vhd
@@ -11,7 +11,7 @@ use work.hw_node_pkg.all;
 entity ipcore2RTL_hwn_nd_1 is
    generic (
       RESET_HIGH : natural := 1;
-      PAR_WIDTH  : natural := 16;
+      PAR_WIDTH  : natural := 32;
       QUANT      : natural := 32;
       WRAP       : boolean := true
    );
@@ -63,9 +63,9 @@ architecture RTL of ipcore2RTL_hwn_nd_1 is
    constant c_STAGES       : natural := 1; -- number of pipeline stages or delay
    constant c_IP_RESET     : natural := 1; -- active level of the HW IP reset signal
    constant c_WRAP         : boolean := true; -- Operation mode: Single_Shot (false) or Continuous (true)
-   constant c_PAR_NUMBER   : natural := 0; -- number of global parameters
-   constant c_N_PAR        : natural := 0; -- indicates if parameters are used (1) or not (0)
-   constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
+   constant c_PAR_NUMBER   : natural := 1; -- number of global parameters
+   constant c_N_PAR        : natural := 1; -- indicates if parameters are used (1) or not (0)
+   constant c_PAR_BITWIDTH : natural := 32; -- aggregate bitwidth of the parameter vector
    constant c_PAR_VECTOR   : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
        (0,0,0,0), (0,0,0,0)    -- two dummy elements
    );
@@ -85,7 +85,7 @@ architecture RTL of ipcore2RTL_hwn_nd_1 is
       port (
          RST           : in  std_logic;
          CLK           : in  std_logic;
-         PARAMETERS    : in  std_logic_vector(0 downto 0); 
+         PARAMETERS    : in  std_logic_vector(31 downto 0); 
          REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
          READ_EN       : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
          READ_ST       : in  std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
@@ -136,7 +136,7 @@ architecture RTL of ipcore2RTL_hwn_nd_1 is
       port (
          RST           : in  std_logic;
          CLK           : in  std_logic;
-         PARAMETERS    : in  std_logic_vector(0 downto 0); 
+         PARAMETERS    : in  std_logic_vector(31 downto 0); 
          WRITE_EN      : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
          WRITE_ST      : in  std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
          HALT          : in  std_logic;
@@ -213,7 +213,7 @@ architecture RTL of ipcore2RTL_hwn_nd_1 is
          PARAM_DT   : in  std_logic_vector(PAR_WIDTH-1 downto 0);
          PARAM_LD   : in  std_logic;
 
-         PARAMETERS : out std_logic_vector(0 downto 0)
+         PARAMETERS : out std_logic_vector(31 downto 0)
       );
    end component;
 
@@ -270,7 +270,7 @@ architecture RTL of ipcore2RTL_hwn_nd_1 is
 
    --  
    -- Parameter related signals 
-   signal sl_parameters       : std_logic_vector(0 downto 0);
+   signal sl_parameters       : std_logic_vector(31 downto 0);
 
    signal sl_RST : std_logic;
 
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd
index 409d1e5dd8341d580f66ae531f3e74b391234b7c..9ffe6c0a5e1b98cfa97c0ae9c203337b6330d418 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd
@@ -18,7 +18,7 @@ entity ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1 is
    port (
       RST           : in  std_logic;
       CLK           : in  std_logic;
-      PARAMETERS    : in  std_logic_vector(0 downto 0); 
+      PARAMETERS    : in  std_logic_vector(31 downto 0); 
       REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
       READ_EN       : out std_logic_vector(0 downto 0);
       READ_ST       : in  std_logic_vector(0 downto 0);
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd
index a2c87e6749830963663cc0287c606ae26b6c5ba7..9b4dc4d69b77c81f7ff0350d5ee984e21ccfb271 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd
@@ -18,7 +18,7 @@ entity ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1 is
    port (
       RST           : in  std_logic;
       CLK           : in  std_logic;
-      PARAMETERS    : in  std_logic_vector(0 downto 0); 
+      PARAMETERS    : in  std_logic_vector(31 downto 0); 
       WRITE_EN      : out std_logic_vector(0 downto 0);
       WRITE_ST      : in  std_logic_vector(0 downto 0);
       HALT          : in  std_logic;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2.vhd
index e842e8cb6e4b45fecd886d4fcbd730d4a2607fa3..9b2433bab9e4ba7b8e9630895897c75d4f99505e 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2.vhd
@@ -64,9 +64,9 @@ architecture RTL of ipcore2RTL_hwn_nd_2 is
    constant c_STAGES       : natural := 1; -- number of pipeline stages or delay
    constant c_IP_RESET     : natural := 1; -- active level of the HW IP reset signal
    constant c_WRAP         : boolean := true; -- Operation mode: Single_Shot (false) or Continuous (true)
-   constant c_PAR_NUMBER   : natural := 0; -- number of global parameters
-   constant c_N_PAR        : natural := 0; -- indicates if parameters are used (1) or not (0)
-   constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
+   constant c_PAR_NUMBER   : natural := 1; -- number of global parameters
+   constant c_N_PAR        : natural := 1; -- indicates if parameters are used (1) or not (0)
+   constant c_PAR_BITWIDTH : natural := 32; -- aggregate bitwidth of the parameter vector
    constant c_PAR_VECTOR   : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
        (0,0,0,0), (0,0,0,0)    -- two dummy elements
    );
@@ -86,7 +86,7 @@ architecture RTL of ipcore2RTL_hwn_nd_2 is
       port (
          RST           : in  std_logic;
          CLK           : in  std_logic;
-         PARAMETERS    : in  std_logic_vector(0 downto 0); 
+         PARAMETERS    : in  std_logic_vector(31 downto 0); 
          REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
          READ_EN       : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
          READ_ST       : in  std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
@@ -137,7 +137,7 @@ architecture RTL of ipcore2RTL_hwn_nd_2 is
       port (
          RST           : in  std_logic;
          CLK           : in  std_logic;
-         PARAMETERS    : in  std_logic_vector(0 downto 0); 
+         PARAMETERS    : in  std_logic_vector(31 downto 0); 
          WRITE_EN      : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
          WRITE_ST      : in  std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
          HALT          : in  std_logic;
@@ -214,7 +214,7 @@ architecture RTL of ipcore2RTL_hwn_nd_2 is
          PARAM_DT   : in  std_logic_vector(PAR_WIDTH-1 downto 0);
          PARAM_LD   : in  std_logic;
 
-         PARAMETERS : out std_logic_vector(0 downto 0)
+         PARAMETERS : out std_logic_vector(31 downto 0)
       );
    end component;
 
@@ -271,7 +271,7 @@ architecture RTL of ipcore2RTL_hwn_nd_2 is
 
    --  
    -- Parameter related signals 
-   signal sl_parameters       : std_logic_vector(0 downto 0);
+   signal sl_parameters       : std_logic_vector(31 downto 0);
 
    signal sl_RST : std_logic;
 
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd
index 61c5c4099b779d2daa67b10f8aa7b73444b98514..68e933311dd02539c5c2544d083493ef64394a0a 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd
@@ -18,7 +18,7 @@ entity ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2 is
    port (
       RST           : in  std_logic;
       CLK           : in  std_logic;
-      PARAMETERS    : in  std_logic_vector(0 downto 0); 
+      PARAMETERS    : in  std_logic_vector(31 downto 0); 
       REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
       READ_EN       : out std_logic_vector(0 downto 0);
       READ_ST       : in  std_logic_vector(0 downto 0);
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd
index ebe1a50005d7f0f19c5a4fcf70effd367b4f6bcc..13de23943aa7060f73e921574e0702f4f45d034e 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd
@@ -18,7 +18,7 @@ entity ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2 is
    port (
       RST           : in  std_logic;
       CLK           : in  std_logic;
-      PARAMETERS    : in  std_logic_vector(0 downto 0); 
+      PARAMETERS    : in  std_logic_vector(31 downto 0); 
       WRITE_EN      : out std_logic_vector(0 downto 0);
       WRITE_ST      : in  std_logic_vector(0 downto 0);
       HALT          : in  std_logic;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd
index da4b638280305498eeb5dcd9a4f0f303779737e8..ed813c89479b738a9e0520dad9d75085851a0dff 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd
@@ -62,9 +62,9 @@ architecture RTL of ipcore2RTL_hwn_nd_3 is
    constant c_STAGES       : natural := 1; -- number of pipeline stages or delay
    constant c_IP_RESET     : natural := 1; -- active level of the HW IP reset signal
    constant c_WRAP         : boolean := true; -- Operation mode: Single_Shot (false) or Continuous (true)
-   constant c_PAR_NUMBER   : natural := 0; -- number of global parameters
-   constant c_N_PAR        : natural := 0; -- indicates if parameters are used (1) or not (0)
-   constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
+   constant c_PAR_NUMBER   : natural := 1; -- number of global parameters
+   constant c_N_PAR        : natural := 1; -- indicates if parameters are used (1) or not (0)
+   constant c_PAR_BITWIDTH : natural := 32; -- aggregate bitwidth of the parameter vector
    constant c_PAR_VECTOR   : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
        (0,0,0,0), (0,0,0,0)    -- two dummy elements
    );
@@ -84,7 +84,7 @@ architecture RTL of ipcore2RTL_hwn_nd_3 is
       port (
          RST           : in  std_logic;
          CLK           : in  std_logic;
-         PARAMETERS    : in  std_logic_vector(0 downto 0); 
+         PARAMETERS    : in  std_logic_vector(31 downto 0); 
          REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
          READ_EN       : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
          READ_ST       : in  std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
@@ -135,7 +135,7 @@ architecture RTL of ipcore2RTL_hwn_nd_3 is
       port (
          RST           : in  std_logic;
          CLK           : in  std_logic;
-         PARAMETERS    : in  std_logic_vector(0 downto 0); 
+         PARAMETERS    : in  std_logic_vector(31 downto 0); 
          WRITE_EN      : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
          WRITE_ST      : in  std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
          HALT          : in  std_logic;
@@ -212,7 +212,7 @@ architecture RTL of ipcore2RTL_hwn_nd_3 is
          PARAM_DT   : in  std_logic_vector(PAR_WIDTH-1 downto 0);
          PARAM_LD   : in  std_logic;
 
-         PARAMETERS : out std_logic_vector(0 downto 0)
+         PARAMETERS : out std_logic_vector(31 downto 0)
       );
    end component;
 
@@ -269,7 +269,7 @@ architecture RTL of ipcore2RTL_hwn_nd_3 is
 
    --  
    -- Parameter related signals 
-   signal sl_parameters       : std_logic_vector(0 downto 0);
+   signal sl_parameters       : std_logic_vector(31 downto 0);
 
    signal sl_RST : std_logic;
 
@@ -360,7 +360,7 @@ begin
       WRITE_ST => sl_write_st(0)
    );
    --
-   data_out_Dout <= sl_out_port_0;  -- Func. Output param. "tmp0"
+   data_out_Dout <= PARAM_DT;  -- Func. Output param. "tmp0"
    data_out_CTRL <= sl_sof_wr ;
    data_out_Wr   <= sl_WRITES(0);
    sl_FULLS(0) <= data_out_Full;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd
index 45387a209844dbfbb2389245f873201ce42da705..25092b29e46c7c0b463714bbab4382bc68c9288a 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd
@@ -18,7 +18,7 @@ entity ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3 is
    port (
       RST           : in  std_logic;
       CLK           : in  std_logic;
-      PARAMETERS    : in  std_logic_vector(0 downto 0); 
+      PARAMETERS    : in  std_logic_vector(31 downto 0); 
       REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
       READ_EN       : out std_logic_vector(0 downto 0);
       READ_ST       : in  std_logic_vector(0 downto 0);
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd
index 5056736b11cf5aa7f42f93db9ced3d82608b5b0e..9247ea5b07c2b052d50751353c9490ee8827900c 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd
@@ -18,7 +18,7 @@ entity ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3 is
    port (
       RST           : in  std_logic;
       CLK           : in  std_logic;
-      PARAMETERS    : in  std_logic_vector(0 downto 0); 
+      PARAMETERS    : in  std_logic_vector(31 downto 0); 
       WRITE_EN      : out std_logic_vector(0 downto 0);
       WRITE_ST      : in  std_logic_vector(0 downto 0);
       HALT          : in  std_logic;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/register_rf/1/register_rf.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/register_rf/1/register_rf.vhd
index 80c477cfe5664f29cbd8b9d6dcb8ff888344a4e2..e09729b6ed853b977fb9cc22ee936b33a7b6e995 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/register_rf/1/register_rf.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/register_rf/1/register_rf.vhd
@@ -1,30 +1,80 @@
--------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 entity register_rf is
-
+generic (
+	C_reg_rf_address  : std_logic_vector(18 downto 0) := B"0000000000000000000" -- 0
+);
 port (
-	rst  : in std_logic;
-	clk  : in std_logic;
-	--
+	rst            : in std_logic;
+	clk            : in std_logic;
 	
 	-- Interface to PCIe 
-	address         : in std_logic_vector(18 downto 0);
-	read_data       : out std_logic_vector(31 downto 0);
-	read_en         : in std_logic;
-	write_en        : in std_logic;
-	write_data      : in std_logic_vector(31 downto 0)
-	--
+	address           : in std_logic_vector(18 downto 0);
+	read_data         : out std_logic_vector(31 downto 0);
+	read_en           : in std_logic;
+	write_en          : in std_logic;
+	write_data        : in std_logic_vector(31 downto 0);
+	
+	-- Interface to reg reg
+	reg_rf_read_data  : in std_logic_vector(32-1 downto 0);
+	reg_rf_read_en    : out std_logic;
+	reg_rf_write_en   : out std_logic;
+	reg_rf_write_data : out std_logic_vector(32-1 downto 0)	
 );
 end register_rf;
 
 architecture RTL of register_rf is
  
-	signal sl_read_data : std_logic_vector(32-1 downto 0)   := (others=>'0');
+signal sl_read_data : std_logic_vector(32-1 downto 0)   := (others=>'0');
  
+signal mm_clk : std_logic;
+signal mm_rst : std_logic; 
+ 
+begin
+
+mm_clk <= clk;
+mm_rst <= rst;
+
+process (mm_clk, mm_rst)
+	begin
+		if (rising_edge(mm_clk)) then
+			if (mm_rst = '1') then
+				reg_rf_write_en <= '0';
+				reg_rf_read_en  <= '0';
+			else
+				if ( (address(18 downto 2) = C_reg_rf_address(18 downto 2)) and write_en = '1') then
+					reg_rf_write_data <= write_data(32-1 downto 0);
+					reg_rf_write_en <= '1';
+				else
+					reg_rf_write_en <= '0';
+				end if;
+
+				if( (address(18 downto 2) = C_reg_rf_address(18 downto 2)) and read_en= '1') then
+					reg_rf_read_en <= '1';
+				else
+					reg_rf_read_en <= '0';
+				end if;
+		end if;
+	end if;
+end process;
+
+process (mm_clk, mm_rst)
 begin
-	read_data <= (others => '0');
+  if (rising_edge(mm_clk)) then
+    if (mm_rst = '1') then
+	  else
+	    case address(18 downto 2) is
+			  when (C_reg_rf_address(18 downto 2) ) =>
+			    sl_read_data(32-1 downto 0) <=   reg_rf_read_data;
+			  when others => 
+				  sl_read_data <= (others => '0');
+		  end case;
+	  end if;
+	end if;
+end process;
+
+read_data <= sl_read_data;
 
 end RTL;
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_control_if_ip_wrapper.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_control_if_ip_wrapper.vhd
index f0b19997c23cfd0430e37229ffb1df0cc6955b37..46f96b1a213fd244f221b2d13462f18f340333ad 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_control_if_ip_wrapper.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_control_if_ip_wrapper.vhd
@@ -6,9 +6,9 @@ use IEEE.STD_LOGIC_1164.ALL;
 
 entity ipcore2RTL_control_if_ip_wrapper is
   port (
-    PARAM_DT : out std_logic_vector(0 downto 0);
+    PARAM_DT : out std_logic_vector(31 downto 0);
     PARAM_LD : out std_logic;
-    PARAMETERS_IN : in std_logic_vector(0 downto 0);
+    PARAMETERS_IN : in std_logic_vector(31 downto 0);
     PARAMETERS_IN_LD : in std_logic;
     RST : in std_logic;
     CLK : in std_logic
@@ -39,7 +39,7 @@ begin
 ipcore2RTL_control_if_ip_wrapper_ip : control_if
 	generic map (
 		RESET_HIGH => 1,
-		QUANT => 1
+		QUANT => 32
 	)
     port map (
 		PARAM_DT => PARAM_DT,
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_1_ip_wrapper.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_1_ip_wrapper.vhd
index c1c91b24bd9cb5d1342bc7bd78663c3748bd49a8..49b4bf6039484b6f198e842fa51688fd8cff7174 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_1_ip_wrapper.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_1_ip_wrapper.vhd
@@ -16,7 +16,7 @@ entity ipcore2RTL_hwn_nd_1_ip_wrapper is
     ND_1OP_1_Full : in std_logic;
     ND_1OP_1_CLK : out std_logic;
     ND_1OP_1_CTRL : out std_logic;
-    PARAM_DT : in std_logic_vector(0 downto 0);
+    PARAM_DT : in std_logic_vector(31 downto 0);
     PARAM_LD : in std_logic;
     STOP : out std_logic;
     ERROR : out std_logic;
@@ -48,7 +48,7 @@ architecture STRUCTURE of ipcore2RTL_hwn_nd_1_ip_wrapper is
 		ND_1OP_1_Full : in std_logic;
 		ND_1OP_1_CLK : out std_logic;
 		ND_1OP_1_CTRL : out std_logic;
-		PARAM_DT : in std_logic_vector(0 downto 0);
+		PARAM_DT : in std_logic_vector(31 downto 0);
 		PARAM_LD : in std_logic;
 		STOP : out std_logic;
 		ERROR : out std_logic;
@@ -63,7 +63,7 @@ begin
 ipcore2RTL_hwn_nd_1_ip_wrapper_ip : ipcore2rtl_hwn_nd_1
 	generic map (
 		RESET_HIGH => 1,
-		PAR_WIDTH => 1,
+		PAR_WIDTH => 32,
 		QUANT => 32,
 		WRAP => true
 	)
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_2_ip_wrapper.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_2_ip_wrapper.vhd
index 075125c442c98821e2d2a0d985ce322a825630d2..eb637addc4c17caca8c45f158a350b55163d9611 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_2_ip_wrapper.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_2_ip_wrapper.vhd
@@ -16,7 +16,7 @@ entity ipcore2RTL_hwn_nd_2_ip_wrapper is
     ND_2OP_1_Full : in std_logic;
     ND_2OP_1_CLK : out std_logic;
     ND_2OP_1_CTRL : out std_logic;
-    PARAM_DT : in std_logic_vector(0 downto 0);
+    PARAM_DT : in std_logic_vector(31 downto 0);
     PARAM_LD : in std_logic;
     STOP : out std_logic;
     ERROR : out std_logic;
@@ -48,7 +48,7 @@ architecture STRUCTURE of ipcore2RTL_hwn_nd_2_ip_wrapper is
 		ND_2OP_1_Full : in std_logic;
 		ND_2OP_1_CLK : out std_logic;
 		ND_2OP_1_CTRL : out std_logic;
-		PARAM_DT : in std_logic_vector(0 downto 0);
+		PARAM_DT : in std_logic_vector(31 downto 0);
 		PARAM_LD : in std_logic;
 		STOP : out std_logic;
 		ERROR : out std_logic;
@@ -63,7 +63,7 @@ begin
 ipcore2RTL_hwn_nd_2_ip_wrapper_ip : ipcore2rtl_hwn_nd_2
 	generic map (
 		RESET_HIGH => 1,
-		PAR_WIDTH => 1,
+		PAR_WIDTH => 32,
 		QUANT => 32,
 		WRAP => true
 	)
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_3_ip_wrapper.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_3_ip_wrapper.vhd
index 97cedf281f21391c2446830c1fe42780b64fe8d6..94d3add4b9a51be450bb85e497c05e1cc6e54ccc 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_3_ip_wrapper.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_hwn_nd_3_ip_wrapper.vhd
@@ -16,7 +16,7 @@ entity ipcore2RTL_hwn_nd_3_ip_wrapper is
     data_out_Full : in std_logic;
     data_out_CLK : out std_logic;
     data_out_CTRL : out std_logic;
-    PARAM_DT : in std_logic_vector(0 downto 0);
+    PARAM_DT : in std_logic_vector(31 downto 0);
     PARAM_LD : in std_logic;
     STOP : out std_logic;
     ERROR : out std_logic;
@@ -48,7 +48,7 @@ architecture STRUCTURE of ipcore2RTL_hwn_nd_3_ip_wrapper is
 		data_out_Full : in std_logic;
 		data_out_CLK : out std_logic;
 		data_out_CTRL : out std_logic;
-		PARAM_DT : in std_logic_vector(0 downto 0);
+		PARAM_DT : in std_logic_vector(31 downto 0);
 		PARAM_LD : in std_logic;
 		STOP : out std_logic;
 		ERROR : out std_logic;
@@ -63,7 +63,7 @@ begin
 ipcore2RTL_hwn_nd_3_ip_wrapper_ip : ipcore2rtl_hwn_nd_3
 	generic map (
 		RESET_HIGH => 1,
-		PAR_WIDTH => 1,
+		PAR_WIDTH => 32,
 		QUANT => 32,
 		WRAP => true
 	)
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_register_rf_ip_wrapper.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_register_rf_ip_wrapper.vhd
index 0b91df0ed9dcc14c2fb67688aeb90938e6ad5603..d699356bf3fa94b6072d2baaf8facb50b174849d 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_register_rf_ip_wrapper.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL_register_rf_ip_wrapper.vhd
@@ -11,6 +11,10 @@ entity ipcore2RTL_register_rf_ip_wrapper is
     read_en : in std_logic;
     write_en : in std_logic;
     write_data : in std_logic_vector(31 downto 0);
+		reg_rf_read_data  : in std_logic_vector(32-1 downto 0);
+		reg_rf_read_en    : out std_logic;
+		reg_rf_write_en   : out std_logic;
+		reg_rf_write_data : out std_logic_vector(32-1 downto 0);	    
     RST : in std_logic;
     CLK : in std_logic
   );
@@ -27,6 +31,10 @@ architecture STRUCTURE of ipcore2RTL_register_rf_ip_wrapper is
 		read_en : in std_logic;
 		write_en : in std_logic;
 		write_data : in std_logic_vector(31 downto 0);
+		reg_rf_read_data  : in std_logic_vector(32-1 downto 0);   
+		reg_rf_read_en    : out std_logic;                        
+		reg_rf_write_en   : out std_logic;                        
+		reg_rf_write_data : out std_logic_vector(32-1 downto 0);			
 		RST : in std_logic;
 		CLK : in std_logic
 	);
@@ -41,6 +49,10 @@ ipcore2RTL_register_rf_ip_wrapper_ip : register_rf
 		read_en => read_en,
 		write_en => write_en,
 		write_data => write_data,
+		reg_rf_read_data   => reg_rf_read_data, 
+		reg_rf_read_en     => reg_rf_read_en,   
+		reg_rf_write_en    => reg_rf_write_en,  
+		reg_rf_write_data  => reg_rf_write_data,		
 		RST => RST,
 		CLK => CLK
     );
diff --git a/applications/compaan/libraries/src/vhdl/ipcore.vhd b/applications/compaan/libraries/src/vhdl/ipcore.vhd
index 5ff91d2d39c7c6de5d84bf5765f07bb539751cd5..2ab280cb3c1df0a8c4c5ad5a9a04231c67f9268e 100644
--- a/applications/compaan/libraries/src/vhdl/ipcore.vhd
+++ b/applications/compaan/libraries/src/vhdl/ipcore.vhd
@@ -130,6 +130,10 @@ component ipcore2RTL_register_rf_ip_wrapper is
 		read_en : in std_logic;
 		write_en : in std_logic;
 		write_data : in std_logic_vector(31 downto 0);
+		reg_rf_read_data  : in std_logic_vector(32-1 downto 0);   
+		reg_rf_read_en    : out std_logic;                        
+		reg_rf_write_en   : out std_logic;                        
+		reg_rf_write_data : out std_logic_vector(32-1 downto 0);		
 		RST : in std_logic;
 		CLK : in std_logic
 
@@ -245,6 +249,11 @@ end component;
 	signal snc_state : std_logic;
 	signal snc_cnt : natural;
 
+  signal signal_reg_rf_read_data  : std_logic_vector(31 downto 0);
+  signal signal_reg_rf_read_en    : std_logic;
+  signal signal_reg_rf_write_en   : std_logic;
+  signal signal_reg_rf_write_data : std_logic_vector(31 downto 0);
+
 	-- START the actual definition of a Design
 
 begin
@@ -257,6 +266,10 @@ begin
 	mm_clk_s <= MM_CLK;
 	mm_rst_s <= MM_RST;
 
+	-- Connect parameters
+	signal_PARAMETERS <= signal_reg_rf_write_data;
+	signal_PARAMETERS_LD <= signal_reg_rf_write_en;
+
 	-- Connect Hiercical Interconnections
 
   -- Hierarchical signals -3- compaandesign.com:ipcore2RTL:design_ipcore:1:data_in
@@ -376,6 +389,10 @@ begin
 		read_en => signal_read_en,
 		write_en => signal_write_en,
 		write_data => signal_write_data,
+		reg_rf_read_data  => signal_reg_rf_read_data,
+		reg_rf_read_en    => signal_reg_rf_read_en,
+		reg_rf_write_en   => signal_reg_rf_write_en,
+		reg_rf_write_data => signal_reg_rf_write_data,	
 		RST => mm_rst_s,
 		CLK => mm_clk_s
 	);