diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip
index d3c75ae0307c27ce1f524f86617126b8cc6c9deb..21089dce5a11b69ebc9405e6b4e416c197f19b6a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_xonoff_ring.mem' start='0x80' end='0xC0' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_dp_block_validate_err.mem' start='0x400' end='0x600' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx.mem' start='0x600' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_ring_input_select.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_ring_lane_info.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync.mem' start='0x3080' end='0x30C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x30C0' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='timer_0.s1' start='0x3400' end='0x3420' datawidth='16' /><slave name='reg_diag_bg.mem' start='0x3420' end='0x3440' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3440' end='0x3460' datawidth='32' /><slave name='reg_epcs.mem' start='0x3460' end='0x3480' datawidth='32' /><slave name='reg_remu.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x34A0' end='0x34B0' datawidth='32' /><slave name='pio_pps.mem' start='0x34B0' end='0x34C0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x34C0' end='0x34C8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x34C8' end='0x34D0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x34D0' end='0x34D8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x34D8' end='0x34E0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x34E0' end='0x34E8' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_ring_lane_info.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_dp_block_validate_err.mem' start='0x400' end='0x600' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx.mem' start='0x600' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_diag_bg.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_xonoff_local.mem' start='0x3080' end='0x30C0' datawidth='32' /><slave name='reg_dp_xonoff_lane.mem' start='0x30C0' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='timer_0.s1' start='0x3440' end='0x3460' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x3460' end='0x3480' datawidth='32' /><slave name='reg_epcs.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_remu.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x34C0' end='0x34D0' datawidth='32' /><slave name='pio_pps.mem' start='0x34D0' end='0x34E0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x34E0' end='0x34E8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x34E8' end='0x34F0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x34F0' end='0x34F8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x34F8' end='0x3500' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3500' end='0x3508' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_xonoff_ring.mem' start='0x80' end='0xC0' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_dp_block_validate_err.mem' start='0x400' end='0x600' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx.mem' start='0x600' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_ring_input_select.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_ring_lane_info.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync.mem' start='0x3080' end='0x30C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x30C0' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='timer_0.s1' start='0x3400' end='0x3420' datawidth='16' /><slave name='reg_diag_bg.mem' start='0x3420' end='0x3440' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3440' end='0x3460' datawidth='32' /><slave name='reg_epcs.mem' start='0x3460' end='0x3480' datawidth='32' /><slave name='reg_remu.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x34A0' end='0x34B0' datawidth='32' /><slave name='pio_pps.mem' start='0x34B0' end='0x34C0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x34C0' end='0x34C8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x34C8' end='0x34D0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x34D0' end='0x34D8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x34D8' end='0x34E0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x34E0' end='0x34E8' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_ring_lane_info.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_dp_block_validate_err.mem' start='0x400' end='0x600' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx.mem' start='0x600' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_diag_bg.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_xonoff_local.mem' start='0x3080' end='0x30C0' datawidth='32' /><slave name='reg_dp_xonoff_lane.mem' start='0x30C0' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='timer_0.s1' start='0x3440' end='0x3460' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x3460' end='0x3480' datawidth='32' /><slave name='reg_epcs.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_remu.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x34C0' end='0x34D0' datawidth='32' /><slave name='pio_pps.mem' start='0x34D0' end='0x34E0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x34E0' end='0x34E8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x34E8' end='0x34F0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x34F0' end='0x34F8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x34F8' end='0x3500' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3500' end='0x3508' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip
similarity index 98%
rename from applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.ip
rename to applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip
index ab02eab551b2d90973477eaaefc9e291c0635980..76151c053edc6f61b82ecb2d7fd2f4d53c3f77dd 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -1406,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_input_select.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_input_select.ip
rename to applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip
index c96795028e5159a7e96cedb008bf5aa82ae0e8bf..b5a1f35d48e598ab5a848bc68a400b71b7d692df 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_input_select.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_ring_reg_ring_input_select</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_ring_reg_ring_input_select</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">32</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>2</spirit:right>
+ <spirit:right>3</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>2</spirit:right>
+ <spirit:right>3</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_ring_reg_ring_input_select</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">3</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">4</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1406,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_input_select.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_input_select.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_input_select.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_input_select.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_input_select.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_input_select.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_input_select.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_input_select.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_input_select.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_input_select.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/qsys_lofar2_unb2b_ring.qsys b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/qsys_lofar2_unb2b_ring.qsys
index 7d3085abcfae06fea5df4cef8c1e99452544971f..ed28393abeccadf6702dafb6ea2281382a73ca83 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/qsys_lofar2_unb2b_ring.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/qsys_lofar2_unb2b_ring.qsys
@@ -30,7 +30,7 @@
{
datum baseAddress
{
- value = "192";
+ value = "128";
type = "String";
}
}
@@ -83,7 +83,7 @@
{
datum baseAddress
{
- value = "13536";
+ value = "13568";
type = "String";
}
}
@@ -133,7 +133,7 @@
{
datum baseAddress
{
- value = "13488";
+ value = "13520";
type = "String";
}
}
@@ -178,7 +178,7 @@
{
datum _sortIndex
{
- value = "31";
+ value = "33";
type = "int";
}
}
@@ -242,7 +242,7 @@
{
datum _sortIndex
{
- value = "30";
+ value = "32";
type = "int";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "13344";
+ value = "12320";
type = "String";
}
}
@@ -258,7 +258,7 @@
{
datum _sortIndex
{
- value = "26";
+ value = "28";
type = "int";
}
}
@@ -266,7 +266,7 @@
{
datum baseAddress
{
- value = "12416";
+ value = "12352";
type = "String";
}
}
@@ -274,7 +274,7 @@
{
datum _sortIndex
{
- value = "25";
+ value = "27";
type = "int";
}
}
@@ -286,19 +286,35 @@
type = "String";
}
}
- element reg_dp_xonoff_ring
+ element reg_dp_xonoff_lane
{
datum _sortIndex
{
- value = "32";
+ value = "25";
type = "int";
}
}
- element reg_dp_xonoff_ring.mem
+ element reg_dp_xonoff_lane.mem
{
datum baseAddress
{
- value = "128";
+ value = "12480";
+ type = "String";
+ }
+ }
+ element reg_dp_xonoff_local
+ {
+ datum _sortIndex
+ {
+ value = "26";
+ type = "int";
+ }
+ }
+ element reg_dp_xonoff_local.mem
+ {
+ datum baseAddress
+ {
+ value = "12416";
type = "String";
}
}
@@ -319,7 +335,7 @@
{
datum baseAddress
{
- value = "13528";
+ value = "13560";
type = "String";
}
}
@@ -340,7 +356,7 @@
{
datum baseAddress
{
- value = "13520";
+ value = "13552";
type = "String";
}
}
@@ -361,7 +377,7 @@
{
datum baseAddress
{
- value = "13408";
+ value = "13440";
type = "String";
}
}
@@ -377,7 +393,7 @@
{
datum baseAddress
{
- value = "13376";
+ value = "13408";
type = "String";
}
}
@@ -398,7 +414,7 @@
{
datum baseAddress
{
- value = "12480";
+ value = "13312";
type = "String";
}
}
@@ -419,7 +435,7 @@
{
datum baseAddress
{
- value = "13512";
+ value = "13544";
type = "String";
}
}
@@ -440,7 +456,7 @@
{
datum baseAddress
{
- value = "13504";
+ value = "13536";
type = "String";
}
}
@@ -461,7 +477,7 @@
{
datum baseAddress
{
- value = "13440";
+ value = "13472";
type = "String";
}
}
@@ -469,7 +485,7 @@
{
datum _sortIndex
{
- value = "27";
+ value = "29";
type = "int";
}
}
@@ -477,23 +493,7 @@
{
datum baseAddress
{
- value = "13472";
- type = "String";
- }
- }
- element reg_ring_input_select
- {
- datum _sortIndex
- {
- value = "33";
- type = "int";
- }
- }
- element reg_ring_input_select.mem
- {
- datum baseAddress
- {
- value = "12320";
+ value = "13504";
type = "String";
}
}
@@ -509,7 +509,7 @@
{
datum baseAddress
{
- value = "12352";
+ value = "192";
type = "String";
}
}
@@ -517,7 +517,7 @@
{
datum _sortIndex
{
- value = "29";
+ value = "31";
type = "int";
}
}
@@ -533,7 +533,7 @@
{
datum _sortIndex
{
- value = "28";
+ value = "30";
type = "int";
}
}
@@ -641,7 +641,7 @@
{
datum baseAddress
{
- value = "13312";
+ value = "13376";
type = "String";
}
}
@@ -1103,38 +1103,73 @@
type="conduit"
dir="end" />
<interface
- name="reg_dp_xonoff_ring_address"
- internal="reg_dp_xonoff_ring.address"
+ name="reg_dp_xonoff_lane_address"
+ internal="reg_dp_xonoff_lane.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_lane_clk"
+ internal="reg_dp_xonoff_lane.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_lane_read"
+ internal="reg_dp_xonoff_lane.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_lane_readdata"
+ internal="reg_dp_xonoff_lane.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_dp_xonoff_ring_clk"
- internal="reg_dp_xonoff_ring.clk"
+ name="reg_dp_xonoff_lane_reset"
+ internal="reg_dp_xonoff_lane.reset"
type="conduit"
dir="end" />
<interface
- name="reg_dp_xonoff_ring_read"
- internal="reg_dp_xonoff_ring.read"
+ name="reg_dp_xonoff_lane_write"
+ internal="reg_dp_xonoff_lane.write"
type="conduit"
dir="end" />
<interface
- name="reg_dp_xonoff_ring_readdata"
- internal="reg_dp_xonoff_ring.readdata"
+ name="reg_dp_xonoff_lane_writedata"
+ internal="reg_dp_xonoff_lane.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_dp_xonoff_ring_reset"
- internal="reg_dp_xonoff_ring.reset"
+ name="reg_dp_xonoff_local_address"
+ internal="reg_dp_xonoff_local.address"
type="conduit"
dir="end" />
<interface
- name="reg_dp_xonoff_ring_write"
- internal="reg_dp_xonoff_ring.write"
+ name="reg_dp_xonoff_local_clk"
+ internal="reg_dp_xonoff_local.clk"
type="conduit"
dir="end" />
<interface
- name="reg_dp_xonoff_ring_writedata"
- internal="reg_dp_xonoff_ring.writedata"
+ name="reg_dp_xonoff_local_read"
+ internal="reg_dp_xonoff_local.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_local_readdata"
+ internal="reg_dp_xonoff_local.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_local_reset"
+ internal="reg_dp_xonoff_local.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_local_write"
+ internal="reg_dp_xonoff_local.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_local_writedata"
+ internal="reg_dp_xonoff_local.writedata"
type="conduit"
dir="end" />
<interface
@@ -1444,41 +1479,6 @@
internal="reg_ring_info.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_ring_input_select_address"
- internal="reg_ring_input_select.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_ring_input_select_clk"
- internal="reg_ring_input_select.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_ring_input_select_read"
- internal="reg_ring_input_select.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_ring_input_select_readdata"
- internal="reg_ring_input_select.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_ring_input_select_reset"
- internal="reg_ring_input_select.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_ring_input_select_write"
- internal="reg_ring_input_select.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_ring_input_select_writedata"
- internal="reg_ring_input_select.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_ring_lane_info_address"
internal="reg_ring_lane_info.address"
@@ -4684,7 +4684,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_xonoff_ring.mem' start='0x80' end='0xC0' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_dp_block_validate_err.mem' start='0x400' end='0x600' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx.mem' start='0x600' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_ring_input_select.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_ring_lane_info.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync.mem' start='0x3080' end='0x30C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x30C0' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='timer_0.s1' start='0x3400' end='0x3420' datawidth='16' /><slave name='reg_diag_bg.mem' start='0x3420' end='0x3440' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3440' end='0x3460' datawidth='32' /><slave name='reg_epcs.mem' start='0x3460' end='0x3480' datawidth='32' /><slave name='reg_remu.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x34A0' end='0x34B0' datawidth='32' /><slave name='pio_pps.mem' start='0x34B0' end='0x34C0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x34C0' end='0x34C8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x34C8' end='0x34D0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x34D0' end='0x34D8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x34D8' end='0x34E0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x34E0' end='0x34E8' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_ring_lane_info.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_dp_block_validate_err.mem' start='0x400' end='0x600' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx.mem' start='0x600' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_diag_bg.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_xonoff_local.mem' start='0x3080' end='0x30C0' datawidth='32' /><slave name='reg_dp_xonoff_lane.mem' start='0x30C0' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='timer_0.s1' start='0x3440' end='0x3460' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x3460' end='0x3480' datawidth='32' /><slave name='reg_epcs.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_remu.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x34C0' end='0x34D0' datawidth='32' /><slave name='pio_pps.mem' start='0x34D0' end='0x34E0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x34E0' end='0x34E8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x34E8' end='0x34F0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x34F0' end='0x34F8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x34F8' end='0x3500' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3500' end='0x3508' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -12251,7 +12251,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_xonoff_ring"
+ name="reg_dp_xonoff_lane"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -12837,37 +12837,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_dp_xonoff_local"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -12883,7 +12883,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12947,7 +12947,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13016,7 +13016,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -13422,11 +13422,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -13453,37 +13453,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14069,37 +14069,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14115,7 +14115,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14179,7 +14179,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14248,7 +14248,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -14654,11 +14654,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -14685,37 +14685,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15301,37 +15301,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15347,7 +15347,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15411,7 +15411,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15480,7 +15480,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15886,11 +15886,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15917,37 +15917,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15963,7 +15963,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16027,7 +16027,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16096,7 +16096,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -16502,11 +16502,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -16533,37 +16533,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17149,37 +17149,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17195,7 +17195,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17259,7 +17259,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17328,7 +17328,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17734,11 +17734,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17765,37 +17765,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_ring_info"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17811,7 +17811,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17875,7 +17875,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17944,7 +17944,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18350,11 +18350,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18381,37 +18381,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_ring_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_ring_input_select"
+ name="reg_ring_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18427,7 +18427,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18491,7 +18491,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18560,7 +18560,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18966,11 +18966,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18997,30 +18997,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_ring_input_select</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_ring_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_input_select</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_input_select</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_input_select</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_input_select</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_input_select</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_input_select</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_input_select.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -24067,7 +24067,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x34e0" />
+ <parameter name="baseAddress" value="0x3500" />
</connection>
<connection
kind="avalon"
@@ -24102,7 +24102,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x34b0" />
+ <parameter name="baseAddress" value="0x34d0" />
</connection>
<connection
kind="avalon"
@@ -24116,49 +24116,49 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x3480" />
+ <parameter name="baseAddress" value="0x34a0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x3460" />
+ <parameter name="baseAddress" value="0x3480" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x34d8" />
+ <parameter name="baseAddress" value="0x34f8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x34d0" />
+ <parameter name="baseAddress" value="0x34f0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x34c8" />
+ <parameter name="baseAddress" value="0x34e8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x34c0" />
+ <parameter name="baseAddress" value="0x34e0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x3440" />
+ <parameter name="baseAddress" value="0x3460" />
</connection>
<connection
kind="avalon"
@@ -24172,7 +24172,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="baseAddress" value="0x30c0" />
+ <parameter name="baseAddress" value="0x3400" />
</connection>
<connection
kind="avalon"
@@ -24195,6 +24195,20 @@
end="reg_bsn_monitor_v2_ring_tx.mem">
<parameter name="baseAddress" value="0x0600" />
</connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_dp_xonoff_lane.mem">
+ <parameter name="baseAddress" value="0x30c0" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_dp_xonoff_local.mem">
+ <parameter name="baseAddress" value="0x3080" />
+ </connection>
<connection
kind="avalon"
version="18.0"
@@ -24207,14 +24221,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync.mem">
- <parameter name="baseAddress" value="0x3080" />
+ <parameter name="baseAddress" value="0x3040" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_ring_info.mem">
- <parameter name="baseAddress" value="0x34a0" />
+ <parameter name="baseAddress" value="0x34c0" />
</connection>
<connection
kind="avalon"
@@ -24235,14 +24249,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_ring_lane_info.mem">
- <parameter name="baseAddress" value="0x3040" />
+ <parameter name="baseAddress" value="0x00c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_diag_bg.mem">
- <parameter name="baseAddress" value="0x3420" />
+ <parameter name="baseAddress" value="0x3020" />
</connection>
<connection
kind="avalon"
@@ -24251,20 +24265,6 @@
end="ram_diag_bg.mem">
<parameter name="baseAddress" value="0x0200" />
</connection>
- <connection
- kind="avalon"
- version="18.0"
- start="cpu_0.data_master"
- end="reg_dp_xonoff_ring.mem">
- <parameter name="baseAddress" value="0x0080" />
- </connection>
- <connection
- kind="avalon"
- version="18.0"
- start="cpu_0.data_master"
- end="reg_ring_input_select.mem">
- <parameter name="baseAddress" value="0x3020" />
- </connection>
<connection
kind="avalon"
version="18.0"
@@ -24277,7 +24277,7 @@
version="18.0"
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
- <parameter name="baseAddress" value="0x00c0" />
+ <parameter name="baseAddress" value="0x0080" />
</connection>
<connection
kind="avalon"
@@ -24305,7 +24305,7 @@
version="18.0"
start="cpu_0.data_master"
end="timer_0.s1">
- <parameter name="baseAddress" value="0x3400" />
+ <parameter name="baseAddress" value="0x3440" />
</connection>
<connection
kind="avalon"
@@ -24405,47 +24405,47 @@
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_dp_block_validate_err.system" />
+ end="reg_dp_xonoff_lane.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_dp_block_validate_bsn_at_sync.system" />
+ end="reg_dp_xonoff_local.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_ring_info.system" />
+ end="reg_dp_block_validate_err.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_tr_10gbe_mac.system" />
+ end="reg_dp_block_validate_bsn_at_sync.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_tr_10gbe_eth10g.system" />
+ end="reg_ring_info.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_diag_bg.system" />
+ end="reg_tr_10gbe_mac.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="ram_diag_bg.system" />
+ end="reg_tr_10gbe_eth10g.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_dp_xonoff_ring.system" />
+ end="reg_diag_bg.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_ring_input_select.system" />
+ end="ram_diag_bg.system" />
<connection
kind="interrupt"
version="18.0"
@@ -24577,6 +24577,11 @@
version="18.0"
start="clk_0.clk_reset"
end="reg_ring_lane_info.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_dp_xonoff_local.system_reset" />
<connection
kind="reset"
version="18.0"
@@ -24606,22 +24611,17 @@
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_diag_bg.system_reset" />
+ end="reg_dp_xonoff_lane.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="ram_diag_bg.system_reset" />
- <connection
- kind="reset"
- version="18.0"
- start="clk_0.clk_reset"
- end="reg_dp_xonoff_ring.system_reset" />
+ end="reg_diag_bg.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_ring_input_select.system_reset" />
+ end="ram_diag_bg.system_reset" />
<connection
kind="reset"
version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg
index 53dfd8b061f515143a638fd25514bb76d8e87479..44153f43a312914a79f42322622e0acb776de660 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg
@@ -57,8 +57,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_input_select.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg
index 55b63370124b8ab2e43f0d773416dfe1f096b367..68e36f783e66c851947adced910b1d78875e8d4b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg
@@ -57,8 +57,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_ring.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_input_select.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
index 121c7413656e9ace1a90b74ec8eacfcfcd0a5c89..31cf5e202561d25d6780c9b1b8d4a7f13d5dc1e4 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
@@ -249,11 +249,11 @@ ARCHITECTURE str OF lofar2_unb2b_ring IS
SIGNAL ram_diag_bg_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL ram_diag_bg_cipo : t_mem_cipo := c_mem_cipo_rst;
- SIGNAL reg_ring_input_select_copi : t_mem_copi := c_mem_copi_rst;
- SIGNAL reg_ring_input_select_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_dp_xonoff_lane_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_xonoff_lane_cipo : t_mem_cipo := c_mem_cipo_rst;
- SIGNAL reg_dp_xonoff_ring_copi : t_mem_copi := c_mem_copi_rst;
- SIGNAL reg_dp_xonoff_ring_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_dp_xonoff_local_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_xonoff_local_cipo : t_mem_cipo := c_mem_cipo_rst;
SIGNAL reg_ring_info_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL reg_ring_info_cipo : t_mem_cipo := c_mem_cipo_rst;
@@ -295,7 +295,6 @@ ARCHITECTURE str OF lofar2_unb2b_ring IS
SIGNAL dp_xonoff_local_snk_in_arr : t_dp_sosi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL dp_xonoff_local_src_out_arr : t_dp_sosi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL dp_xonoff_local_src_in_arr : t_dp_siso_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
- SIGNAL dp_xonoff_snk_in_arr : t_dp_sosi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL lane_rx_cable_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL lane_rx_board_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
@@ -317,9 +316,6 @@ ARCHITECTURE str OF lofar2_unb2b_ring IS
SIGNAL ring_info : t_ring_info;
- SIGNAL dp_mux_sel_ctrl_arr : t_natural_arr(c_nof_lanes-1 DOWNTO 0);
- SIGNAL reg_ring_input_select_slv : STD_LOGIC_VECTOR(c_nof_lanes-1 DOWNTO 0);
-
-- 10GbE
SIGNAL tr_ref_clk_312 : STD_LOGIC;
SIGNAL tr_ref_clk_156 : STD_LOGIC;
@@ -541,10 +537,10 @@ BEGIN
ram_diag_bg_cipo => ram_diag_bg_cipo,
reg_ring_lane_info_copi => reg_ring_lane_info_copi,
reg_ring_lane_info_cipo => reg_ring_lane_info_cipo,
- reg_ring_input_select_copi => reg_ring_input_select_copi,
- reg_ring_input_select_cipo => reg_ring_input_select_cipo,
- reg_dp_xonoff_ring_copi => reg_dp_xonoff_ring_copi,
- reg_dp_xonoff_ring_cipo => reg_dp_xonoff_ring_cipo,
+ reg_dp_xonoff_lane_copi => reg_dp_xonoff_lane_copi,
+ reg_dp_xonoff_lane_cipo => reg_dp_xonoff_lane_cipo,
+ reg_dp_xonoff_local_copi => reg_dp_xonoff_local_copi,
+ reg_dp_xonoff_local_cipo => reg_dp_xonoff_local_cipo,
reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
@@ -642,119 +638,88 @@ BEGIN
);
bs_sosi <= local_sosi;
+
-----------------------------------------------------------------------------
- -- dp_xonoffs
+ -- MMP dp_xonoff from_lane_sosi
-----------------------------------------------------------------------------
- gen_dp_xonoff: FOR I IN 0 TO c_nof_lanes -1 GENERATE
- -- dp_xonoff from_lane_sosi
- u_dp_xonoff_lane : ENTITY dp_lib.dp_xonoff
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
+ u_mmp_dp_xonoff_lane : ENTITY dp_lib.mms_dp_xonoff
+ GENERIC MAP (
+ g_nof_streams => c_nof_lanes,
+ g_default_value => '0'
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- in_siso => OPEN,
- in_sosi => from_lane_sosi_arr(I),
+ reg_mosi => reg_dp_xonoff_lane_copi,
+ reg_miso => reg_dp_xonoff_lane_cipo,
- out_siso => dp_xonoff_lane_src_in_arr(I),
- out_sosi => dp_xonoff_lane_src_out_arr(I)
- );
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- dp_xonoff local_sosi
- dp_xonoff_local_snk_in_arr(I) <= local_sosi; -- copy local sosi to all lanes
+ snk_out_arr => OPEN,
+ snk_in_arr => from_lane_sosi_arr,
- u_dp_xonoff_local : ENTITY dp_lib.dp_xonoff
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
-
- in_siso => OPEN,
- in_sosi => dp_xonoff_local_snk_in_arr(I),
-
- out_siso => dp_xonoff_local_src_in_arr(I),
- out_sosi => dp_xonoff_local_src_out_arr(I)
- );
- END GENERATE;
+ src_in_arr => dp_xonoff_lane_src_in_arr,
+ src_out_arr => dp_xonoff_lane_src_out_arr
+ );
-----------------------------------------------------------------------------
- -- DP Mux
+ -- MMP dp_xonoff local_sosi
-----------------------------------------------------------------------------
- -- The DP Mux is used in mode 4 which enables us to safely control the selected
- -- input externally. The inputs for the DP Mux come from two dp_xonoff that turn
- -- off the unselected input. This results in an output where either one or the
- -- other input is on and never both simultaneously. This selection is controlled
- -- using a MM register. The output of the DP Mux is conected to a mmp_dp_xonoff
- -- to disable the stream completly so no data at all is outputted.
-
- -- MM reg for dp_mux sel_ctrl.
- u_mmp_common_reg : ENTITY common_lib.mms_common_reg
+ gen_copy_local: FOR I IN 0 TO c_nof_lanes -1 GENERATE
+ dp_xonoff_local_snk_in_arr(I) <= local_sosi; -- copy local sosi to all lanes
+ END GENERATE;
+
+ u_mmp_dp_xonoff_local : ENTITY dp_lib.mms_dp_xonoff
GENERIC MAP (
- g_mm_reg => c_reg_ring_input_select
+ g_nof_streams => c_nof_lanes,
+ g_default_value => '0'
)
PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_ring_input_select_copi,
- reg_miso => reg_ring_input_select_cipo,
+ reg_mosi => reg_dp_xonoff_local_copi,
+ reg_miso => reg_dp_xonoff_local_cipo,
- in_reg => reg_ring_input_select_slv,
- out_reg => reg_ring_input_select_slv
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_out_arr => OPEN,
+ snk_in_arr => dp_xonoff_local_snk_in_arr,
+
+ src_in_arr => dp_xonoff_local_src_in_arr,
+ src_out_arr => dp_xonoff_local_src_out_arr
);
- -- dp mux array
+ -----------------------------------------------------------------------------
+ -- DP Mux
+ -----------------------------------------------------------------------------
gen_dp_mux: FOR I IN 0 TO c_nof_lanes -1 GENERATE
+
dp_xonoff_lane_src_in_arr(I) <= dp_mux_snk_out_2arr(I)(0);
dp_xonoff_local_src_in_arr(I) <= dp_mux_snk_out_2arr(I)(1);
dp_mux_snk_in_2arr(I)(0) <= dp_xonoff_lane_src_out_arr(I);
dp_mux_snk_in_2arr(I)(1) <= dp_xonoff_local_src_out_arr(I);
- dp_mux_sel_ctrl_arr(I) <= TO_UINT(slv(reg_ring_input_select_slv(I)));
-
u_dp_mux : ENTITY dp_lib.dp_mux
GENERIC MAP (
- g_mode => 4,
g_append_channel_lo => FALSE,
g_sel_ctrl_invert => TRUE
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
-
- sel_ctrl => dp_mux_sel_ctrl_arr(I),
snk_out_arr => dp_mux_snk_out_2arr(I),
snk_in_arr => dp_mux_snk_in_2arr(I),
src_in => c_dp_siso_rdy,
- src_out => dp_xonoff_snk_in_arr(I)
+ src_out => to_lane_sosi_arr(I)
);
END GENERATE;
- -- mmp_dp_xonoff to enable/disable the output
- u_mmp_dp_xonoff_ring : ENTITY dp_lib.mms_dp_xonoff
- GENERIC MAP (
- g_nof_streams => c_nof_lanes,
- g_default_value => '1' -- default enabled
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_dp_xonoff_ring_copi,
- reg_miso => reg_dp_xonoff_ring_cipo,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- snk_out_arr => OPEN,
- snk_in_arr => dp_xonoff_snk_in_arr,
-
- src_in_arr => (OTHERS => c_dp_siso_rdy),
- src_out_arr => to_lane_sosi_arr
- );
-
-----------------------------------------------------------------------------
-- Ring info
-----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
index 099613cd7f76156876aeeea65cd1383368a7fc84..dfc18d9825f75d59cf0244bbf5066b441c7ab2e9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
@@ -37,92 +37,92 @@ ENTITY mmc_lofar2_unb2b_ring IS
g_sim_node_nr : NATURAL := 0
);
PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
- pout_wdi : OUT STD_LOGIC;
-
+ pout_wdi : OUT STD_LOGIC;
+
-- Manual WDI override
- reg_wdi_copi : OUT t_mem_copi;
- reg_wdi_cipo : IN t_mem_cipo;
-
+ reg_wdi_copi : OUT t_mem_copi;
+ reg_wdi_cipo : IN t_mem_cipo;
+
-- system_info
- reg_unb_system_info_copi : OUT t_mem_copi;
- reg_unb_system_info_cipo : IN t_mem_cipo;
- rom_unb_system_info_copi : OUT t_mem_copi;
- rom_unb_system_info_cipo : IN t_mem_cipo;
-
+ reg_unb_system_info_copi : OUT t_mem_copi;
+ reg_unb_system_info_cipo : IN t_mem_cipo;
+ rom_unb_system_info_copi : OUT t_mem_copi;
+ rom_unb_system_info_cipo : IN t_mem_cipo;
+
-- UniBoard I2C sensors
- reg_unb_sens_copi : OUT t_mem_copi;
- reg_unb_sens_cipo : IN t_mem_cipo;
+ reg_unb_sens_copi : OUT t_mem_copi;
+ reg_unb_sens_cipo : IN t_mem_cipo;
- reg_fpga_temp_sens_copi : OUT t_mem_copi;
- reg_fpga_temp_sens_cipo : IN t_mem_cipo;
- reg_fpga_voltage_sens_copi : OUT t_mem_copi;
- reg_fpga_voltage_sens_cipo : IN t_mem_cipo;
+ reg_fpga_temp_sens_copi : OUT t_mem_copi;
+ reg_fpga_temp_sens_cipo : IN t_mem_cipo;
+ reg_fpga_voltage_sens_copi : OUT t_mem_copi;
+ reg_fpga_voltage_sens_cipo : IN t_mem_cipo;
- reg_unb_pmbus_copi : OUT t_mem_copi;
- reg_unb_pmbus_cipo : IN t_mem_cipo;
+ reg_unb_pmbus_copi : OUT t_mem_copi;
+ reg_unb_pmbus_cipo : IN t_mem_cipo;
-- PPSH
- reg_ppsh_copi : OUT t_mem_copi;
- reg_ppsh_cipo : IN t_mem_cipo;
-
+ reg_ppsh_copi : OUT t_mem_copi;
+ reg_ppsh_cipo : IN t_mem_cipo;
+
-- eth1g
- eth1g_mm_rst : OUT STD_LOGIC;
- eth1g_tse_copi : OUT t_mem_copi;
- eth1g_tse_cipo : IN t_mem_cipo;
- eth1g_reg_copi : OUT t_mem_copi;
- eth1g_reg_cipo : IN t_mem_cipo;
- eth1g_reg_interrupt : IN STD_LOGIC;
- eth1g_ram_copi : OUT t_mem_copi;
- eth1g_ram_cipo : IN t_mem_cipo;
+ eth1g_mm_rst : OUT STD_LOGIC;
+ eth1g_tse_copi : OUT t_mem_copi;
+ eth1g_tse_cipo : IN t_mem_cipo;
+ eth1g_reg_copi : OUT t_mem_copi;
+ eth1g_reg_cipo : IN t_mem_cipo;
+ eth1g_reg_interrupt : IN STD_LOGIC;
+ eth1g_ram_copi : OUT t_mem_copi;
+ eth1g_ram_cipo : IN t_mem_cipo;
-- EPCS read
- reg_dpmm_data_copi : OUT t_mem_copi;
- reg_dpmm_data_cipo : IN t_mem_cipo;
- reg_dpmm_ctrl_copi : OUT t_mem_copi;
- reg_dpmm_ctrl_cipo : IN t_mem_cipo;
+ reg_dpmm_data_copi : OUT t_mem_copi;
+ reg_dpmm_data_cipo : IN t_mem_cipo;
+ reg_dpmm_ctrl_copi : OUT t_mem_copi;
+ reg_dpmm_ctrl_cipo : IN t_mem_cipo;
-- EPCS write
- reg_mmdp_data_copi : OUT t_mem_copi;
- reg_mmdp_data_cipo : IN t_mem_cipo;
- reg_mmdp_ctrl_copi : OUT t_mem_copi;
- reg_mmdp_ctrl_cipo : IN t_mem_cipo;
+ reg_mmdp_data_copi : OUT t_mem_copi;
+ reg_mmdp_data_cipo : IN t_mem_cipo;
+ reg_mmdp_ctrl_copi : OUT t_mem_copi;
+ reg_mmdp_ctrl_cipo : IN t_mem_cipo;
-- EPCS status/control
- reg_epcs_copi : OUT t_mem_copi;
- reg_epcs_cipo : IN t_mem_cipo;
+ reg_epcs_copi : OUT t_mem_copi;
+ reg_epcs_cipo : IN t_mem_cipo;
-- Remote Update
- reg_remu_copi : OUT t_mem_copi;
- reg_remu_cipo : IN t_mem_cipo;
+ reg_remu_copi : OUT t_mem_copi;
+ reg_remu_cipo : IN t_mem_cipo;
-- BSN Monitor
- reg_bsn_monitor_v2_ring_rx_copi : OUT t_mem_copi := c_mem_copi_rst;
- reg_bsn_monitor_v2_ring_rx_cipo : IN t_mem_cipo := c_mem_cipo_rst;
+ reg_bsn_monitor_v2_ring_rx_copi : OUT t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_ring_rx_cipo : IN t_mem_cipo := c_mem_cipo_rst;
-- BSN Monitor
- reg_bsn_monitor_v2_ring_tx_copi : OUT t_mem_copi := c_mem_copi_rst;
- reg_bsn_monitor_v2_ring_tx_cipo : IN t_mem_cipo := c_mem_cipo_rst;
+ reg_bsn_monitor_v2_ring_tx_copi : OUT t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_ring_tx_cipo : IN t_mem_cipo := c_mem_cipo_rst;
-- BG
- reg_diag_bg_copi : OUT t_mem_copi;
- reg_diag_bg_cipo : IN t_mem_cipo;
- ram_diag_bg_copi : OUT t_mem_copi;
- ram_diag_bg_cipo : IN t_mem_cipo;
+ reg_diag_bg_copi : OUT t_mem_copi;
+ reg_diag_bg_cipo : IN t_mem_cipo;
+ ram_diag_bg_copi : OUT t_mem_copi;
+ ram_diag_bg_cipo : IN t_mem_cipo;
-- ring_lane_info
reg_ring_lane_info_copi : OUT t_mem_copi;
reg_ring_lane_info_cipo : IN t_mem_cipo;
-- Lane xonoff
- reg_ring_input_select_copi : OUT t_mem_copi;
- reg_ring_input_select_cipo : IN t_mem_cipo;
+ reg_dp_xonoff_lane_copi : OUT t_mem_copi;
+ reg_dp_xonoff_lane_cipo : IN t_mem_cipo;
-- Local xonoff
- reg_dp_xonoff_ring_copi : OUT t_mem_copi;
- reg_dp_xonoff_ring_cipo : IN t_mem_cipo;
+ reg_dp_xonoff_local_copi : OUT t_mem_copi;
+ reg_dp_xonoff_local_cipo : IN t_mem_cipo;
-- Local xonoff
reg_dp_block_validate_err_copi : OUT t_mem_copi;
@@ -212,11 +212,11 @@ BEGIN
u_mm_file_reg_ring_lane_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO")
PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_copi, reg_ring_lane_info_cipo );
- u_mm_file_reg_ring_input_select : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INPUT_SELECT")
- PORT MAP(mm_rst, mm_clk, reg_ring_input_select_copi, reg_ring_input_select_cipo );
+ u_mm_file_reg_dp_xonoff_lane : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LANE")
+ PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_lane_copi, reg_dp_xonoff_lane_cipo );
- u_mm_file_reg_dp_xonoff_ring : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_RING")
- PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_ring_copi, reg_dp_xonoff_ring_cipo );
+ u_mm_file_reg_dp_xonoff_local : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LOCAL")
+ PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_local_copi, reg_dp_xonoff_local_cipo );
u_mm_file_reg_ring_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
PORT MAP(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo);
@@ -424,21 +424,21 @@ BEGIN
reg_ring_lane_info_read_export => reg_ring_lane_info_copi.rd,
reg_ring_lane_info_readdata_export => reg_ring_lane_info_cipo.rddata(c_word_w-1 DOWNTO 0),
- reg_ring_input_select_clk_export => OPEN,
- reg_ring_input_select_reset_export => OPEN,
- reg_ring_input_select_address_export => reg_ring_input_select_copi.address(c_sdp_reg_ring_input_select_addr_w-1 DOWNTO 0),
- reg_ring_input_select_write_export => reg_ring_input_select_copi.wr,
- reg_ring_input_select_writedata_export => reg_ring_input_select_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_ring_input_select_read_export => reg_ring_input_select_copi.rd,
- reg_ring_input_select_readdata_export => reg_ring_input_select_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_dp_xonoff_ring_clk_export => OPEN,
- reg_dp_xonoff_ring_reset_export => OPEN,
- reg_dp_xonoff_ring_address_export => reg_dp_xonoff_ring_copi.address(c_sdp_reg_dp_xonoff_ring_addr_w-1 DOWNTO 0),
- reg_dp_xonoff_ring_write_export => reg_dp_xonoff_ring_copi.wr,
- reg_dp_xonoff_ring_writedata_export => reg_dp_xonoff_ring_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_xonoff_ring_read_export => reg_dp_xonoff_ring_copi.rd,
- reg_dp_xonoff_ring_readdata_export => reg_dp_xonoff_ring_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_xonoff_lane_clk_export => OPEN,
+ reg_dp_xonoff_lane_reset_export => OPEN,
+ reg_dp_xonoff_lane_address_export => reg_dp_xonoff_lane_copi.address(c_sdp_reg_dp_xonoff_lane_addr_w-1 DOWNTO 0),
+ reg_dp_xonoff_lane_write_export => reg_dp_xonoff_lane_copi.wr,
+ reg_dp_xonoff_lane_writedata_export => reg_dp_xonoff_lane_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_xonoff_lane_read_export => reg_dp_xonoff_lane_copi.rd,
+ reg_dp_xonoff_lane_readdata_export => reg_dp_xonoff_lane_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dp_xonoff_local_clk_export => OPEN,
+ reg_dp_xonoff_local_reset_export => OPEN,
+ reg_dp_xonoff_local_address_export => reg_dp_xonoff_local_copi.address(c_sdp_reg_dp_xonoff_local_addr_w-1 DOWNTO 0),
+ reg_dp_xonoff_local_write_export => reg_dp_xonoff_local_copi.wr,
+ reg_dp_xonoff_local_writedata_export => reg_dp_xonoff_local_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_xonoff_local_read_export => reg_dp_xonoff_local_copi.rd,
+ reg_dp_xonoff_local_readdata_export => reg_dp_xonoff_local_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dp_block_validate_err_clk_export => OPEN,
reg_dp_block_validate_err_reset_export => OPEN,
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
index 4f2b1cf59bbd6dd84cee8b51c06adc41b5f0ce91..93ac9db79e3f1c1e2d99536b408fc06886a75ec7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
@@ -113,20 +113,20 @@ PACKAGE qsys_lofar2_unb2b_ring_pkg IS
reg_dp_block_validate_err_reset_export : out std_logic; -- export
reg_dp_block_validate_err_write_export : out std_logic; -- export
reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_input_select_address_export : out std_logic_vector(2 downto 0); -- export
- reg_ring_input_select_clk_export : out std_logic; -- export
- reg_ring_input_select_read_export : out std_logic; -- export
- reg_ring_input_select_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_input_select_reset_export : out std_logic; -- export
- reg_ring_input_select_write_export : out std_logic; -- export
- reg_ring_input_select_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_ring_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_ring_clk_export : out std_logic; -- export
- reg_dp_xonoff_ring_read_export : out std_logic; -- export
- reg_dp_xonoff_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_ring_reset_export : out std_logic; -- export
- reg_dp_xonoff_ring_write_export : out std_logic; -- export
- reg_dp_xonoff_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_xonoff_lane_clk_export : out std_logic; -- export
+ reg_dp_xonoff_lane_read_export : out std_logic; -- export
+ reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_lane_reset_export : out std_logic; -- export
+ reg_dp_xonoff_lane_write_export : out std_logic; -- export
+ reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_xonoff_local_clk_export : out std_logic; -- export
+ reg_dp_xonoff_local_read_export : out std_logic; -- export
+ reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_local_reset_export : out std_logic; -- export
+ reg_dp_xonoff_local_write_export : out std_logic; -- export
+ reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
reg_dpmm_ctrl_clk_export : out std_logic; -- export
reg_dpmm_ctrl_read_export : out std_logic; -- export
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index f47e38de08be73cc3d5376dd80709ae9e7d49acb..aeaa4b503ef02754561922705d2f9803c9444a18 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -349,8 +349,8 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 4;
CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 4;
CONSTANT c_sdp_reg_ring_lane_info_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
- CONSTANT c_sdp_reg_ring_input_select_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max);
- CONSTANT c_sdp_reg_dp_xonoff_ring_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
+ CONSTANT c_sdp_reg_dp_xonoff_lane_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
+ CONSTANT c_sdp_reg_dp_xonoff_local_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
CONSTANT c_sdp_reg_dp_block_validate_err_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 4;
CONSTANT c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
CONSTANT c_sdp_reg_ring_info_addr_w : NATURAL := 2;