diff --git a/libraries/io/i2c/hdllib.cfg b/libraries/io/i2c/hdllib.cfg
index f844cd8696bdada99af7ed351fe271dc0b0d7117..875b18fe4995e251309184b346aa954fef4f98fe 100644
--- a/libraries/io/i2c/hdllib.cfg
+++ b/libraries/io/i2c/hdllib.cfg
@@ -40,7 +40,7 @@ test_bench_files =
$UNB/Firmware/modules/Lofar/i2c/tb/vhdl/tb_i2cslave.vhd
$UNB/Firmware/modules/Lofar/i2c/tb/vhdl/tb_i2c_master.vhd
$UNB/Firmware/modules/Lofar/i2c/tb/vhdl/tb_avs_i2c_master.vhd
- $UNB/Firmware/modules/Lofar/i2c/tb/vhdl/tb_i2c_commander.vhd
+ tb/vhdl/tb_i2c_commander.vhd
tb/vhdl/tb_tb_i2c_commander.vhd
modelsim_copy_files =
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..34692956a6d10c507a072b73ecb32729ca104354
--- /dev/null
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd
@@ -0,0 +1,459 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+
+-- Purpose: Verify the i2c_commander and create a u_protocol_ram init file
+--
+-- Description:
+-- The protocols for the I2C slaves on UNB are stored in the dev_unb_pkg.
+-- The protocols for the I2C slaves on ADU are stored in the dev_adu_pkg.
+-- This tb can model both via g_board = "unb" or "adu". The protocols for the
+-- board are concatenated into c_protocol_ram_init.
+-- The p_mm_stimuli writes the c_protocol_ram_init bytes to u_protocol_ram
+-- and in parallel they get written to a file by u_protocol_ram_init_file:
+--
+-- data/adu_protocol_ram_init.txt
+-- or
+-- data/unb_protocol_ram_init.txt
+--
+-- See data/how_to_create_memory_init_hex_file.txt for how to
+-- create a memory initialization hex file from this.
+--
+-- The p_mm_stimuli continues with executing all protocol lists and checking
+-- the expected results and ASSERTs ERROR if an access went not OK and in
+-- case of read data if the read data value was not OK.
+--
+-- Remark:
+-- . Use c_protocol_ram_init_file="UNUSED" to initialize the u_protocol_ram
+-- with the c_protocol_ram_init sequence,
+-- else use the actual protocol_ram_init.hex file and verify that it contains
+-- the same as the c_protocol_ram_init sequence.
+--
+-- Usage:
+-- > do wave_i2c_commander.do
+-- > run -all
+-- In the Wave Window view the signal u_commander/protocol_index to observe
+-- the progress
+
+
+ENTITY tb_i2c_commander IS
+ GENERIC (
+ g_board : STRING := "adu" -- else default to "unb"
+ --g_board : STRING := "unb"
+ );
+END tb_i2c_commander;
+
+LIBRARY IEEE, common_lib, tst_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE work.i2c_smbus_pkg.ALL;
+USE work.i2c_dev_max1617_pkg.ALL;
+USE work.i2c_dev_adu_pkg.ALL;
+USE work.i2c_dev_unb_pkg.ALL;
+USE work.i2c_pkg.ALL;
+USE work.i2c_commander_pkg.ALL;
+USE work.i2c_commander_aduh_pkg.ALL;
+USE work.i2c_commander_unbh_pkg.ALL;
+
+
+ARCHITECTURE tb OF tb_i2c_commander IS
+
+ CONSTANT c_protocol_ram_init_file : STRING := sel_a_b(g_board="adu", "data/adu_protocol_ram_init.hex", "data/unb_protocol_ram_init.hex");
+ --CONSTANT c_protocol_ram_init_file : STRING := "UNUSED";
+
+ CONSTANT c_use_result_ram : BOOLEAN := TRUE;
+
+ CONSTANT c_sim : BOOLEAN := TRUE; --FALSE
+ --CONSTANT c_sim : BOOLEAN := FALSE;
+ CONSTANT c_clk_freq_in_MHz : NATURAL := 100; -- 100 MHz
+ CONSTANT c_clk_period : TIME := (10**3/c_clk_freq_in_MHz) * 1 ns;
+ CONSTANT c_rst_period : TIME := 4 * c_clk_period;
+
+ CONSTANT c_phy_i2c : t_c_i2c_phy := func_i2c_sel_a_b(c_sim, c_i2c_phy_sim, func_i2c_calculate_phy(c_clk_freq_in_MHz));
+
+ -- Model I2C sensor slaves on the bus
+ CONSTANT ADR_MAX6652 : NATURAL := sel_a_b(g_board="adu", 0, I2C_UNB_MAX6652_ADR);
+ CONSTANT ADR_MAX1617 : NATURAL := sel_a_b(g_board="adu", I2C_ADU_MAX1617_ADR, I2C_UNB_MAX1617_ADR);
+ CONSTANT ADR_PCA9555 : NATURAL := sel_a_b(g_board="adu", I2C_ADU_PCA9555_ADR, 0);
+
+ CONSTANT c_sens_volt_address : STD_LOGIC_VECTOR := TO_UVEC(ADR_MAX6652, 7); -- MAX6652 address GND
+ CONSTANT c_max6652_volt_1v2 : NATURAL := 92; -- 92 * 2.5/192 = 1.2
+ CONSTANT c_max6652_volt_2v5 : NATURAL := 147; -- 147 * 3.3/192 = 2.5
+ CONSTANT c_max6652_volt_nc : NATURAL := 13; -- 13 * 12 /192 = 0.1
+ CONSTANT c_max6652_volt_3v3 : NATURAL := 127; -- 127 * 5.0/192 = 3.3
+ CONSTANT c_max6652_temp : NATURAL := 40;
+
+ --CONSTANT c_sens_temp_address : STD_LOGIC_VECTOR := TO_UVEC(MAX1617_ADR_LOW_MID, 7); -- use other slave address to force I2C errors
+ CONSTANT c_sens_temp_address : STD_LOGIC_VECTOR := TO_UVEC(ADR_MAX1617, 7); -- MAX1618 address MID MID
+ CONSTANT c_max1618_temp : INTEGER := 60;
+
+ CONSTANT c_io_expander_address : STD_LOGIC_VECTOR := TO_UVEC(ADR_PCA9555, 7); -- ADR_PCA9555 address
+
+ -- Select the expected read data arrays for the result data (the read data values are tb dependent, so therefore they are not obtained from a package)
+ CONSTANT c_max1618_expected_data_read_temp_arr : t_i2c_cmdr_natural_arr := (c_max1618_temp, c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x,
+ c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x);
+ CONSTANT c_max6652_expected_data_read_config_arr : t_i2c_cmdr_natural_arr := (c_max6652_volt_1v2, c_max6652_volt_2v5, c_max6652_volt_3v3, c_max6652_temp,
+ c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x);
+
+ CONSTANT c_expected_data_0_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_max1618_expected_data_read_temp_arr, c_max1618_expected_data_read_temp_arr);
+ CONSTANT c_expected_data_1_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_max6652_expected_data_read_config_arr);
+ CONSTANT c_expected_data_2_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ CONSTANT c_expected_data_3_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ CONSTANT c_expected_data_4_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ CONSTANT c_expected_data_5_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ CONSTANT c_expected_data_6_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ CONSTANT c_expected_data_7_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ CONSTANT c_expected_data_8_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ CONSTANT c_expected_data_9_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ CONSTANT c_expected_data_10_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ CONSTANT c_expected_data_11_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ CONSTANT c_expected_data_12_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ CONSTANT c_expected_data_13_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ CONSTANT c_expected_data_14_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ CONSTANT c_expected_data_15_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+
+ CONSTANT c_expected_data_mat : t_i2c_cmdr_natural_mat(0 TO c_i2c_cmdr_max_nof_protocols-1) := (c_expected_data_0_arr,
+ c_expected_data_1_arr,
+ c_expected_data_2_arr,
+ c_expected_data_3_arr,
+ c_expected_data_4_arr,
+ c_expected_data_5_arr,
+ c_expected_data_6_arr,
+ c_expected_data_7_arr,
+ c_expected_data_8_arr,
+ c_expected_data_9_arr,
+ c_expected_data_10_arr,
+ c_expected_data_11_arr,
+ c_expected_data_12_arr,
+ c_expected_data_13_arr,
+ c_expected_data_14_arr,
+ c_expected_data_15_arr);
+
+ -- RAM sizes
+ CONSTANT c_mem_i2c : t_c_i2c_mm := func_i2c_sel_a_b(g_board="adu", c_i2c_cmdr_aduh_i2c_mm, c_i2c_cmdr_unbh_i2c_mm);
+
+ -- Commander parameters
+ CONSTANT c_protocol_ram_init : t_nat_natural_arr := sel_a_b(g_board="adu", c_i2c_cmdr_aduh_protocol_ram_init, c_i2c_cmdr_unbh_protocol_ram_init);
+ CONSTANT c_nof_result_data_arr : t_nat_natural_arr := sel_a_b(g_board="adu", c_i2c_cmdr_aduh_nof_result_data_arr, c_i2c_cmdr_unbh_nof_result_data_arr);
+
+ CONSTANT c_protocol_commander : t_c_i2c_cmdr_commander := func_i2c_cmdr_sel_a_b(g_board="adu", c_i2c_cmdr_aduh_protocol_commander, c_i2c_cmdr_unbh_protocol_commander);
+
+ -- Commander MM register word indexes
+ CONSTANT c_protocol_status_wi : NATURAL := 3*c_protocol_commander.nof_protocols;
+ CONSTANT c_result_error_cnt_wi : NATURAL := 3*c_protocol_commander.nof_protocols + 1;
+ CONSTANT c_result_data_wi : NATURAL := 3*c_protocol_commander.nof_protocols + 2;
+
+
+ -- Test bench PHY
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL rst : STD_LOGIC := '1';
+ SIGNAL sync : STD_LOGIC := '1';
+
+ SIGNAL scl_stretch : STD_LOGIC := 'Z';
+ SIGNAL scl : STD_LOGIC;
+ SIGNAL sda : STD_LOGIC;
+
+ -- IO expander
+ SIGNAL iobank0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
+ SIGNAL iobank1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+ -- IO expander ADU
+ SIGNAL adu_sclk : STD_LOGIC;
+ SIGNAL adu_sdata : STD_LOGIC;
+ SIGNAL adu_led_scs_n : STD_LOGIC;
+ SIGNAL adu_cal_adc : STD_LOGIC;
+ SIGNAL adu_pwr_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL adu_pwr_ctrl_1_dig : STD_LOGIC;
+ SIGNAL adu_pwr_ctrl_0_ana : STD_LOGIC;
+ SIGNAL adu_ctrl : STD_LOGIC_VECTOR(3 DOWNTO 0);
+ SIGNAL adu_ctrl_0_atten_le : STD_LOGIC;
+ SIGNAL adu_ctrl_1_modem_on : STD_LOGIC;
+ SIGNAL adu_ctrl_2_atten_le : STD_LOGIC;
+ SIGNAL adu_ctrl_3_modem_on : STD_LOGIC;
+
+ SIGNAL adu_atten_ctrl : STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+ -- File interface
+ SIGNAL file_miso : t_mem_miso;
+ SIGNAL file_mosi : t_mem_mosi;
+
+ -- MM registers interface
+ SIGNAL commander_miso : t_mem_miso;
+ SIGNAL commander_mosi : t_mem_mosi;
+ SIGNAL protocol_miso : t_mem_miso;
+ SIGNAL protocol_mosi : t_mem_mosi;
+ SIGNAL result_miso : t_mem_miso;
+ SIGNAL result_mosi : t_mem_mosi;
+
+ -- Commander results
+ SIGNAL protocol_data : NATURAL;
+ SIGNAL protocol_status : NATURAL;
+ SIGNAL result_data : NATURAL;
+ SIGNAL result_error_cnt : NATURAL;
+
+BEGIN
+
+ -- run -all
+
+ rst <= '0' AFTER 4*c_clk_period;
+ clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
+
+ -- I2C bus
+ scl <= 'H'; -- model I2C pull up
+ sda <= 'H'; -- model I2C pull up, use '0' and '1' to verify SDA forced low or high error
+
+ scl <= scl_stretch;
+
+ sens_clk_stretch : PROCESS (scl)
+ BEGIN
+ IF falling_edge(scl) THEN
+ scl_stretch <= '0', 'Z' AFTER 50 ns; -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ END IF;
+ END PROCESS;
+
+ u_protocol_ram_init_file : ENTITY tst_lib.tst_output
+ GENERIC MAP (
+ g_file_name => "data/" & g_board & "_protocol_ram_init.txt",
+ g_nof_data => 1,
+ g_data_width => c_byte_w,
+ g_data_type => "UNSIGNED"
+ )
+ PORT MAP (
+ clk => clk,
+ rst => rst,
+ in_dat => file_mosi.wrdata(c_byte_w-1 DOWNTO 0),
+ in_val => file_mosi.wr
+ );
+
+ p_mm_stimuli : PROCESS
+ BEGIN
+ -- Wait for reset release
+ commander_mosi <= c_mem_mosi_rst;
+ file_mosi <= c_mem_mosi_rst;
+ protocol_mosi <= c_mem_mosi_rst;
+ result_mosi <= c_mem_mosi_rst;
+ proc_common_wait_until_low(clk, rst);
+ proc_common_wait_some_cycles(clk, 10);
+
+ ----------------------------------------------------------------------------
+ -- Initialize the u_protocol_ram or verify its default contents
+ ----------------------------------------------------------------------------
+
+ IF c_protocol_ram_init_file="UNUSED" THEN
+ -- Write
+ FOR I IN 0 TO c_protocol_ram_init'LENGTH-1 LOOP
+ proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, protocol_miso, protocol_mosi); -- fill u_protocol_ram
+ END LOOP;
+ FOR I IN c_protocol_ram_init'LENGTH TO c_mem_i2c.protocol_nof_dat-1 LOOP
+ proc_mem_mm_bus_wr(I, SMBUS_C_END, clk, protocol_miso, protocol_mosi); -- fill remainder of u_protocol_ram with default
+ END LOOP;
+
+ ELSE
+ -- Read and verify
+ FOR I IN 0 TO c_protocol_ram_init'LENGTH-1 LOOP
+ proc_mem_mm_bus_rd(I, clk, protocol_miso, protocol_mosi);
+ proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, clk);
+ protocol_data <= TO_UINT(protocol_miso.rddata(c_byte_w-1 DOWNTO 0));
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT c_protocol_ram_init(I)=protocol_data
+ REPORT "Unexpected protocol data" SEVERITY ERROR;
+ END LOOP;
+ FOR I IN c_protocol_ram_init'LENGTH TO c_mem_i2c.protocol_nof_dat-1 LOOP
+ proc_mem_mm_bus_rd(I, clk, protocol_miso, protocol_mosi);
+ proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, clk);
+ protocol_data <= TO_UINT(protocol_miso.rddata(c_byte_w-1 DOWNTO 0));
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT SMBUS_C_END=protocol_data
+ REPORT "Unexpected protocol end data" SEVERITY ERROR;
+ END LOOP;
+ END IF;
+
+ proc_common_wait_some_cycles(clk, 10);
+
+
+ ----------------------------------------------------------------------------
+ -- Create the u_protocol_ram_init_file
+ ----------------------------------------------------------------------------
+
+ FOR I IN 0 TO c_protocol_ram_init'LENGTH-1 LOOP
+ proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, file_miso, file_mosi); -- fill u_protocol_ram_init_file
+ END LOOP;
+ FOR I IN c_protocol_ram_init'LENGTH TO c_mem_i2c.protocol_nof_dat-1 LOOP
+ proc_mem_mm_bus_wr(I, SMBUS_C_END, clk, file_miso, file_mosi); -- fill remainder of u_protocol_ram_init_file with default
+ END LOOP;
+
+ proc_common_wait_some_cycles(clk, 10);
+
+
+ ----------------------------------------------------------------------------
+ -- Try and verify all commander protocols
+ ----------------------------------------------------------------------------
+
+ FOR P IN 0 TO c_protocol_commander.nof_protocols-1 LOOP
+
+ -- Issue protocol list P
+ proc_mem_mm_bus_wr(P, 1, clk, commander_miso, commander_mosi);
+
+ -- Wait for protocol done
+ WHILE protocol_status/=c_i2c_cmdr_state_done LOOP
+ -- read commander protocol status register
+ proc_mem_mm_bus_rd(c_protocol_status_wi, clk, commander_miso, commander_mosi);
+ proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, clk);
+ protocol_status <= TO_UINT(commander_miso.rddata);
+ proc_common_wait_some_cycles(clk, 1);
+ END LOOP;
+
+ -- Read commander result error count
+ proc_mem_mm_bus_rd(c_result_error_cnt_wi, clk, commander_miso, commander_mosi);
+ proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, clk);
+ result_error_cnt <= TO_UINT(commander_miso.rddata);
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT result_error_cnt=0
+ REPORT "The result error count is not 0" SEVERITY ERROR;
+
+ -- Read commander result data
+ FOR I IN 0 TO c_nof_result_data_arr(P)-1 LOOP
+ proc_mem_mm_bus_rd(c_result_data_wi+I, clk, commander_miso, commander_mosi);
+ proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, clk);
+ result_data <= TO_UINT(commander_miso.rddata);
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT c_expected_data_mat(P)(I)=result_data
+ REPORT "Unexpected result data" SEVERITY ERROR;
+ END LOOP;
+
+ -- Wait for protocol idle
+ WHILE protocol_status/=c_i2c_cmdr_state_idle LOOP
+ -- read commander protocol status register
+ proc_mem_mm_bus_rd(c_protocol_status_wi, clk, commander_miso, commander_mosi);
+ proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, clk);
+ protocol_status <= TO_UINT(commander_miso.rddata);
+ proc_common_wait_some_cycles(clk, 1);
+ END LOOP;
+
+ -- Wait some time between the protocols
+ proc_common_wait_some_cycles(clk, 100);
+ END LOOP;
+
+ ----------------------------------------------------------------------------
+ -- The end
+ ----------------------------------------------------------------------------
+
+ proc_common_wait_some_cycles(clk, 100);
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+
+ -- I2C commander
+ u_commander : ENTITY work.i2c_commander
+ GENERIC MAP (
+ g_sim => c_sim,
+ g_i2c_cmdr => c_protocol_commander,
+ g_i2c_mm => c_mem_i2c,
+ g_i2c_phy => c_phy_i2c,
+ g_protocol_ram_init_file => c_protocol_ram_init_file,
+ g_use_result_ram => c_use_result_ram
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ sync => sync,
+
+ ---------------------------------------------------------------------------
+ -- Memory Mapped slave interfaces
+ ---------------------------------------------------------------------------
+ commander_mosi => commander_mosi,
+ commander_miso => commander_miso,
+
+ -- If the default protocol list in u_protocol_ram is fine, then the protocol slave port can be left no connected
+ protocol_mosi => protocol_mosi,
+ protocol_miso => protocol_miso,
+
+ -- Typically the commander status registers are sufficient, so then the results slave port can be left no connected
+ result_mosi => result_mosi,
+ result_miso => result_miso,
+
+ ---------------------------------------------------------------------------
+ -- I2C interface
+ ---------------------------------------------------------------------------
+ scl => scl,
+ sda => sda
+ );
+
+ -- I2C slaves
+ u_sens_volt : ENTITY work.dev_max6652 -- only on "unb"
+ GENERIC MAP (
+ g_address => c_sens_volt_address
+ )
+ PORT MAP (
+ scl => scl,
+ sda => sda,
+ volt_2v5 => c_max6652_volt_1v2,
+ volt_3v3 => c_max6652_volt_2v5,
+ volt_12v => c_max6652_volt_nc,
+ volt_vcc => c_max6652_volt_3v3,
+ temp => c_max6652_temp
+ );
+
+ u_sens_temp : ENTITY work.dev_max1618 -- both on "unb" and on "adu"
+ GENERIC MAP (
+ g_address => c_sens_temp_address
+ )
+ PORT MAP (
+ scl => scl,
+ sda => sda,
+ temp => c_max1618_temp
+ );
+
+ u_io_expander : ENTITY work.dev_pca9555 -- only on "adu"
+ GENERIC MAP (
+ g_address => c_io_expander_address
+ )
+ PORT MAP (
+ scl => scl,
+ sda => sda,
+ iobank0 => iobank0,
+ iobank1 => iobank1
+ );
+
+ -- ADU interpretation of the IO expander outputs
+ adu_sclk <= iobank0(4);
+ adu_sdata <= iobank0(5);
+ adu_led_scs_n <= iobank0(7);
+ adu_cal_adc <= iobank1(7);
+ adu_pwr_ctrl <= iobank0(6) & iobank1(6);
+ adu_pwr_ctrl_1_dig <= adu_pwr_ctrl(1);
+ adu_pwr_ctrl_0_ana <= adu_pwr_ctrl(0);
+
+ adu_ctrl <= iobank0(3 DOWNTO 0);
+ adu_ctrl_0_atten_le <= adu_ctrl(0);
+ adu_ctrl_1_modem_on <= adu_ctrl(1);
+ adu_ctrl_2_atten_le <= adu_ctrl(2);
+ adu_ctrl_3_modem_on <= adu_ctrl(3);
+
+ adu_atten_ctrl <= iobank1(5 DOWNTO 0);
+
+END tb;
+