From 49698ceced963e340761e1e569f9fc8c8be2b101 Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Thu, 5 Nov 2020 10:33:20 +0100
Subject: [PATCH] L2SDP-180, processed review comment 2.
---
.../common/src/vhdl/common_variable_delay.vhd | 35 ++++++++-----------
.../tb/vhdl/tb_common_variable_delay.vhd | 13 +------
2 files changed, 15 insertions(+), 33 deletions(-)
diff --git a/libraries/base/common/src/vhdl/common_variable_delay.vhd b/libraries/base/common/src/vhdl/common_variable_delay.vhd
index d7388c21df..5db4449ca1 100644
--- a/libraries/base/common/src/vhdl/common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_variable_delay.vhd
@@ -54,39 +54,32 @@ ARCHITECTURE rtl OF common_variable_delay IS
SIGNAL nxt_out_val : STD_LOGIC;
SIGNAL delay_cnt : NATURAL;
SIGNAL nxt_delay_cnt : NATURAL;
- SIGNAL in_val_lock : STD_LOGIC := '0';
SIGNAL prev_in_val : STD_LOGIC := '0';
BEGIN
out_val <= i_out_val;
- p_delay: PROCESS(enable, in_val, prev_in_val, in_val_lock, nxt_delay_cnt, delay_cnt, delay, i_out_val)
+ p_delay: PROCESS(enable, in_val, prev_in_val, nxt_delay_cnt, delay_cnt, delay)
BEGIN
-
+ nxt_out_val <= '0';
+ nxt_delay_cnt <= delay_cnt + 1;
+
IF enable = '1' THEN
- IF in_val = '1' AND prev_in_val = '0' THEN -- detect rising_edge of in_val
- in_val_lock <= '1';
- END IF;
-
- IF in_val_lock = '1' THEN
- IF delay_cnt = delay THEN
+ IF in_val = '1' AND prev_in_val = '0' THEN -- detect risingedge of in_val
+ IF delay = 0 THEN
nxt_out_val <= '1';
- END IF;
- nxt_delay_cnt <= delay_cnt + 1;
- ELSE
- nxt_delay_cnt <= 0;
+ nxt_delay_cnt <= g_max_delay;
+ ELSE
+ nxt_delay_cnt <= 1;
+ END IF;
END IF;
- IF i_out_val = '1' THEN
- nxt_out_val <= '0';
- in_val_lock <= '0';
- END IF;
+ IF delay_cnt = delay THEN
+ nxt_out_val <= '1';
+ END IF;
ELSE
- nxt_delay_cnt <= 0;
- nxt_out_val <= '0';
- in_val_lock <= '0';
+ nxt_delay_cnt <= g_max_delay;
END IF;
-
END PROCESS;
p_clk : PROCESS(rst, clk)
diff --git a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
index 41c1d53574..c917a51f13 100644
--- a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
@@ -87,18 +87,7 @@ BEGIN
ASSERT clk_cnt = (c_trigger_latency + delay) REPORT "delay failure, got " & int_to_str(clk_cnt) & ", expect " & int_to_str(c_trigger_latency+delay) SEVERITY ERROR;
proc_common_wait_some_cycles(clk, 10);
END LOOP;
-
- -- If delay > trigger interval, trigger lo-hi shold not start new delay, see also wave window
- delay <= c_trigger_interval+2;
- clk_cnt <= 0;
- proc_common_wait_until_lo_hi(clk, trigger);
- WHILE trigger_dly = '0' LOOP
- clk_cnt <= clk_cnt + 1;
- proc_common_wait_some_cycles(clk, 1);
- END LOOP;
- ASSERT clk_cnt = (c_trigger_latency + delay) REPORT "delay failure, got " & int_to_str(clk_cnt) & ", expect " & int_to_str(c_trigger_latency+delay) SEVERITY ERROR;
- proc_common_wait_some_cycles(clk, 10);
-
+
enable <= '0';
proc_common_wait_some_cycles(clk, 10);
--
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