From 495be1ab0ea90196d1902d881d2696ea28f2a958 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Thu, 25 Aug 2016 07:16:50 +0000
Subject: [PATCH] -Renamed entities.
---
applications/arts/designs/arts_unb1_sc1/hdllib.cfg | 2 +-
.../arts_unb1_sc1/src/vhdl/arts_unb1_sc1.vhd | 14 +++++++-------
.../src/vhdl/arts_unb1_sc1_mm_master.vhd | 6 +++---
.../src/vhdl/arts_unb1_sc1_output.vhd | 6 +++---
.../arts_unb1_sc1/tb/vhdl/tb_arts_unb1_sc1.vhd | 10 +++++-----
5 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/applications/arts/designs/arts_unb1_sc1/hdllib.cfg b/applications/arts/designs/arts_unb1_sc1/hdllib.cfg
index 7a5b8c5f89..8ec2c9e4f0 100644
--- a/applications/arts/designs/arts_unb1_sc1/hdllib.cfg
+++ b/applications/arts/designs/arts_unb1_sc1/hdllib.cfg
@@ -33,7 +33,7 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/arts_unb1_sc1/qsys_mm_master/synthesis/qsys_mm_master.qip
quartus_tcl_files =
- $RADIOHDL/applications/arts/designs/arts_unb1_sc1/quartus/pinning/arts_unb1_sc1_pins.tcl
+ $RADIOHDL/applications/arts/designs/arts_unb1_sc1/quartus/arts_unb1_sc1_pins.tcl
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/applications/arts/designs/arts_unb1_sc1/src/vhdl/arts_unb1_sc1.vhd b/applications/arts/designs/arts_unb1_sc1/src/vhdl/arts_unb1_sc1.vhd
index dca31cea7c..9656955243 100644
--- a/applications/arts/designs/arts_unb1_sc1/src/vhdl/arts_unb1_sc1.vhd
+++ b/applications/arts/designs/arts_unb1_sc1/src/vhdl/arts_unb1_sc1.vhd
@@ -44,7 +44,7 @@ LIBRARY tr_10GbE_lib;
LIBRARY apertif_lib;
USE apertif_lib.apertif_udp_offload_pkg.ALL;
-ENTITY arts_unb1_sc1_bf_offload IS
+ENTITY arts_unb1_sc1 IS
GENERIC (
g_sim : BOOLEAN := FALSE; -- Overridden by simulation test bench
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
@@ -88,9 +88,9 @@ ENTITY arts_unb1_sc1_bf_offload IS
SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_RSTN : OUT STD_LOGIC := '1'
);
-END arts_unb1_sc1_bf_offload;
+END arts_unb1_sc1;
-ARCHITECTURE str OF arts_unb1_sc1_bf_offload IS
+ARCHITECTURE str OF arts_unb1_sc1 IS
-------------------------------------------------------------------------------
-- ARTS SC1
@@ -222,8 +222,8 @@ ARCHITECTURE str OF arts_unb1_sc1_bf_offload IS
-------------------------------------------------------------------------------
-- ctrl_unb1_board
-------------------------------------------------------------------------------
- CONSTANT c_ctrl_unb1_board_design_name : STRING := "arts_unb1_sc1_bf_offload";
- CONSTANT c_ctrl_unb1_board_design_note : STRING := "ARTS SC1 3 10GBE input and BF unit";
+ CONSTANT c_ctrl_unb1_board_design_name : STRING := "arts_unb1_sc1";
+ CONSTANT c_ctrl_unb1_board_design_note : STRING := "ARTS SC1 12-dish, dual pol";
CONSTANT c_use_1GbE : BOOLEAN := TRUE;
CONSTANT c_nof_streams_1GbE : NATURAL := sel_a_b(c_use_1GbE,1,0); --sel_a_b(c_use_1GbE,c_unb2_board_nof_eth,0);
@@ -569,7 +569,7 @@ BEGIN
-- 1GbE packetizing: merge 50 24-subband blocks into one 1200 (16b) word packet
-- . 1200 16b words = 4800 bytes
-------------------------------------------------------------------------------
- u_arts_unb1_sc1_bf_offload_output : ENTITY work.arts_unb1_sc1_bf_offload_output
+ u_arts_unb1_sc1_output : ENTITY work.arts_unb1_sc1_output
GENERIC MAP (
g_nof_streams => c_nof_1GbE_streams,
g_nof_blocks => c_nof_channel_blocks_per_packet,
@@ -700,7 +700,7 @@ BEGIN
-------------------------------------------------------------------------------
-- mm_master
-------------------------------------------------------------------------------
- u_arts_unb1_sc1_bf_offload_mm_master : ENTITY work.arts_unb1_sc1_bf_offload_mm_master
+ u_arts_unb1_sc1_mm_master : ENTITY work.arts_unb1_sc1_mm_master
GENERIC MAP (
g_sim => g_sim
)
diff --git a/applications/arts/designs/arts_unb1_sc1/src/vhdl/arts_unb1_sc1_mm_master.vhd b/applications/arts/designs/arts_unb1_sc1/src/vhdl/arts_unb1_sc1_mm_master.vhd
index c9b37915a2..6bc8684ded 100644
--- a/applications/arts/designs/arts_unb1_sc1/src/vhdl/arts_unb1_sc1_mm_master.vhd
+++ b/applications/arts/designs/arts_unb1_sc1/src/vhdl/arts_unb1_sc1_mm_master.vhd
@@ -40,7 +40,7 @@ USE common_lib.common_network_total_header_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
-ENTITY arts_unb1_sc1_bf_offload_mm_master IS
+ENTITY arts_unb1_sc1_mm_master IS
GENERIC (
g_sim : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0;
@@ -97,8 +97,8 @@ ENTITY arts_unb1_sc1_bf_offload_mm_master IS
reg_dp_xonoff_output_mosi : OUT t_mem_mosi;
reg_dp_xonoff_output_miso : IN t_mem_miso
);
-END arts_unb1_sc1_bf_offload_mm_master;
-ARCHITECTURE str OF arts_unb1_sc1_bf_offload_mm_master IS
+END arts_unb1_sc1_mm_master;
+ARCHITECTURE str OF arts_unb1_sc1_mm_master IS
CONSTANT c_sim_node_type : STRING(1 TO 2) := sel_a_b(g_sim_node_nr<4, "FN", "BN");
CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
diff --git a/applications/arts/designs/arts_unb1_sc1/src/vhdl/arts_unb1_sc1_output.vhd b/applications/arts/designs/arts_unb1_sc1/src/vhdl/arts_unb1_sc1_output.vhd
index 01c7bcd71f..d56173b155 100644
--- a/applications/arts/designs/arts_unb1_sc1/src/vhdl/arts_unb1_sc1_output.vhd
+++ b/applications/arts/designs/arts_unb1_sc1/src/vhdl/arts_unb1_sc1_output.vhd
@@ -35,7 +35,7 @@ USE unb1_board_lib.unb1_board_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-ENTITY arts_unb1_sc1_bf_offload_output IS
+ENTITY arts_unb1_sc1_output IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_nof_streams : POSITIVE := 1;
@@ -64,10 +64,10 @@ ENTITY arts_unb1_sc1_bf_offload_output IS
ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0)
);
-END arts_unb1_sc1_bf_offload_output;
+END arts_unb1_sc1_output;
-ARCHITECTURE wrap OF arts_unb1_sc1_bf_offload_output IS
+ARCHITECTURE wrap OF arts_unb1_sc1_output IS
-- Word align + Eth + IP + UDP + ID + Flags
CONSTANT c_nof_hdr_fields : NATURAL := 1 + 3 + 12 + 4 + 6 + 8 ; -- 34 fields
diff --git a/applications/arts/designs/arts_unb1_sc1/tb/vhdl/tb_arts_unb1_sc1.vhd b/applications/arts/designs/arts_unb1_sc1/tb/vhdl/tb_arts_unb1_sc1.vhd
index 290688ff68..07c4bc2979 100644
--- a/applications/arts/designs/arts_unb1_sc1/tb/vhdl/tb_arts_unb1_sc1.vhd
+++ b/applications/arts/designs/arts_unb1_sc1/tb/vhdl/tb_arts_unb1_sc1.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
-- Purpose:
--- . Feed 3 10GbE 'beamlet' streams to arts_unb1_sc1_bf_offload.
+-- . Feed 3 10GbE 'beamlet' streams to arts_unb1_sc1.
-- Description:
LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, apertif_unb1_fn_bf_emu_lib;
@@ -31,10 +31,10 @@ USE common_lib.common_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
-ENTITY tb_arts_unb1_sc1_bf_offload IS
-END tb_arts_unb1_sc1_bf_offload;
+ENTITY tb_arts_unb1_sc1 IS
+END tb_arts_unb1_sc1;
-ARCHITECTURE tb OF tb_arts_unb1_sc1_bf_offload IS
+ARCHITECTURE tb OF tb_arts_unb1_sc1 IS
CONSTANT c_sim : BOOLEAN := TRUE;
@@ -124,7 +124,7 @@ BEGIN
------------------------------------------------------------------------------
-- ARTS SC1 beamformer
------------------------------------------------------------------------------
- u_arts_unb1_sc1_bf_offload : ENTITY work.arts_unb1_sc1_bf_offload
+ u_arts_unb1_sc1 : ENTITY work.arts_unb1_sc1
GENERIC MAP (
g_sim => c_sim
)
--
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