diff --git a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
index e837236616c834d8503572a1be8bfa966089fc1c..56ea2ac738bb241187f47bfaa0299d4d57741711 100644
--- a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
@@ -66,7 +66,8 @@ ARCHITECTURE rtl OF dp_counter_func_single IS
   --   . range(0,7,2) = [0, 2, 4, 6]
   --   . range(1,7,2) = [1, 3, 5]
   -- . The maximum value is: start+((stop-1-start)/step)*step
-  CONSTANT c_count_max : NATURAL := g_range_start+((g_range_stop-1-g_range_start)/g_range_step)*g_range_step;
+  CONSTANT c_nof_count : NATURAL := (g_range_stop-1-g_range_start)/g_range_step + 1;
+  CONSTANT c_count_max : NATURAL := g_range_start+(c_nof_count-1)*g_range_step;
   CONSTANT c_count_w   : NATURAL := ceil_log2(c_count_max+1);
 
   TYPE t_reg IS RECORD