From 4870f6ccb9ddd1f331d06dce9a6e740075492819 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 28 May 2014 13:45:15 +0000
Subject: [PATCH] Renamed altera_mf prefix into using ip_altera_mf prefix. By
using extra 'ip_' as prefix it is more clear that it is an IP wrapper between
the external IP and the 'tech_' components.
---
.../technology/altera/altera_mf/hdllib.cfg | 20 ++++++++---------
...f_ddio_in.vhd => ip_altera_mf_ddio_in.vhd} | 6 ++---
...ddio_out.vhd => ip_altera_mf_ddio_out.vhd} | 6 ++---
...f_fifo_dc.vhd => ip_altera_mf_fifo_dc.vhd} | 22 +++++++++----------
... => ip_altera_mf_fifo_dc_mixed_widths.vhd} | 22 +++++++++----------
...f_fifo_sc.vhd => ip_altera_mf_fifo_sc.vhd} | 22 +++++++++----------
...m_cr_cw.vhd => ip_altera_mf_ram_cr_cw.vhd} | 18 +++++++--------
...w_crw.vhd => ip_altera_mf_ram_crw_crw.vhd} | 22 +++++++++----------
..._crw.vhd => ip_altera_mf_ram_crwk_crw.vhd} | 22 +++++++++----------
...f_ram_r_w.vhd => ip_altera_mf_ram_r_w.vhd} | 22 +++++++++----------
...ra_mf_rom_r.vhd => ip_altera_mf_rom_r.vhd} | 22 +++++++++----------
.../fifo/tech_fifo_component_pkg.vhd | 6 ++---
libraries/technology/fifo/tech_fifo_dc.vhd | 2 +-
.../fifo/tech_fifo_dc_mixed_widths.vhd | 2 +-
libraries/technology/fifo/tech_fifo_sc.vhd | 2 +-
libraries/technology/memory/hdllib.cfg | 1 +
.../memory/tech_memory_component_pkg.vhd | 10 ++++-----
.../memory/tech_memory_ram_cr_cw.vhd | 2 +-
.../memory/tech_memory_ram_crw_crw.vhd | 2 +-
.../memory/tech_memory_ram_crwk_crw.vhd | 2 +-
.../technology/memory/tech_memory_ram_r_w.vhd | 2 +-
.../technology/memory/tech_memory_rom_r.vhd | 2 +-
22 files changed, 119 insertions(+), 118 deletions(-)
rename libraries/technology/altera/altera_mf/{altera_mf_ddio_in.vhd => ip_altera_mf_ddio_in.vhd} (94%)
rename libraries/technology/altera/altera_mf/{altera_mf_ddio_out.vhd => ip_altera_mf_ddio_out.vhd} (94%)
rename libraries/technology/altera/altera_mf/{altera_mf_fifo_dc.vhd => ip_altera_mf_fifo_dc.vhd} (89%)
rename libraries/technology/altera/altera_mf/{altera_mf_fifo_dc_mixed_widths.vhd => ip_altera_mf_fifo_dc_mixed_widths.vhd} (88%)
rename libraries/technology/altera/altera_mf/{altera_mf_fifo_sc.vhd => ip_altera_mf_fifo_sc.vhd} (88%)
rename libraries/technology/altera/altera_mf/{altera_mf_ram_cr_cw.vhd => ip_altera_mf_ram_cr_cw.vhd} (95%)
rename libraries/technology/altera/altera_mf/{altera_mf_ram_crw_crw.vhd => ip_altera_mf_ram_crw_crw.vhd} (92%)
rename libraries/technology/altera/altera_mf/{altera_mf_ram_crwk_crw.vhd => ip_altera_mf_ram_crwk_crw.vhd} (92%)
rename libraries/technology/altera/altera_mf/{altera_mf_ram_r_w.vhd => ip_altera_mf_ram_r_w.vhd} (91%)
rename libraries/technology/altera/altera_mf/{altera_mf_rom_r.vhd => ip_altera_mf_rom_r.vhd} (88%)
diff --git a/libraries/technology/altera/altera_mf/hdllib.cfg b/libraries/technology/altera/altera_mf/hdllib.cfg
index ecf58de721..a34f038b8a 100644
--- a/libraries/technology/altera/altera_mf/hdllib.cfg
+++ b/libraries/technology/altera/altera_mf/hdllib.cfg
@@ -6,15 +6,15 @@ build_sim_dir = $HDL_BUILD_DIR
build_synth_dir =
synth_files =
- altera_mf_ram_crwk_crw.vhd
- altera_mf_ram_crw_crw.vhd
- altera_mf_ram_cr_cw.vhd
- altera_mf_ram_r_w.vhd
- altera_mf_rom_r.vhd
- altera_mf_fifo_dc_mixed_widths.vhd
- altera_mf_fifo_dc.vhd
- altera_mf_fifo_sc.vhd
- altera_mf_ddio_in.vhd
- altera_mf_ddio_out.vhd
+ ip_altera_mf_ram_crwk_crw.vhd
+ ip_altera_mf_ram_crw_crw.vhd
+ ip_altera_mf_ram_cr_cw.vhd
+ ip_altera_mf_ram_r_w.vhd
+ ip_altera_mf_rom_r.vhd
+ ip_altera_mf_fifo_dc_mixed_widths.vhd
+ ip_altera_mf_fifo_dc.vhd
+ ip_altera_mf_fifo_sc.vhd
+ ip_altera_mf_ddio_in.vhd
+ ip_altera_mf_ddio_out.vhd
test_bench_files =
diff --git a/libraries/technology/altera/altera_mf/altera_mf_ddio_in.vhd b/libraries/technology/altera/altera_mf/ip_altera_mf_ddio_in.vhd
similarity index 94%
rename from libraries/technology/altera/altera_mf/altera_mf_ddio_in.vhd
rename to libraries/technology/altera/altera_mf/ip_altera_mf_ddio_in.vhd
index b81c71806e..0579d09ad4 100644
--- a/libraries/technology/altera/altera_mf/altera_mf_ddio_in.vhd
+++ b/libraries/technology/altera/altera_mf/ip_altera_mf_ddio_in.vhd
@@ -55,7 +55,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.ALL;
-ENTITY altera_mf_ddio_in IS
+ENTITY ip_altera_mf_ddio_in IS
GENERIC(
g_device_family : STRING := "Stratix IV";
g_width : NATURAL := 1
@@ -68,10 +68,10 @@ ENTITY altera_mf_ddio_in IS
out_dat_hi : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
out_dat_lo : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
);
-END altera_mf_ddio_in;
+END ip_altera_mf_ddio_in;
-ARCHITECTURE str OF altera_mf_ddio_in IS
+ARCHITECTURE str OF ip_altera_mf_ddio_in IS
BEGIN
diff --git a/libraries/technology/altera/altera_mf/altera_mf_ddio_out.vhd b/libraries/technology/altera/altera_mf/ip_altera_mf_ddio_out.vhd
similarity index 94%
rename from libraries/technology/altera/altera_mf/altera_mf_ddio_out.vhd
rename to libraries/technology/altera/altera_mf/ip_altera_mf_ddio_out.vhd
index cb4be10ded..ccb5b09188 100644
--- a/libraries/technology/altera/altera_mf/altera_mf_ddio_out.vhd
+++ b/libraries/technology/altera/altera_mf/ip_altera_mf_ddio_out.vhd
@@ -59,7 +59,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.ALL;
-ENTITY altera_mf_ddio_out IS
+ENTITY ip_altera_mf_ddio_out IS
GENERIC(
g_device_family : STRING := "Stratix IV";
g_width : NATURAL := 1
@@ -72,9 +72,9 @@ ENTITY altera_mf_ddio_out IS
in_dat_lo : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
out_dat : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
);
-END altera_mf_ddio_out;
+END ip_altera_mf_ddio_out;
-ARCHITECTURE str OF altera_mf_ddio_out IS
+ARCHITECTURE str OF ip_altera_mf_ddio_out IS
BEGIN
diff --git a/libraries/technology/altera/altera_mf/altera_mf_fifo_dc.vhd b/libraries/technology/altera/altera_mf/ip_altera_mf_fifo_dc.vhd
similarity index 89%
rename from libraries/technology/altera/altera_mf/altera_mf_fifo_dc.vhd
rename to libraries/technology/altera/altera_mf/ip_altera_mf_fifo_dc.vhd
index ae59f38b2b..53066ef46f 100644
--- a/libraries/technology/altera/altera_mf/altera_mf_fifo_dc.vhd
+++ b/libraries/technology/altera/altera_mf/ip_altera_mf_fifo_dc.vhd
@@ -4,7 +4,7 @@
-- MODULE: dcfifo
-- ============================================================
--- File Name: altera_mf_fifo_dc.vhd
+-- File Name: ip_altera_mf_fifo_dc.vhd
-- Megafunction Name(s):
-- dcfifo
--
@@ -42,7 +42,7 @@ USE technology_lib.technology_pkg.ALL;
LIBRARY altera_mf;
USE altera_mf.all;
-ENTITY altera_mf_fifo_dc IS
+ENTITY ip_altera_mf_fifo_dc IS
GENERIC (
g_dat_w : NATURAL;
g_nof_words : NATURAL
@@ -61,10 +61,10 @@ ENTITY altera_mf_fifo_dc IS
wrfull : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
);
-END altera_mf_fifo_dc;
+END ip_altera_mf_fifo_dc;
-ARCHITECTURE SYN OF altera_mf_fifo_dc IS
+ARCHITECTURE SYN OF ip_altera_mf_fifo_dc IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
@@ -214,11 +214,11 @@ END SYN;
-- Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/altera/altera_mf/altera_mf_fifo_dc_mixed_widths.vhd b/libraries/technology/altera/altera_mf/ip_altera_mf_fifo_dc_mixed_widths.vhd
similarity index 88%
rename from libraries/technology/altera/altera_mf/altera_mf_fifo_dc_mixed_widths.vhd
rename to libraries/technology/altera/altera_mf/ip_altera_mf_fifo_dc_mixed_widths.vhd
index 94eb703450..bcceb70065 100644
--- a/libraries/technology/altera/altera_mf/altera_mf_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/altera/altera_mf/ip_altera_mf_fifo_dc_mixed_widths.vhd
@@ -4,7 +4,7 @@
-- MODULE: dcfifo_mixed_widths
-- ============================================================
--- File Name: altera_mf_fifo_dc_mixed_widths.vhd
+-- File Name: ip_altera_mf_fifo_dc_mixed_widths.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
@@ -42,7 +42,7 @@ USE technology_lib.technology_pkg.ALL;
LIBRARY altera_mf;
USE altera_mf.all;
-ENTITY altera_mf_fifo_dc_mixed_widths IS
+ENTITY ip_altera_mf_fifo_dc_mixed_widths IS
GENERIC (
g_nof_words : NATURAL; -- FIFO size in nof wr_dat words
g_wrdat_w : NATURAL;
@@ -62,10 +62,10 @@ ENTITY altera_mf_fifo_dc_mixed_widths IS
wrfull : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
);
-END altera_mf_fifo_dc_mixed_widths;
+END ip_altera_mf_fifo_dc_mixed_widths;
-ARCHITECTURE SYN OF altera_mf_fifo_dc_mixed_widths IS
+ARCHITECTURE SYN OF ip_altera_mf_fifo_dc_mixed_widths IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (q'RANGE);
@@ -221,11 +221,11 @@ END SYN;
-- Retrieval info: CONNECT: rdusedw 0 0 7 0 @rdusedw 0 0 7 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_mixed_widths.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_mixed_widths.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_mixed_widths.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_mixed_widths.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_mixed_widths_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_mixed_widths_waveforms.html FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_mixed_widths_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_mixed_widths.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_mixed_widths.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_mixed_widths.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_mixed_widths.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_mixed_widths_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_mixed_widths_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_mixed_widths_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/altera/altera_mf/altera_mf_fifo_sc.vhd b/libraries/technology/altera/altera_mf/ip_altera_mf_fifo_sc.vhd
similarity index 88%
rename from libraries/technology/altera/altera_mf/altera_mf_fifo_sc.vhd
rename to libraries/technology/altera/altera_mf/ip_altera_mf_fifo_sc.vhd
index 64e8743b51..2526ea171e 100644
--- a/libraries/technology/altera/altera_mf/altera_mf_fifo_sc.vhd
+++ b/libraries/technology/altera/altera_mf/ip_altera_mf_fifo_sc.vhd
@@ -4,7 +4,7 @@
-- MODULE: scfifo
-- ============================================================
--- File Name: altera_mf_fifo_sc.vhd
+-- File Name: ip_altera_mf_fifo_sc.vhd
-- Megafunction Name(s):
-- scfifo
--
@@ -42,7 +42,7 @@ USE technology_lib.technology_pkg.ALL;
LIBRARY altera_mf;
USE altera_mf.all;
-ENTITY altera_mf_fifo_sc IS
+ENTITY ip_altera_mf_fifo_sc IS
GENERIC (
g_use_eab : STRING := "ON";
g_dat_w : NATURAL;
@@ -60,10 +60,10 @@ ENTITY altera_mf_fifo_sc IS
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
);
-END altera_mf_fifo_sc;
+END ip_altera_mf_fifo_sc;
-ARCHITECTURE SYN OF altera_mf_fifo_sc IS
+ARCHITECTURE SYN OF ip_altera_mf_fifo_sc IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (usedw'RANGE);
SIGNAL sub_wire1 : STD_LOGIC ;
@@ -197,10 +197,10 @@ END SYN;
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_sc.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_sc.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_sc.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_sc.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_sc_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_sc_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_sc_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_sc.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_sc.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_sc.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_sc.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_sc_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_sc_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_sc_wave*.jpg FALSE
diff --git a/libraries/technology/altera/altera_mf/altera_mf_ram_cr_cw.vhd b/libraries/technology/altera/altera_mf/ip_altera_mf_ram_cr_cw.vhd
similarity index 95%
rename from libraries/technology/altera/altera_mf/altera_mf_ram_cr_cw.vhd
rename to libraries/technology/altera/altera_mf/ip_altera_mf_ram_cr_cw.vhd
index 31a03e4ed9..cdba78b9b1 100644
--- a/libraries/technology/altera/altera_mf/altera_mf_ram_cr_cw.vhd
+++ b/libraries/technology/altera/altera_mf/ip_altera_mf_ram_cr_cw.vhd
@@ -4,7 +4,7 @@
-- MODULE: altsyncram
-- ============================================================
--- File Name: altera_mf_ram_cr_cw.vhd
+-- File Name: ip_altera_mf_ram_cr_cw.vhd
-- Megafunction Name(s):
-- altsyncram
--
@@ -42,7 +42,7 @@ USE altera_mf.all;
LIBRARY technology_lib;
USE technology_lib.technology_pkg.ALL;
-ENTITY altera_mf_ram_cr_cw IS
+ENTITY ip_altera_mf_ram_cr_cw IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
@@ -62,10 +62,10 @@ ENTITY altera_mf_ram_cr_cw IS
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
);
-END altera_mf_ram_cr_cw;
+END ip_altera_mf_ram_cr_cw;
-ARCHITECTURE SYN OF altera_mf_ram_cr_cw IS
+ARCHITECTURE SYN OF ip_altera_mf_ram_cr_cw IS
CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
@@ -248,9 +248,9 @@ END SYN;
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_cr_cw.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_cr_cw.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_cr_cw.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_cr_cw.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_cr_cw_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_cr_cw.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_cr_cw.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_cr_cw.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_cr_cw.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_cr_cw_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/altera/altera_mf/altera_mf_ram_crw_crw.vhd b/libraries/technology/altera/altera_mf/ip_altera_mf_ram_crw_crw.vhd
similarity index 92%
rename from libraries/technology/altera/altera_mf/altera_mf_ram_crw_crw.vhd
rename to libraries/technology/altera/altera_mf/ip_altera_mf_ram_crw_crw.vhd
index 4475797dcf..17dde5f44a 100644
--- a/libraries/technology/altera/altera_mf/altera_mf_ram_crw_crw.vhd
+++ b/libraries/technology/altera/altera_mf/ip_altera_mf_ram_crw_crw.vhd
@@ -4,7 +4,7 @@
-- MODULE: altsyncram
-- ============================================================
--- File Name: altera_mf_ram_crw_crw.vhd
+-- File Name: ip_altera_mf_ram_crw_crw.vhd
-- Megafunction Name(s):
-- altsyncram
--
@@ -42,7 +42,7 @@ USE altera_mf.all;
LIBRARY technology_lib;
USE technology_lib.technology_pkg.ALL;
-ENTITY altera_mf_ram_crw_crw IS
+ENTITY ip_altera_mf_ram_crw_crw IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
@@ -67,10 +67,10 @@ ENTITY altera_mf_ram_crw_crw IS
q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
);
-END altera_mf_ram_crw_crw;
+END ip_altera_mf_ram_crw_crw;
-ARCHITECTURE SYN OF altera_mf_ram_crw_crw IS
+ARCHITECTURE SYN OF ip_altera_mf_ram_crw_crw IS
FUNCTION sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING IS
BEGIN
@@ -304,11 +304,11 @@ END SYN;
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0
-- Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crw_crw.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crw_crw.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crw_crw.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crw_crw.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crw_crw_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crw_crw_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crw_crw_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crw_crw.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crw_crw.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crw_crw.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crw_crw.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crw_crw_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crw_crw_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crw_crw_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/altera/altera_mf/altera_mf_ram_crwk_crw.vhd b/libraries/technology/altera/altera_mf/ip_altera_mf_ram_crwk_crw.vhd
similarity index 92%
rename from libraries/technology/altera/altera_mf/altera_mf_ram_crwk_crw.vhd
rename to libraries/technology/altera/altera_mf/ip_altera_mf_ram_crwk_crw.vhd
index 30cbe657d2..4bd7dcc9cf 100644
--- a/libraries/technology/altera/altera_mf/altera_mf_ram_crwk_crw.vhd
+++ b/libraries/technology/altera/altera_mf/ip_altera_mf_ram_crwk_crw.vhd
@@ -4,7 +4,7 @@
-- MODULE: altsyncram
-- ============================================================
--- File Name: altera_mf_ram_crwk_crw.vhd
+-- File Name: ip_altera_mf_ram_crwk_crw.vhd
-- Megafunction Name(s):
-- altsyncram
--
@@ -42,7 +42,7 @@ USE altera_mf.all;
LIBRARY technology_lib;
USE technology_lib.technology_pkg.ALL;
-ENTITY altera_mf_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
+ENTITY ip_altera_mf_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
GENERIC (
g_adr_a_w : NATURAL := 5;
g_dat_a_w : NATURAL := 32;
@@ -70,10 +70,10 @@ ENTITY altera_mf_ram_crwk_crw IS -- support different port data widths and corr
q_a : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
);
-END altera_mf_ram_crwk_crw;
+END ip_altera_mf_ram_crwk_crw;
-ARCHITECTURE SYN OF altera_mf_ram_crwk_crw IS
+ARCHITECTURE SYN OF ip_altera_mf_ram_crwk_crw IS
FUNCTION sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING IS
BEGIN
@@ -310,11 +310,11 @@ END SYN;
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crwk_crw.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crwk_crw.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crwk_crw.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crwk_crw.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crwk_crw_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crwk_crw_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crwk_crw_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crwk_crw.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crwk_crw.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crwk_crw.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crwk_crw.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crwk_crw_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crwk_crw_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crwk_crw_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/altera/altera_mf/altera_mf_ram_r_w.vhd b/libraries/technology/altera/altera_mf/ip_altera_mf_ram_r_w.vhd
similarity index 91%
rename from libraries/technology/altera/altera_mf/altera_mf_ram_r_w.vhd
rename to libraries/technology/altera/altera_mf/ip_altera_mf_ram_r_w.vhd
index bbf5fa788a..7dc33c5b68 100644
--- a/libraries/technology/altera/altera_mf/altera_mf_ram_r_w.vhd
+++ b/libraries/technology/altera/altera_mf/ip_altera_mf_ram_r_w.vhd
@@ -4,7 +4,7 @@
-- MODULE: altsyncram
-- ============================================================
--- File Name: altera_mf_ram_r_w.vhd
+-- File Name: ip_altera_mf_ram_r_w.vhd
-- Megafunction Name(s):
-- altsyncram
--
@@ -39,7 +39,7 @@ USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
-ENTITY altera_mf_ram_r_w IS
+ENTITY ip_altera_mf_ram_r_w IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
@@ -55,10 +55,10 @@ ENTITY altera_mf_ram_r_w IS
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
);
-END altera_mf_ram_r_w;
+END ip_altera_mf_ram_r_w;
-ARCHITECTURE SYN OF altera_mf_ram_r_w IS
+ARCHITECTURE SYN OF ip_altera_mf_ram_r_w IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
@@ -232,11 +232,11 @@ END SYN;
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_r_w.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_r_w.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_r_w.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_r_w.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_r_w_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_r_w_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_r_w_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_r_w.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_r_w.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_r_w.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_r_w.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_r_w_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_r_w_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_r_w_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/altera/altera_mf/altera_mf_rom_r.vhd b/libraries/technology/altera/altera_mf/ip_altera_mf_rom_r.vhd
similarity index 88%
rename from libraries/technology/altera/altera_mf/altera_mf_rom_r.vhd
rename to libraries/technology/altera/altera_mf/ip_altera_mf_rom_r.vhd
index be557f869c..361017f809 100644
--- a/libraries/technology/altera/altera_mf/altera_mf_rom_r.vhd
+++ b/libraries/technology/altera/altera_mf/ip_altera_mf_rom_r.vhd
@@ -4,7 +4,7 @@
-- MODULE: altsyncram
-- ============================================================
--- File Name: altera_mf_rom_r.vhd
+-- File Name: ip_altera_mf_rom_r.vhd
-- Megafunction Name(s):
-- altsyncram
--
@@ -39,7 +39,7 @@ USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
-ENTITY altera_mf_rom_r IS
+ENTITY ip_altera_mf_rom_r IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
@@ -52,10 +52,10 @@ ENTITY altera_mf_rom_r IS
clken : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
);
-END altera_mf_rom_r;
+END ip_altera_mf_rom_r;
-ARCHITECTURE SYN OF altera_mf_rom_r IS
+ARCHITECTURE SYN OF ip_altera_mf_rom_r IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
@@ -169,11 +169,11 @@ END SYN;
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_rom_r.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_rom_r.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_rom_r.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_rom_r.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_rom_r_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_rom_r_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_rom_r_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_rom_r.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_rom_r.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_rom_r.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_rom_r.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_rom_r_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_rom_r_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_rom_r_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/fifo/tech_fifo_component_pkg.vhd b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
index f079c248b5..cff9af9b3a 100644
--- a/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+++ b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
@@ -31,7 +31,7 @@ PACKAGE tech_fifo_component_pkg IS
-- altera_mf
-----------------------------------------------------------------------------
- COMPONENT altera_mf_fifo_sc IS
+ COMPONENT ip_altera_mf_fifo_sc IS
GENERIC (
g_use_eab : STRING := "ON";
g_dat_w : NATURAL;
@@ -50,7 +50,7 @@ PACKAGE tech_fifo_component_pkg IS
);
END COMPONENT;
- COMPONENT altera_mf_fifo_dc IS
+ COMPONENT ip_altera_mf_fifo_dc IS
GENERIC (
g_dat_w : NATURAL;
g_nof_words : NATURAL
@@ -70,7 +70,7 @@ PACKAGE tech_fifo_component_pkg IS
);
END COMPONENT;
- COMPONENT altera_mf_fifo_dc_mixed_widths IS
+ COMPONENT ip_altera_mf_fifo_dc_mixed_widths IS
GENERIC (
g_nof_words : NATURAL; -- FIFO size in nof wr_dat words
g_wrdat_w : NATURAL;
diff --git a/libraries/technology/fifo/tech_fifo_dc.vhd b/libraries/technology/fifo/tech_fifo_dc.vhd
index 0fc4fb6867..74826118f5 100644
--- a/libraries/technology/fifo/tech_fifo_dc.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc.vhd
@@ -55,7 +55,7 @@ ARCHITECTURE str OF tech_fifo_dc IS
BEGIN
gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : altera_mf_fifo_dc
+ u0 : ip_altera_mf_fifo_dc
GENERIC MAP (g_dat_w, g_nof_words)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
diff --git a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
index c5be5143fd..5ad453b054 100644
--- a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
@@ -56,7 +56,7 @@ ARCHITECTURE str OF tech_fifo_dc_mixed_widths IS
BEGIN
gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : altera_mf_fifo_dc_mixed_widths
+ u0 : ip_altera_mf_fifo_dc_mixed_widths
GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
diff --git a/libraries/technology/fifo/tech_fifo_sc.vhd b/libraries/technology/fifo/tech_fifo_sc.vhd
index 84b89f4395..8fe25fc017 100644
--- a/libraries/technology/fifo/tech_fifo_sc.vhd
+++ b/libraries/technology/fifo/tech_fifo_sc.vhd
@@ -54,7 +54,7 @@ ARCHITECTURE str OF tech_fifo_sc IS
BEGIN
gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : altera_mf_fifo_sc
+ u0 : ip_altera_mf_fifo_sc
GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
END GENERATE;
diff --git a/libraries/technology/memory/hdllib.cfg b/libraries/technology/memory/hdllib.cfg
index 377b160488..759bc105aa 100644
--- a/libraries/technology/memory/hdllib.cfg
+++ b/libraries/technology/memory/hdllib.cfg
@@ -11,5 +11,6 @@ synth_files =
tech_memory_ram_crw_crw.vhd
tech_memory_ram_crwk_crw.vhd
tech_memory_ram_r_w.vhd
+ tech_memory_rom_r.vhd
test_bench_files =
diff --git a/libraries/technology/memory/tech_memory_component_pkg.vhd b/libraries/technology/memory/tech_memory_component_pkg.vhd
index c45c6883ac..2cbe4a2626 100644
--- a/libraries/technology/memory/tech_memory_component_pkg.vhd
+++ b/libraries/technology/memory/tech_memory_component_pkg.vhd
@@ -30,7 +30,7 @@ PACKAGE tech_memory_component_pkg IS
-- altera_mf
-----------------------------------------------------------------------------
- COMPONENT altera_mf_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
+ COMPONENT ip_altera_mf_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
GENERIC (
g_adr_a_w : NATURAL := 5;
g_dat_a_w : NATURAL := 32;
@@ -59,7 +59,7 @@ PACKAGE tech_memory_component_pkg IS
);
END COMPONENT;
- COMPONENT altera_mf_ram_crw_crw IS
+ COMPONENT ip_altera_mf_ram_crw_crw IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
@@ -85,7 +85,7 @@ PACKAGE tech_memory_component_pkg IS
);
END COMPONENT;
- COMPONENT altera_mf_ram_cr_cw IS
+ COMPONENT ip_altera_mf_ram_cr_cw IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
@@ -106,7 +106,7 @@ PACKAGE tech_memory_component_pkg IS
);
END COMPONENT;
- COMPONENT altera_mf_ram_r_w IS
+ COMPONENT ip_altera_mf_ram_r_w IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
@@ -124,7 +124,7 @@ PACKAGE tech_memory_component_pkg IS
);
END COMPONENT;
- COMPONENT altera_mf_rom_r IS
+ COMPONENT ip_altera_mf_rom_r IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index 184de5f57f..38057d929e 100644
--- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -56,7 +56,7 @@ ARCHITECTURE str OF tech_memory_ram_cr_cw IS
BEGIN
gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : altera_mf_ram_cr_cw
+ u0 : ip_altera_mf_ram_cr_cw
GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (data, rdaddress, rdclock, rdclocken, wraddress, wrclock, wrclocken, wren, q);
END GENERATE;
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index 786ab45cc2..9c43aebec6 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -63,7 +63,7 @@ ARCHITECTURE str OF tech_memory_ram_crw_crw IS
BEGIN
gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : altera_mf_ram_crw_crw
+ u0 : ip_altera_mf_ram_crw_crw
GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index ce3e4919b9..050f87fc64 100644
--- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -65,7 +65,7 @@ ARCHITECTURE str OF tech_memory_ram_crwk_crw IS
BEGIN
gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : altera_mf_ram_crwk_crw
+ u0 : ip_altera_mf_ram_crwk_crw
GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
diff --git a/libraries/technology/memory/tech_memory_ram_r_w.vhd b/libraries/technology/memory/tech_memory_ram_r_w.vhd
index 162e9f7cae..f0bec3b79a 100644
--- a/libraries/technology/memory/tech_memory_ram_r_w.vhd
+++ b/libraries/technology/memory/tech_memory_ram_r_w.vhd
@@ -53,7 +53,7 @@ ARCHITECTURE str OF tech_memory_ram_r_w IS
BEGIN
gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : altera_mf_ram_r_w
+ u0 : ip_altera_mf_ram_r_w
GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_init_file)
PORT MAP (clock, enable, data, rdaddress, wraddress, wren, q);
END GENERATE;
diff --git a/libraries/technology/memory/tech_memory_rom_r.vhd b/libraries/technology/memory/tech_memory_rom_r.vhd
index 4702c46f54..263aa34206 100644
--- a/libraries/technology/memory/tech_memory_rom_r.vhd
+++ b/libraries/technology/memory/tech_memory_rom_r.vhd
@@ -49,7 +49,7 @@ ARCHITECTURE str OF tech_memory_rom_r IS
BEGIN
gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : altera_mf_rom_r
+ u0 : ip_altera_mf_rom_r
GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_init_file)
PORT MAP (address, clock, clken, q);
END GENERATE;
--
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