From 47e9a8c14df157ad343556753b9320abc3a71a8d Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Mon, 3 Apr 2023 10:46:28 +0200
Subject: [PATCH] processed review comments
---
.../axi4/src/vhdl/axi4_lite_mm_bridge.vhd | 19 +++++++++++--------
.../base/axi4/src/vhdl/axi4_lite_pkg.vhd | 2 --
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
index 6c50c09f77..a763e876a9 100644
--- a/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
@@ -48,17 +48,19 @@ ENTITY axi4_lite_mm_bridge IS
aresetn : OUT STD_LOGIC := '1'; -- AXI4 active-low reset
mm_rst : OUT STD_LOGIC := '0'; -- MM active-high reset
+ -- Translate AXI4 lite to MM
axi4_in_copi : IN t_axi4_lite_copi := c_axi4_lite_copi_rst;
axi4_in_cipo : OUT t_axi4_lite_cipo := c_axi4_lite_cipo_rst;
- axi4_out_copi : OUT t_axi4_lite_copi := c_axi4_lite_copi_rst;
- axi4_out_cipo : IN t_axi4_lite_cipo := c_axi4_lite_cipo_rst;
+ mm_out_copi : OUT t_mem_copi := c_mem_copi_rst;
+ mm_out_cipo : IN t_mem_cipo := c_mem_cipo_rst;
- mm_in_copi : IN t_mem_copi := c_mem_copi_rst;
- mm_in_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ -- Translate MM to AXI4 lite
+ mm_in_copi : IN t_mem_copi := c_mem_copi_rst;
+ mm_in_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
- mm_out_copi : OUT t_mem_copi := c_mem_copi_rst;
- mm_out_cipo : IN t_mem_cipo := c_mem_cipo_rst
+ axi4_out_copi : OUT t_axi4_lite_copi := c_axi4_lite_copi_rst;
+ axi4_out_cipo : IN t_axi4_lite_cipo := c_axi4_lite_cipo_rst
);
END axi4_lite_mm_bridge;
@@ -66,7 +68,7 @@ ARCHITECTURE str OF axi4_lite_mm_bridge IS
-- Sum of all t_mem_copi fields widths (synthesis will optimize away unused address and data bits)
CONSTANT c_data_w : NATURAL := c_mem_address_w + c_mem_data_w + 2; -- 32 + 72 + 1 (wr) + 1 (rd) = 106
- SIGNAL i_rst : STD_LOGIC := '0'; -- Internal active high reset.
+ SIGNAL i_rst : STD_LOGIC := '0';
SIGNAL axi4_from_mm_copi : t_mem_copi;
SIGNAL axi4_from_mm_cipo : t_mem_cipo;
@@ -166,7 +168,8 @@ BEGIN
-- Generate bvalid
q_bvalid <= d_bvalid WHEN rising_edge(in_clk);
- p_bvalid : PROCESS(i_rst, mm_from_axi4_cipo, mm_from_axi4_copi, axi4_in_copi)
+
+ p_bvalid : PROCESS(i_rst, q_bvalid, mm_from_axi4_cipo, mm_from_axi4_copi, axi4_in_copi)
BEGIN
d_bvalid <= q_bvalid;
IF mm_from_axi4_cipo.waitrequest = '0' AND mm_from_axi4_copi.wr = '1' THEN
diff --git a/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
index 67581a5384..497c8c9068 100644
--- a/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
@@ -40,8 +40,6 @@ PACKAGE axi4_lite_pkg IS
------------------------------------------------------------------------------
-- Simple AXI4 lite memory access (for MM control interface)
------------------------------------------------------------------------------
- CONSTANT c_max_string : NATURAL := 128;
-
CONSTANT c_axi4_lite_address_w : NATURAL := 32;
CONSTANT c_axi4_lite_data_w : NATURAL := 32;
CONSTANT c_axi4_lite_prot_w : NATURAL := 3;
--
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