From 47c53ea8e12a45a7d59e1dd2aeae83fe66a80962 Mon Sep 17 00:00:00 2001
From: Jonathan Hargreaves <hargreaves@astron.nl>
Date: Mon, 1 Feb 2016 10:40:56 +0000
Subject: [PATCH] Ten GbE pll ip for arria 10 e3sge3 (unb2a) device
---
.../transceiver_pll_10g/compile_ip.tcl | 49 +++++
.../transceiver_pll_10g/generate_ip.sh | 44 ++++
.../transceiver_pll_10g/hdllib.cfg | 16 ++
...ip_arria10_e3sge3_transceiver_pll_10g.qsys | 195 ++++++++++++++++++
4 files changed, 304 insertions(+)
create mode 100644 libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
create mode 100755 libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generate_ip.sh
create mode 100644 libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
create mode 100644 libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/ip_arria10_e3sge3_transceiver_pll_10g.qsys
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
new file mode 100644
index 0000000000..b4e0ebc532
--- /dev/null
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
@@ -0,0 +1,49 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generated/sim"
+
+#vlib ./work/ ;# Assume library work already exists
+
+vmap ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151 ./work/
+
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_151/sim/twentynm_xcvr_avmm.sv" -work ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_151/sim/mentor/twentynm_xcvr_avmm.sv" -work ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_151/sim/alt_xcvr_resync.sv" -work ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_151/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_151/sim/a10_avmm_h.sv" -work ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_151/sim/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_151/sim/altera_xcvr_atx_pll_a10.sv" -work ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_151/sim/a10_xcvr_atx_pll.sv" -work ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_151/sim/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_151/sim/alt_xcvr_pll_avmm_csr.sv" -work ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_151/sim/mentor/altera_xcvr_atx_pll_a10.sv" -work ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_151/sim/mentor/a10_xcvr_atx_pll.sv" -work ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_151/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_151/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ vcom "$IP_DIR/ip_arria10_e3sge3_transceiver_pll_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generate_ip.sh
new file mode 100755
index 0000000000..5461170236
--- /dev/null
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2a
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e3sge3_transceiver_pll_10g.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
new file mode 100644
index 0000000000..ca0096f0c4
--- /dev/null
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e3sge3_transceiver_pll_10g
+hdl_library_clause_name = ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+
+hdl_lib_technology = ip_arria10_e3sge3
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
+
+synth_files =
+
+test_bench_files =
+
+quartus_qip_files =
+ generated/ip_arria10_e3sge3_transceiver_pll_10g.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/ip_arria10_e3sge3_transceiver_pll_10g.qsys b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/ip_arria10_e3sge3_transceiver_pll_10g.qsys
new file mode 100644
index 0000000000..9b4e439ea7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/ip_arria10_e3sge3_transceiver_pll_10g.qsys
@@ -0,0 +1,195 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element xcvr_atx_pll_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115U4F45E3SGE3" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="3" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="mcgb_rst"
+ internal="xcvr_atx_pll_a10_0.mcgb_rst"
+ type="conduit"
+ dir="end">
+ <port name="mcgb_rst" internal="mcgb_rst" />
+ </interface>
+ <interface
+ name="mcgb_serial_clk"
+ internal="xcvr_atx_pll_a10_0.mcgb_serial_clk"
+ type="hssi_serial_clock"
+ dir="start">
+ <port name="mcgb_serial_clk" internal="mcgb_serial_clk" />
+ </interface>
+ <interface
+ name="pll_cal_busy"
+ internal="xcvr_atx_pll_a10_0.pll_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="pll_cal_busy" internal="pll_cal_busy" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="xcvr_atx_pll_a10_0.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="xcvr_atx_pll_a10_0.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_refclk0"
+ internal="xcvr_atx_pll_a10_0.pll_refclk0"
+ type="clock"
+ dir="end">
+ <port name="pll_refclk0" internal="pll_refclk0" />
+ </interface>
+ <interface
+ name="reconfig_avmm0"
+ internal="xcvr_atx_pll_a10_0.reconfig_avmm0"
+ type="avalon"
+ dir="end">
+ <port name="reconfig_write0" internal="reconfig_write0" />
+ <port name="reconfig_read0" internal="reconfig_read0" />
+ <port name="reconfig_address0" internal="reconfig_address0" />
+ <port name="reconfig_writedata0" internal="reconfig_writedata0" />
+ <port name="reconfig_readdata0" internal="reconfig_readdata0" />
+ <port name="reconfig_waitrequest0" internal="reconfig_waitrequest0" />
+ </interface>
+ <interface
+ name="reconfig_clk0"
+ internal="xcvr_atx_pll_a10_0.reconfig_clk0"
+ type="clock"
+ dir="end">
+ <port name="reconfig_clk0" internal="reconfig_clk0" />
+ </interface>
+ <interface
+ name="reconfig_reset0"
+ internal="xcvr_atx_pll_a10_0.reconfig_reset0"
+ type="reset"
+ dir="end">
+ <port name="reconfig_reset0" internal="reconfig_reset0" />
+ </interface>
+ <interface
+ name="tx_serial_clk"
+ internal="xcvr_atx_pll_a10_0.tx_serial_clk"
+ type="hssi_serial_clock"
+ dir="start">
+ <port name="tx_serial_clk" internal="tx_serial_clk" />
+ </interface>
+ <module
+ name="xcvr_atx_pll_a10_0"
+ kind="altera_xcvr_atx_pll_a10"
+ version="15.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="base_device" value="NIGHTFURY5ES" />
+ <parameter name="bw_sel" value="low" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="enable_16G_path" value="0" />
+ <parameter name="enable_8G_path" value="1" />
+ <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
+ <parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_cascade_out" value="0" />
+ <parameter name="enable_debug_ports_parameters" value="0" />
+ <parameter name="enable_fb_comp_bonding" value="0" />
+ <parameter name="enable_fractional" value="0" />
+ <parameter name="enable_hfreq_clk" value="1" />
+ <parameter name="enable_hip_cal_done_port" value="0" />
+ <parameter name="enable_manual_configuration" value="1" />
+ <parameter name="enable_mcgb" value="1" />
+ <parameter name="enable_mcgb_pcie_clksw" value="0" />
+ <parameter name="enable_pcie_clk" value="0" />
+ <parameter name="enable_pld_atx_cal_busy_port" value="1" />
+ <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+ <parameter name="enable_pll_reconfig" value="1" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="mcgb_aux_clkin_cnt" value="0" />
+ <parameter name="mcgb_div" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="pma_width" value="64" />
+ <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
+ <parameter name="prot_mode" value="Basic" />
+ <parameter name="rcfg_debug" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="1" />
+ <parameter name="rcfg_jtag_enable" value="1" />
+ <parameter name="rcfg_mif_file_enable" value="1" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_param_vals1" value="" />
+ <parameter name="rcfg_param_vals2" value="" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_sv_file_enable" value="1" />
+ <parameter name="rcfg_txt_file_enable" value="0" />
+ <parameter name="refclk_cnt" value="1" />
+ <parameter name="refclk_index" value="0" />
+ <parameter name="select_manual_config" value="false" />
+ <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
+ <parameter name="set_auto_reference_clock_frequency" value="644.53125" />
+ <parameter name="set_capability_reg_enable" value="1" />
+ <parameter name="set_csr_soft_logic_enable" value="1" />
+ <parameter name="set_fref_clock_frequency" value="100.0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_k_counter" value="1" />
+ <parameter name="set_l_cascade_counter" value="4" />
+ <parameter name="set_l_counter" value="2" />
+ <parameter name="set_m_counter" value="1" />
+ <parameter name="set_manual_reference_clock_frequency" value="100.0" />
+ <parameter name="set_output_clock_frequency" value="5156.25" />
+ <parameter name="set_ref_clk_div" value="1" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="silicon_rev" value="false" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="test_mode" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
--
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