From 4750ad20ab0905c93ee94f6b64eaf90b8b0de84e Mon Sep 17 00:00:00 2001 From: Zanting <zanting> Date: Wed, 30 Sep 2015 07:15:15 +0000 Subject: [PATCH] IP for 16GB DDR3 So-Dimm modules added --- .../technology/ddr/tech_ddr_component_pkg.vhd | 140 ++++++++++++------ 1 file changed, 96 insertions(+), 44 deletions(-) diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd index f536709936..64718833ce 100644 --- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd +++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd @@ -190,50 +190,102 @@ PACKAGE tech_ddr_component_pkg IS -- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave IS PORT ( - pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk - global_reset_n : IN STD_LOGIC; -- global_reset.reset_n - soft_reset_n : IN STD_LOGIC; -- soft_reset.reset_n - afi_clk : OUT STD_LOGIC; -- afi_clk_in.clk - afi_half_clk : OUT STD_LOGIC; -- afi_half_clk_in.clk - afi_reset_n : OUT STD_LOGIC; -- afi_reset_in.reset_n - mem_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- memory.mem_a - mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba - mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck - mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n - mem_cke : OUT STD_LOGIC; -- .mem_cke - mem_cs_n : OUT STD_LOGIC; -- .mem_cs_n - mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm - mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n - mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n - mem_we_n : OUT STD_LOGIC; -- .mem_we_n - mem_reset_n : OUT STD_LOGIC; -- .mem_reset_n - mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq - mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs - mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n - mem_odt : OUT STD_LOGIC; -- .mem_odt - avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n - avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer - avl_addr : IN STD_LOGIC_VECTOR(26 DOWNTO 0); -- .address - avl_rdata_valid : OUT STD_LOGIC; -- .readdatavalid - avl_rdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); -- .readdata - avl_wdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); -- .writedata - avl_be : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- .byteenable - avl_read_req : IN STD_LOGIC; -- .read - avl_write_req : IN STD_LOGIC; -- .write - avl_size : IN STD_LOGIC_VECTOR(6 DOWNTO 0); -- .burstcount - local_init_done : OUT STD_LOGIC; -- status.local_init_done - local_cal_success : OUT STD_LOGIC; -- .local_cal_success - local_cal_fail : OUT STD_LOGIC; -- .local_cal_fail - seriesterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0); -- oct_sharing.seriesterminationcontrol - parallelterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0); -- .parallelterminationcontrol - pll_mem_clk : OUT STD_LOGIC; -- pll_sharing.pll_mem_clk - pll_write_clk : OUT STD_LOGIC; -- .pll_write_clk - pll_write_clk_pre_phy_clk : OUT STD_LOGIC; -- .pll_write_clk_pre_phy_clk - pll_addr_cmd_clk : OUT STD_LOGIC; -- .pll_addr_cmd_clk - pll_locked : OUT STD_LOGIC; -- .pll_locked - pll_avl_clk : OUT STD_LOGIC; -- .pll_avl_clk - pll_config_clk : OUT STD_LOGIC; -- .pll_config_clk - dll_delayctrl : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) -- dll_sharing.dll_delayctrl + pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk + global_reset_n : IN STD_LOGIC; -- global_reset.reset_n + soft_reset_n : IN STD_LOGIC; -- soft_reset.reset_n + afi_clk : IN STD_LOGIC; -- afi_clk_in.clk + afi_half_clk : IN STD_LOGIC; -- afi_half_clk_in.clk + afi_reset_n : IN STD_LOGIC; -- afi_reset_in.reset_n + mem_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- memory.mem_a + mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba + mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck + mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n + mem_cke : OUT STD_LOGIC; -- .mem_cke + mem_cs_n : OUT STD_LOGIC; -- .mem_cs_n + mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm + mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n + mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n + mem_we_n : OUT STD_LOGIC; -- .mem_we_n + mem_reset_n : OUT STD_LOGIC; -- .mem_reset_n + mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq + mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs + mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n + mem_odt : OUT STD_LOGIC; -- .mem_odt + avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n + avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer + avl_addr : IN STD_LOGIC_VECTOR(26 DOWNTO 0); -- .address + avl_rdata_valid : OUT STD_LOGIC; -- .readdatavalid + avl_rdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); -- .readdata + avl_wdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); -- .writedata + avl_be : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- .byteenable + avl_read_req : IN STD_LOGIC; -- .read + avl_write_req : IN STD_LOGIC; -- .write + avl_size : IN STD_LOGIC_VECTOR(6 DOWNTO 0); -- .burstcount + local_init_done : OUT STD_LOGIC; -- status.local_init_done + local_cal_success : OUT STD_LOGIC; -- .local_cal_success + local_cal_fail : OUT STD_LOGIC; -- .local_cal_fail + oct_rdn : IN STD_LOGIC; -- oct.rdn + oct_rup : IN STD_LOGIC; -- .rup + seriesterminationcontrol : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); -- oct_sharing.seriesterminationcontrol + parallelterminationcontrol : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); -- .parallelterminationcontrol + pll_mem_clk : IN STD_LOGIC; -- pll_sharing.pll_mem_clk + pll_write_clk : IN STD_LOGIC; -- .pll_write_clk + pll_write_clk_pre_phy_clk : IN STD_LOGIC; -- .pll_write_clk_pre_phy_clk + pll_addr_cmd_clk : IN STD_LOGIC; -- .pll_addr_cmd_clk + pll_locked : IN STD_LOGIC; -- .pll_locked + pll_avl_clk : IN STD_LOGIC; -- .pll_avl_clk + pll_config_clk : IN STD_LOGIC; -- .pll_config_clk + dll_delayctrl : IN STD_LOGIC_VECTOR(5 DOWNTO 0) -- dll_sharing.dll_delayctrl + ); + END COMPONENT; + + -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v + COMPONENT ip_stratixiv_ddr3_uphy_16g_dual_rank_800 IS + PORT ( + pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk + global_reset_n : IN STD_LOGIC; -- global_reset.reset_n + soft_reset_n : IN STD_LOGIC; -- soft_reset.reset_n + afi_clk : OUT STD_LOGIC; -- afi_clk.clk + afi_half_clk : OUT STD_LOGIC; -- afi_half_clk.clk + afi_reset_n : OUT STD_LOGIC; -- afi_reset.reset_n + mem_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- memory.mem_a + mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba + mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck + mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n + mem_cke : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_cke + mem_cs_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_cs_n + mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm + mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n + mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n + mem_we_n : OUT STD_LOGIC; -- .mem_we_n + mem_reset_n : OUT STD_LOGIC; -- .mem_reset_n + mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq + mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs + mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n + mem_odt : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_odt + avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n + avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer + avl_addr : IN STD_LOGIC_VECTOR(28 DOWNTO 0); -- .address + avl_rdata_valid : OUT STD_LOGIC; -- .readdatavalid + avl_rdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); -- .readdata + avl_wdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); -- .writedata + avl_be : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- .byteenable + avl_read_req : IN STD_LOGIC; -- .read + avl_write_req : IN STD_LOGIC; -- .write + avl_size : IN STD_LOGIC_VECTOR(6 DOWNTO 0); -- .burstcount + local_init_done : OUT STD_LOGIC; -- status.local_init_done + local_cal_success : OUT STD_LOGIC; -- .local_cal_success + local_cal_fail : OUT STD_LOGIC; -- .local_cal_fail + oct_rdn : IN STD_LOGIC; -- oct.rdn + oct_rup : IN STD_LOGIC; -- .rup + pll_mem_clk : OUT STD_LOGIC; -- pll_sharing.pll_mem_clk + pll_write_clk : OUT STD_LOGIC; -- .pll_write_clk + pll_write_clk_pre_phy_clk : OUT STD_LOGIC; -- .pll_write_clk_pre_phy_clk + pll_addr_cmd_clk : OUT STD_LOGIC; -- .pll_addr_cmd_clk + pll_locked : OUT STD_LOGIC; -- .pll_locked + pll_avl_clk : OUT STD_LOGIC; -- .pll_avl_clk + pll_config_clk : OUT STD_LOGIC; -- .pll_config_clk + dll_delayctrl : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) -- dll_sharing.dll_delayctrl ); END COMPONENT; -- GitLab