diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd index f52a19dbfeadbcf709c410a14b45d22a5d9c239e..1bc78884b78807cc69c43931d05dfc7474540e8b 100644 --- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd +++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd @@ -99,7 +99,7 @@ ARCHITECTURE str OF mmp_dp_bsn_align_v2 IS CONSTANT c_mm_reg : t_c_mem := (1, ceil_log2(g_nof_streams), 1, g_nof_streams, '0'); SIGNAL reg_wr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0); - SIGNAL in_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); + SIGNAL stream_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); SIGNAL mm_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0); @@ -129,7 +129,7 @@ BEGIN in_reg => reg_wr ); - in_en_arr <= reg_wr; + stream_en_arr <= reg_wr; -- Use input BSN monitors for the first g_nof_input_bsn_monitors input -- streams, e.g. to support: @@ -209,7 +209,7 @@ BEGIN dp_clk => dp_clk, node_index => node_index, -- MM control - in_en_arr => in_en_arr, + stream_en_arr => stream_en_arr, -- Streaming input in_sosi_arr => in_sosi_arr, -- Output via local MM in dp_clk domain diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd index 7f1dfc2e3ed9dc5cfa83fc218c1fef0c014b59fa..e167b4cd1068ce6bd8235bf4de3fe95fa8e2ae2a 100644 --- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd +++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd @@ -144,8 +144,8 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS SIGNAL bsn_event : STD_LOGIC := '0'; -- pulse '1' triggers a BSN offset for an input SIGNAL bsn_event_ack_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL bsn_event_ack : STD_LOGIC; - SIGNAL in_en_event : STD_LOGIC := '0'; -- pulse '1' indicates that the input enables in in_en_arr have been updated - SIGNAL in_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'1'); -- default all inputs are enabled + SIGNAL stream_en_event : STD_LOGIC := '0'; -- pulse '1' indicates that the stream enables in stream_en_arr have been updated + SIGNAL stream_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'1'); -- default all streams are enabled BEGIN @@ -185,7 +185,7 @@ BEGIN -- Begin of stimuli FOR R IN 0 TO g_nof_repeat-v_diff_bsn-1 LOOP v_sync := sel_a_b(TO_UINT(v_bsn) MOD c_sync_period = c_sync_offset, '1', '0'); - proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_data_w, v_data, 0, 0, g_block_size, v_channel, v_err, v_sync, v_bsn, clk, in_en_arr(I), in_siso_arr(I), in_sosi_arr(I)); + proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_data_w, v_data, 0, 0, g_block_size, v_channel, v_err, v_sync, v_bsn, clk, stream_en_arr(I), in_siso_arr(I), in_sosi_arr(I)); v_bsn := INCR_UVEC(v_bsn, 1); v_data := v_data + g_block_size; proc_common_wait_some_cycles(clk, c_gap_size); -- create gap between frames @@ -208,7 +208,7 @@ BEGIN proc_common_wait_some_cycles(clk, 500); WHILE verify_extra_end /= '1' LOOP v_sync := sel_a_b(TO_UINT(v_bsn) MOD c_sync_period = c_sync_offset, '1', '0'); - proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_data_w, v_data, 0, 0, g_block_size, v_channel, v_err, v_sync, v_bsn, clk, in_en_arr(I), in_siso_arr(I), in_sosi_arr(I)); + proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_data_w, v_data, 0, 0, g_block_size, v_channel, v_err, v_sync, v_bsn, clk, stream_en_arr(I), in_siso_arr(I), in_sosi_arr(I)); v_bsn := INCR_UVEC(v_bsn, 1); bsn_event_ack_arr(I) <= '0'; IF I=c_event_input AND bsn_event='1' THEN @@ -238,8 +238,8 @@ BEGIN verify_dis_arr <= (OTHERS=>'0'); tb_state <= s_bsn_mis_aligned; - in_en_event <= '0'; - in_en_arr <= (OTHERS=>'1'); + stream_en_event <= '0'; + stream_en_arr <= (OTHERS=>'1'); ---------------------------------------------------------------------------- -- Wait until default verify test is done @@ -311,20 +311,20 @@ BEGIN tb_state <= s_disable_one_input; verify_dis_arr <= (OTHERS=>'1'); - in_en_event <= '1'; - in_en_arr(c_event_input) <= '0'; -- switch an input off + stream_en_event <= '1'; + stream_en_arr(c_event_input) <= '0'; -- switch an input off proc_common_wait_some_cycles(clk, 1); - in_en_event <= '0'; + stream_en_event <= '0'; proc_common_wait_some_cycles(clk, 100); verify_dis_arr <= (OTHERS=>'0'); proc_common_wait_some_cycles(clk, 2000); -- keep this input off for a while tb_state <= s_enable_inputs; verify_dis_arr <= (OTHERS=>'1'); - in_en_event <= '1'; - in_en_arr(c_event_input) <= '1'; -- switch this input on + stream_en_event <= '1'; + stream_en_arr(c_event_input) <= '1'; -- switch this input on proc_common_wait_some_cycles(clk, 1); - in_en_event <= '0'; + stream_en_event <= '0'; proc_common_wait_some_cycles(clk, 100); verify_dis_arr <= (OTHERS=>'0'); proc_common_wait_some_cycles(clk, 500); @@ -354,7 +354,7 @@ BEGIN gen_verify : FOR I IN g_nof_streams-1 DOWNTO 0 GENERATE -- Verification logistics - verify_en_arr(I) <= '1' WHEN rising_edge(clk) AND verify_dis_arr(I)='0' AND in_en_arr(I)='1' AND out_sosi_arr(I).sop='1' ELSE + verify_en_arr(I) <= '1' WHEN rising_edge(clk) AND verify_dis_arr(I)='0' AND stream_en_arr(I)='1' AND out_sosi_arr(I).sop='1' ELSE '0' WHEN rising_edge(clk) AND verify_dis_arr(I)='1'; -- verify enable after first output sop -- Ease in_sosi_arr monitoring @@ -413,7 +413,7 @@ BEGIN dp_clk => clk, -- Control node_index => node_index, - in_en_arr => in_en_arr, + stream_en_arr => stream_en_arr, -- Streaming input in_sosi_arr => in_sosi_arr, -- Output via local MM in dp_clk domain