diff --git a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
index 744a446edfee9a64633da692507284086f48ab4f..4d67b776a75f63bc233269814626a7b24bea91d2 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
@@ -27,9 +27,9 @@
 --   When the io_ddr is starting a new write access, then the write input FIFO
 --   gets filled. The filling starts dependent on:
 --
---   . g_mode = "VALID" : immediately start filling on next valid data
---   . g_mode = "SOP"   : start filling on next sop
---   . g_mode = "SYNC"  : start filling on next sync
+--   . g_mode = "VAL" : immediately start filling on next valid data
+--   . g_mode = "SOP" : start filling on next sop
+--   . g_mode = "SYN" : start filling on next sync
 --
 --   . g_use_channel = TRUE : start filling when channel matches g_start_channel
 
@@ -41,7 +41,7 @@ USE dp_lib.dp_stream_pkg.ALL;
 
 ENTITY io_ddr_driver_flush_ctrl IS 
   GENERIC (
-    g_mode          : STRING := "VALID";  -- "VALID", "SOP", "SYNC"
+    g_mode          : STRING := "VAL";  -- "VAL", "SOP", "SYN"
     g_use_channel   : BOOLEAN := FALSE;
     g_start_channel : NATURAL := 0;
     g_nof_channels  : POSITIVE := 1
@@ -79,17 +79,17 @@ BEGIN
 
   -- Flush disable control
   no_channel: IF g_use_channel=FALSE GENERATE
-    gen_valid : IF g_mode="VALID" GENERATE flush_dis <= wr_sosi.valid; END GENERATE;
-    gen_sop   : IF g_mode="SOP"   GENERATE flush_dis <= wr_sosi.sop  ; END GENERATE;
-    gen_sync  : IF g_mode="SYNC"  GENERATE flush_dis <= wr_sosi.sync ; END GENERATE;
+    gen_valid : IF g_mode="VAL" GENERATE flush_dis <= wr_sosi.valid; END GENERATE;
+    gen_sop   : IF g_mode="SOP" GENERATE flush_dis <= wr_sosi.sop  ; END GENERATE;
+    gen_sync  : IF g_mode="SYN" GENERATE flush_dis <= wr_sosi.sync ; END GENERATE;
   END GENERATE;
     
   use_channel: IF g_use_channel=TRUE GENERATE
     channel <= TO_UINT(wr_sosi.channel(c_channel_w-1 DOWNTO 0));
     
-    gen_valid : IF g_mode="VALID" GENERATE flush_dis <= '1' WHEN wr_sosi.valid='1' AND channel=g_start_channel ELSE '0'; END GENERATE;
-    gen_sop   : IF g_mode="SOP"   GENERATE flush_dis <= '1' WHEN wr_sosi.sop  ='1' AND channel=g_start_channel ELSE '0'; END GENERATE;
-    gen_sync  : IF g_mode="SYNC"  GENERATE flush_dis <= '1' WHEN wr_sosi.sync ='1' AND channel=g_start_channel ELSE '0'; END GENERATE;
+    gen_valid : IF g_mode="VAL" GENERATE flush_dis <= '1' WHEN wr_sosi.valid='1' AND channel=g_start_channel ELSE '0'; END GENERATE;
+    gen_sop   : IF g_mode="SOP" GENERATE flush_dis <= '1' WHEN wr_sosi.sop  ='1' AND channel=g_start_channel ELSE '0'; END GENERATE;
+    gen_sync  : IF g_mode="SYN" GENERATE flush_dis <= '1' WHEN wr_sosi.sync ='1' AND channel=g_start_channel ELSE '0'; END GENERATE;
   END GENERATE;
 
   p_reg : PROCESS(rst, clk)