diff --git a/libraries/base/common/src/vhdl/common_pulse_extend.vhd b/libraries/base/common/src/vhdl/common_pulse_extend.vhd index cb9909dc91930a0afab853887b0602f06cb916d5..1d15bb810fe0859a0e1e1f2356963d0d69993dee 100644 --- a/libraries/base/common/src/vhdl/common_pulse_extend.vhd +++ b/libraries/base/common/src/vhdl/common_pulse_extend.vhd @@ -22,6 +22,7 @@ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.numeric_std.ALL; +USE work.common_pkg.ALL; -- Purpose: Extend the active high time of a pulse -- Description: @@ -34,7 +35,8 @@ ENTITY common_pulse_extend IS g_rst_level : STD_LOGIC := '0'; g_p_in_level : STD_LOGIC := '1'; g_ep_out_level : STD_LOGIC := '1'; - g_extend_w : NATURAL := 1 + g_extend_w : NATURAL := 1; + g_nof_cycles : NATURAL := 1 --1 = use maximum determined by g_extend_w ); PORT ( rst : IN STD_LOGIC := '0'; @@ -48,7 +50,9 @@ END common_pulse_extend; ARCHITECTURE rtl OF common_pulse_extend IS - SIGNAL cnt : STD_LOGIC_VECTOR(g_extend_w-1 DOWNTO 0) := (OTHERS => '0'); + CONSTANT c_cnt_w : NATURAL := sel_a_b(g_nof_cycles>1, ceil_log2(g_nof_cycles), g_extend_w); + + SIGNAL cnt : STD_LOGIC_VECTOR(c_cnt_w-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL nxt_cnt : STD_LOGIC_VECTOR(cnt'RANGE); SIGNAL cnt_is_0 : STD_LOGIC; SIGNAL i_ep_out : STD_LOGIC := g_rst_level; @@ -85,6 +89,9 @@ BEGIN nxt_cnt <= STD_LOGIC_VECTOR(TO_UNSIGNED(1,cnt'LENGTH)); ELSIF cnt_is_0='0' THEN nxt_cnt <= STD_LOGIC_VECTOR(UNSIGNED(cnt) + 1); + IF g_nof_cycles>1 AND UNSIGNED(cnt)=g_nof_cycles-1 THEN + nxt_cnt<=(OTHERS=>'0'); + END IF; END IF; END PROCESS;